KR100272568B1 - Apparatus and method of switching cell in the private branch exchange - Google Patents

Abstract

The present invention relates to a cell switching device and a method of a private exchange. In particular, the internal switch structure is simple when interfacing with an ATM back-bone exchange in the future by using an Asynchronous Transfer Mode (ATM) scheme. A cell switching device and method for easily interfacing with accommodation of a cell header conversion device.

The present invention is composed of a node cell switching unit for switching the ATM cell (Cell) input from each node, and a standard cell switching unit for switching the ATM standard cell input from the ATM backbone switch, wherein each of the input cells Provided is a cell switching device of a private exchange, characterized in that switching to a node cell switching unit or a standard cell switching unit according to the destination to be switched.

The present invention also provides a method for receiving an ATM cell, analyzing a header of the cell, storing the cell in a corresponding memory according to the analysis of the header of the cell, and storing the cell stored in the memory at a destination. According to another aspect of the present invention, there is provided a cell switching method of a private exchange, comprising the step of switching accordingly.

Description

Cell switching device and method of private exchange

The present invention relates to a cell switching device and a method of a private exchange. In particular, the internal switch structure is simple when interfacing with an ATM back-bone exchange in the future by using an Asynchronous Transfer Mode (ATM) scheme. A cell switching device and method for easily interfacing with accommodation of a cell header conversion device.

In general, a method for transmitting voice information by the exchange time-divisionally transmits 64 Kbps voice data to a High Way (HW) using a Time Division Multiplex (TDM) scheme. At this time, in order to implement non-blocking switching, the entire HW must be concentrated and exchanged with a global switching block. At this time, the clock synchronization between the cabinets (Cabinet) must be matched, and if the switch block (Block) by implementing the matrix (Matrix) method is a complicated configuration.

1 is a view showing the configuration and connection relationship of the switching device of the conventional private exchange.

As shown in FIG. 1, when the switching unit accommodates 1024 subscribers in each cabinet 1 in the conventional switching device, 2M HW x 2N pieces (transmission HW) for exchange into a switch cabinet 2 32 HWs (32 receiving HWs) must be connected, and 64 2M HWs are needed for each increase in the number of cabinets when the total number of subscribers increases, that is, when the number of cabinets 1 increases. Here, M of 2M is in mega units, and 64 HW are required for 1024 subscribers. In addition, the private exchange has a function of converting a time switch (T-Switch) applied to the existing private exchange into a cell switch applying the ATM method.

2 is a block diagram showing a configuration of an HW switch that accommodates 4096 subscribers using a conventional TDM scheme.

FIG. 2 illustrates a TDM HW switch that is currently implemented. In the case of configuring a TDM switch using 2M HW, the TDM switch should be configured in a 128 × 128 matrix form. Since it is difficult, it multiplexes 4 2M HW and converts into 8M HW. In addition, the actual TDM switch matrix is represented by a 4 × 4 matrix using an 8M TDM switch. Since eight 2M HWs connected to four MUXs (muxes) 3 each have 256 subscribers, four mux multiplex 1024 subscriber HWs to eight 8M HWs. Such a conventional switch realizes high-speed switching by multiplexing 2M HW in order to configure a large-capacity exchanger, demultiplexes the multiplexed 2M HW into 2M HW, and transmits voice data to an actual subscriber.

Such a conventional technology has to have a multi-stage shelf or multiple cabinets only for implementing a switch matrix for realizing switching, and voice data of each subscriber uses a 2M HW for every 32 subscribers. Because the switch must be concentrated on this configured shelf, it is difficult to match the synchronization of the system's overall clock within a large switch block, and if the synchronization is not matched, the exchange can lose data during operation and the switch block is difficult to configure. There was a losing problem.

In addition, when the TDM type switch is connected to a broadband information communication network, there is a problem in that a terminal adapter must be additionally provided.

An object of the present invention has been made in view of the above-mentioned problems of the prior art, a cell of a private exchange to configure a switching device using a cell switching method to switch between each cabinet, and also to switch with an ATM backbone exchange. To provide a switching device and method.

The present invention for achieving the above object is composed of a node cell switching unit for switching the ATM cell (Cell) input from each node, and a standard cell switching unit for switching the ATM standard cell input from the ATM backbone switch, Provided is a cell switching device of a private exchange, characterized in that the switching to the node cell switching unit or the standard cell switching unit according to the destination to which each input cell is switched.

The present invention also provides a method for receiving an ATM cell, analyzing a header of the cell, storing the cell in a corresponding memory according to the analysis of the header of the cell, and storing the cell stored in the memory at a destination. According to another aspect of the present invention, there is provided a cell switching method of a private exchange, comprising the step of switching accordingly.

Preferably, the node cell switching unit includes a plurality of input cell controllers for analyzing the ATM cells of an internal cell format inputted from each node and dividing the cells according to a destination to be switched, and each node outputted from the input cell controller. A common memory unit for receiving and storing a cell to be switched to and a cell converted into an internal cell format, a header of a cell converted into an internal cell format by the input cell control unit and the standard cell switching unit; A schedule first-in first-out unit for storing the destination address to be output, a common memory output control unit for analyzing the headers outputted from the schedule first-in first-out unit and controlling the cells stored in the common memory unit to be output for each destination node to be switched; The cell stored in the memory unit is switched to serve as an interface for output to the outside It is made to the output buffer control section of the can. The standard cell switching unit includes a first header conversion table having information for converting a standard ATM cell input from an ATM backbone exchanger into an internal cell format, and a second header having information for converting a cell of an internal cell format into a standard ATM cell. A standard cell input control unit which analyzes a standard ATM cell input from an ATM backbone exchanger by referring to a conversion table and the first header conversion table, and selectively converts a cell into an internal cell format according to a destination to be switched; A standard cell common memory unit for storing a cell output from the standard cell input control unit and a cell to be switched from the node cell switching unit to an ATM backbone exchanger, and an internal output unit from the standard cell common memory unit with reference to the second header conversion table; And a standard cell output control unit for converting a cell of a cell format into a standard ATM cell. In addition, the step of analyzing the cell header checks the alignment of the cells and examines the SA (Standard ATM; Standard ATM) bits of the third byte of the cell header to determine whether the cell is to be transmitted to each node or the cell to be transmitted to the ATM backbone exchange The storing of the cells in the memory may be performed by selectively converting a cell header according to a destination to be switched and storing the cells.

According to the present invention as described above, since the auto-routing (Auto-Routing) function is mainly implemented in the existing ATM switch structure, the switching structure is simplified, and there is an advantage of easy capacity neutralization.

1 is a view showing a configuration and a connection relationship of a switching device of a conventional private exchange.

Figure 2 is a block diagram showing the configuration of a HW switch that accommodates 4096 subscribers using a conventional TDM scheme.

3 is a block diagram showing a configuration of an exchange system according to the present invention;

Figure 4 is a block diagram showing the internal configuration of the switching device provided in each node according to the present invention.

Figure 5 is a block diagram showing the internal configuration of the node interfaced with the ATM backbone switch in accordance with the present invention.

6 is a block diagram illustrating an internal configuration of a switch block of a node interfaced with an ATM backbone switch according to the present invention.

7 illustrates the configuration of an internal cell format and a standard ATM cell in accordance with the present invention.

8 illustrates the bits defined in the VCI in the internal cell format according to the present invention.

9 is a block diagram showing the internal structure of a header conversion table according to the present invention;

Explanation of symbols on the main parts of the drawings

16: standard cell input control unit 17: input cell control unit

18: first header conversion table 19: second header conversion table

20 cell disassembly and assembly 21 standard cell common memory

22: common memory unit 23: schedule first-in-first-out

24: common memory output control unit 25: standard cell output control unit

26: output buffer control unit 30: output first-in, first-out unit

100: node cell switching unit 200: standard cell switching unit

Hereinafter, the configuration and operation according to an embodiment of the present invention will be described with reference to the accompanying drawings.

3 is a block diagram showing a configuration of an exchange system according to the present invention. Figure 4 is a block diagram showing the internal configuration of the switching device provided in each node according to the present invention. 5 is a block diagram showing an internal configuration of a node interfaced with an ATM backbone switch according to the present invention. 6 is a block diagram illustrating an internal configuration of a switch block of a node interfaced with an ATM backbone switch according to the present invention. 7 is a diagram illustrating the configuration of an internal cell format and a standard ATM cell according to the present invention. 8 is a diagram illustrating bits defined in a VCI in an internal cell format according to the present invention. 9 is a block diagram showing an internal configuration of a header translation table according to the present invention.

Referring to FIG. 3, each unit represented by node (NODE) -x internally performs a local switch function inside node-x, and a node in a global call with another node (NODE). The cell switching device configured at -5 is used to implement a global currency. At this time, the node is a block existing within the minimum switching unit and is the minimum switching block accommodating 1024 subscribers.

And, the ATM cell data transmission from each node (node-1 to node-4) to the node-5 configured with the global switch is transmitted in a SONET method having a transmission rate of 155M bps. Here, sonnet is a standard for ATM transmission. Synchronization of the cell data transmitted through the sonnet uses an asynchronous method in which the reference clock is restored by the devices at both ends connected through the UTP cable. Therefore, when configuring a large-scale system, it is necessary to configure a separate synchronization circuit to synchronize each node. This eliminates the need for synchronizing the entire system as in an exchange implemented with a conventional TDM scheme. In particular, since the cell switching method is used, the data of all subscribers configured in one system is recognized only as a cell input to a switch block requesting routing from a switch point of view, thereby enabling a system that is not sensitive to system synchronization. Link connection between each node can use an optical module and UTP cable (Cable) can be used in a distributed manner without operating the switching node in one place.

Referring to FIG. 4, the switch block of each node receives an HW and converts the HW to Cell Conversion Block (H2CCB) 7 into an ATM cell having an internal cell format. A UTP control block (UCB) 8 for outputting a cell through a UTP cable, and a UTP interface 9 configured to interface with the front end of the switching device.

The switch block of each node receives 32 HW, and the cell converting unit 7 converts the ATM cell into an ATM cell, which is transmitted to the UTP interface 9 via the UTP control unit 8.

At this time, the cell conversion unit 7 does not convert to a standardized ATM cell but converts to an internally defined internal cell format.

As shown in FIG. 7, the internal cell format uses a cell header 2 bytes as an output port number (OPN) for cell switching in an auto-routing manner inside the switch. For this output port number, the destination node number of each node is recorded. For example, when a cell inputted from node-1 is transmitted to node-4, the first byte of the OPN becomes "0000 0000" and the second byte is " 0000 1000 ". That is, only Node-4 is set to '1'. The cell in which the OPN is recorded in this way is transmitted to the UTP interface 9 through the UTP control unit 8. In addition, SA (Standard ATM) is a bit for recording whether or not to convert to a standard ATM cell. If set to '1', it is converted to a standard ATM cell and transmitted to an ATM backbone exchange.

As shown in FIG. 8, a destination HW number designates one of 32 HWs in a corresponding node, and a destination channel number designates one of 32 time-divided channel numbers in the designated HW. It is supposed to specify.

As shown in FIG. 5, a node interfaced with an ATM backbone switch includes a plurality of first to fourth UTP interfaces 10 to 13, and a switch block 14 for switching between each node and also switching to an ATM backbone switch. ) And a standard ATM interface unit 15 that interfaces with the ATM backbone exchange. In this case, the plurality of UTP interface unit can be expanded according to the number of nodes.

Cells of the internal cell format inputted from each node to the plurality of UTP interface units 10 to 13 are switched in the switch block 14 to be transmitted to each node or ATM backbone exchange depending on the destination.

In addition, 16-bit transmission is performed between the plurality of UTP interfaces 10 to 13 and the switch block 14 using UTOPIA 2 (Universal Test Of Physical Interface of ATM 2) standard, and 50 MHZ clock (Clock) is used. In the case of operating by), the switch block 14 must process one cell within one cycle of 35 clocks.

Referring to FIG. 6, a switch block of a node interfaced with an ATM backbone switch is a switching device according to the present invention, including a node cell switching unit 100 for switching an ATM cell input from each node, and an ATM. It consists of a standard cell switching unit 200 for switching the ATM standard cell input from the backbone exchange.

The node cell switching unit 100 analyzes an ATM cell of an internal cell format inputted from each node, and outputs a cell according to a destination to be switched and outputs a plurality of input cell control blocks (hereinafter, abbreviated as ICCB). A common memory unit for receiving and storing a cell to be switched to each node output from the input cell control unit and a standard cell switching unit and converted into an internal cell format; A schedule FIFO for storing a cell header output from the input cell control unit and a header of a cell input to the standard cell switching unit and converted into an internal cell format; A common memo that analyzes a schedule FIFO) 23 and a header output from the schedule first-in-first-out unit to control the cells stored in the common memory unit to be output for each switching destination node Output CM Control Block (hereinafter, abbreviated as OCMCB) 24 and a plurality of output buffer controllers serving as an interface for switching cells stored in the common memory unit to be output to the outside. Block (hereinafter abbreviated as OBCB) 26 and an output first-in first-out (Out FIFO) 30 for storing cells output from the output buffer control unit.

In addition, the standard cell switching unit 200 includes a first header conversion table and a first header conversion table (hereinafter referred to as a first HXT) having information for converting a standard ATM cell input from an ATM backbone exchanger into an internal cell format. 18, a second header conversion table (hereinafter, abbreviated to second HXT) 19 having information for converting a cell of an internal cell format into a standard ATM cell; 1 Standard ATM cell input control block for analyzing a standard ATM cell inputted from an ATM backbone exchanger by referring to a header conversion table and selectively converting a cell into an internal cell format according to a destination to be switched. Common cell for storing a cell output from the standard cell input control unit and a cell to be switched from the node cell switching unit to the ATM backbone switch (hereinafter abbreviated as SAICB). Standard ATM cell (hereinafter abbreviated as CMSA) 21 and a standard cell output control unit for converting a cell of an internal cell format output from a standard cell common memory unit into a standard ATM cell with reference to the second header conversion table. ATM Output cell Control Block (hereinafter abbreviated to SAOCB) 25 and a cell having a predefined VCI (Virtual Channel Identifier) input from the SAICB 16, disassembled, assembled and outputted Segment And Reassembly (hereinafter abbreviated as SAR) 20.

The present invention configured as described above is primarily based on a distributed processing structure since the main focus is on the non-blocking switch configuration of the cell switch type and the expansion of subscribers. In addition, a simple switch block is constructed by mainly configuring an auto-routing function using OPN information included in a cell header among functions configured in an existing ATM switch. And the method of displaying the respective subscriber information of each node is as described in FIG. 7, and the representation method of the number information of the other party is recorded in the VCI of the internal cell format as shown in FIG.

Referring to the operation of the switching device according to the present invention made as described above are as follows.

First, when an ICCB receives an ATM cell of an internal cell format from each node, the ICCB checks the alignment of the cell to determine whether the cell is normally composed of 53 bytes, and then checks the third byte of the cell header. Checks the SA (Standard ATM) bit and distinguishes whether the input cell is a cell to be transmitted to a standard ATM backbone exchange or a cell to be transmitted to each node. The cell to be stored is stored in the CM and the cell to be transmitted to the ATM backbone exchange is stored in the CMSA. On the other hand, the switching device according to the present invention has a 5 x 5 ATM switch structure, the ICCB is a structure that is input by multiplexing each of the four nodes and has a structure for connecting up to 16 nodes. At this time, the switch structure and the ICCB is much easier to expand than the conventional T-switch. This ICCB can handle 622 Mbps and also provide 155 Mbps transfers to ATM backbone exchanges. Cells that enter the ICCB use a 16-bit bus and are expanded to 128 bits inside the ICCB. The extended 128 bits correspond to 16 bytes as bytes, and only 48 bytes of payload of a cell are stored in the CM. In this case, when 48 bytes are extended to 128 bits, one cell becomes 128 x 3 = 384 bits. Thus, in order to store one cell in the memory, the memory can be accessed three times. Here, the reason for extending to 128 bits is that the minimum time to process one cell is allowed because only 6 clocks per block are allowed to process cells input to four ICCBs and one SAICB for 34 clocks. To secure. Here, four ICCBs and one SAICB are time-divided to access the CM. Four ICCBs and one SAICB are configured to store cells in a dual-buffer format internally, and the finished cell writes the cells to the CM at the time allowed in its block. When the payload of the cell is stored in the CM, the cell header is stored as the schedule FIFO, which includes the address of the CM in which the payload portion of the header stored in the current schedule FIFO is written. If there is a cell to be written to the ATM backbone exchange in the same manner, the extended data is written to the CMSA using the same time and data bit extension method as described above. At this time, a block that performs the function of the schedule FIFO is configured inside the CMSA.

The switching of cells stored in the CM is performed by the OCMCB, which must process one cell at six clocks of 50 MHz. The OCMCB uses the OPN of the header information written in the schedule FIFO to decide whether to write the cell currently stored in the CM to one OBCB out of the four OBCBs, and applies the address and read signal to the CM. The write signal is applied to the dual buffer configured in FIG. If a cell stored in the CM requests a plurality of output nodes, that is, when a plurality of node bits are set to '1' in the OPN of the cell header, data and writes of the same CM are written to all corresponding OBCBs. ) Apply a signal. The OBCB has a dual buffer inside and performs a 16-bit interface with an output FIFO configured outside the switch. At this time, the size of the data bus used inside the switch block is 128 bits, whereas the data bus of the output FIFO is 16 bits, so the OBCB converts the data from 128 bits to 16 bits. In order to perform this process, OBCB has a dual buffer internally. During processing of cells input to OBCB, the input cells are temporarily stored in one of the dual buffers, and the buffer used for the current data bit conversion is used during the next cycle. Operates in a structure used to store data input. As described above, the present invention configures a common memory and an output buffer type ATM in a voice service oriented switch, thereby preventing a phenomenon in which switch efficiency is deteriorated when the same output generated in the input buffer type switch is requested.

The method of interfacing with an ATM backbone exchange is described, providing an efficient interface with an existing ATM exchange, and providing a method of connecting an exchange that mainly provides voice services to a broadband information network without requiring a new interface. Provided is a method for easily increasing the dose. The physical medium is connected to an ATM backbone exchanger in the form of OC-3C (155 Mbps) or OC-12C (622 Mbps). SAICB is connected to the existing standard ATM switch and converts a cell input into a standard cell structure into an internal cell form. As shown in FIG. 7. In the standard cell form, only 4096 virtual channel connections (VCCs) are used using only 12 bits among the VCIs without using the entire virtual path identifier (VPI) and the virtual channel identifier (VCI). Restrict services to the form they provide. In this case, the VCI used may be used in the same form as the case where the ATM backbone exchange includes a plurality of Node-5s as shown in FIG. 3 and increases subscriber capacity using bits defined in an internal cell format. . That is, when the ATM backbone exchange manages all the subscriber information of the system managed by Node-5, the limit of the switch structure shown in FIG. 6, that is, the 5 x 5 switch structure is exceeded (5 x N) x (5 x N) performs the same function as the switch structure. At this time, the system is strictly configured as a blocking method, but the non-blocking method does not have a significant meaning when the system is expanded to a large capacity. The SAICB checks the alignment of the cells input from the ATM backbone exchanger, converts the header of the input cells into the internal cell form using the header conversion information stored in the first HXT using the VCI, and expands the data to 128 bits to store them in the CM do. The header converted into an internal cell form while storing the data in the CM is stored in the schedule FIFO, and then the switch processes the cell and the method for processing the cell input to the ICCB. In order to perform such cell header conversion, a call must be initially set up using a signaling cell in an ATM backbone exchanger, and the signal cell is predefined in advance by assigning a specific VCI. When a cell with a predefined VCI is inputted, the SAICB is packetized in an externally configured SAR block and analyzed by a higher layer protocol. The first HXT modifies the region corresponding to the VCI for header conversion of the cell input with the specific VCI. Referring to FIG. 9, if there is a cell to be transmitted to the ATM backbone exchange in each node, the header of the cell should be converted into a standard cell form. Since the header change information is stored in the second HXT and all the header change information of each node must be accommodated, the address area has a 16-fold address area to display all 16 nodes as compared to the first HXT. When the SA of the header is set to '1' among the cells input to the ICCB, the OPN is not used to designate the destination node but is used as a bit that informs the position of the node currently transmitting.

As described above, if the cell switching device is configured in the form of emphasizing only the self routing function among the functions of the actual ATM switch, a cell switch having a configurable structure can be implemented by a simple method. By configuring a switching device interfaced to a standard ATM backbone exchange in such a basic function, a terminal interface module for a broadband information communication network is configured inside the system, or when a broadband information network service is accommodated using an existing HW, The connection can be easily provided.

As described above, the present invention uses cell switching to switch, so that the capacity can be easily increased in the large-capacity switching system than the conventional TDM method, and the system synchronization generated as the system capacity is increased is also used. This makes it easier to synchronize the system, so that the switch structure can be easily expanded, thereby increasing the capacity of subscribers.

In addition, the present invention has the effect of providing a service of a broadband information communication network without having to provide an additional device at the interface with the broadband information communication network.

Claims (6)

A node cell switching unit for switching ATM cells input from each node, Consists of a standard cell switching unit for switching the ATM standard cell input from the ATM backbone exchange, And switching to a node cell switching unit or a standard cell switching unit according to a destination to which each inputted cell is switched. The method of claim 1, The node cell switching unit comprises: a plurality of input cell controllers for analyzing the ATM cells of an internal cell format inputted from each node and dividing the cells according to a destination to be switched; A common memory unit for receiving and storing a cell to be switched to each node output from the input cell controller and a standard cell switching unit, and converting a cell converted into an internal cell format; A schedule first-in first-out unit for storing a header of a cell converted into an internal cell format and an output destination address by the input cell controller and the standard cell switching unit; A common memory output controller configured to analyze the header output from the schedule first-in-first-out unit and to output a cell stored in the common memory unit for each destination node to be switched; And a plurality of output buffer controllers serving as an interface for switching cells stored in the common memory unit to be output to the outside. The method of claim 1, The standard cell switching unit comprises: a first header conversion table having information for converting a standard ATM cell input from an ATM backbone exchanger into an internal cell format; A second header conversion table having information for converting a cell of an internal cell format into a standard ATM cell; A standard cell input control unit for analyzing a standard ATM cell inputted from an ATM backbone exchanger by referring to the first header conversion table and selectively converting a cell into an internal cell format according to a destination to be switched; A standard cell common memory unit configured to store a cell output from the standard cell input controller and a cell to be switched from the node cell switching unit to an ATM backbone exchanger; And a standard cell output control unit for converting a cell of an internal cell format output from a standard cell common memory unit into a standard ATM cell with reference to the second header conversion table. Receiving an ATM cell; Analyzing the header of the cell; Storing the cell in a corresponding memory according to the analysis of the cell header; And switching a cell stored in the memory according to a destination. The method of claim 4, wherein The step of analyzing the cell header is to check the alignment of the cells and examine the SA bits of the third byte of the cell header to distinguish whether the cell is to be transmitted to each node or whether the cell is to be transmitted to the ATM backbone exchange. Cell switching method. The method of claim 4, wherein The storing of the cell in the memory may include selectively converting a cell header according to a destination to be switched to store the cell.