KR100233679B1 - An apparatus for interfacing medium speed subscriber to atm switch - Google Patents

Abstract

The present invention relates to a medium speed subscriber matching device for connecting a medium speed subscriber (DS3 class speed subscriber) to an ATM switching network in an ATM switch.

The present invention receives ATM cell data from the DS3 frame processing means 110 and the DS3 frame processing means through the receiving FIFO, obtains the VPI index and the VCI index from the index table from the VPI / VCI of the corresponding cell, and multiplexes the ATM cells. Finds and attaches a routing header from the routing table by the multiplexer 122, the user parameter control processor 140, and the VPI / VCI index received from the multiplexer, and transfers the corresponding cell according to the output of the user parameter control processor. And receiving the ATM cell from the routing processing means 150, the switch matching means 160, and the switch matching means, which perform the discarding, and the corresponding cell extracts the VPI / VCI index from the index table by VPI / VCI and then links the cell. A demultiplexing unit 126 for assigning a number and demultiplexing to a transmission FIFO of a corresponding link, and an OAM cell dropped from the routing processing unit; The matching unit 130 outputs an OAM cell to the demultiplexer, transmits and receives an IPC cell to and from the switch matching unit, and controls the operation of each block.

Description

Intermediate subscriber matching device at ATM switch

The present invention relates to a medium speed subscriber matching device for connecting a medium speed subscriber (DS3 class speed subscriber) to an ATM switching network in an ATM switch.

In general, an ATM switch is a system that performs a node function to connect an ATM network, an ATM network, or a subscriber to an ATM network in the case of a public network using an ATM method. A virtual channel (VC) switch and a virtual It is divided into a route exchange (VP). The ATM switching system is implemented with a subscriber matching device, a switch network, a relay line matching device, and the like and processors for controlling them.

The subscriber matching device performs traffic control function according to user parameter control (UPC) along with UNI physical layer matching, ATM layer processing, signal cell and user cell separation transmission, header change, and OAM processing. Subscriber matching devices can also include low- and medium-speed subscriber matching for existing subscriber services, as well as ATM subscribers. The low-speed subscriber matching provides DSIE (approximately 2.048 Mbps) level access, and the subscriber registration feature provides DS3 (about 44.736 Mbps) level of connectivity.

ATM switch networks are realized by multiple stages of unit switches capable of high-speed switching of hundreds of Mbits. ATM unit switches are divided into input buffers, output buffers, common memories, common buses, cross point switches, and the like according to the configuration.

ATM trunk line matching device performs NNI interface, physical layer processing, ATM layer processing, OAM processing, and traffic control function works in conjunction with switch network. It also includes interworking functions with other networks such as existing telephone network, narrowband (N) -ISDN, packet network, frame relay network, etc.

However, in the ATM switch, a matching device for connecting the intermediate subscriber to the switch has not been specifically presented in the related art, and thus an apparatus for implementing the matching device is required.

Accordingly, an object of the present invention is to provide an intermediate subscriber matching device for accessing an existing DS3 level intermediate subscriber in an ATM switch.

In order to achieve the above object, the apparatus of the present invention, the DS3 frame processing unit for extracting the ATM cell from the DS3 frame input from the subscriber side, discards the invalid cell, and maps the received ATM cell to the DS3 frame to transmit to the subscriber side; ; ATM cell transmission processing means for receiving ATM cell data from the DS3 frame processing unit through a transmission FIFO, obtaining a VPI index and a VCI index from an index table by VPI / VCI of a corresponding cell, and multiplexing ATM cells; A user parameter control processor configured to receive a VPI / VCI index from the ATM cell transmission processing unit and process user parameter control on a connection of a corresponding cell to determine transfer or discard of the corresponding cell; A routing processing unit for finding and attaching a routing header from a routing table by a VPI / VCI index received from the ATM cell transmission processing unit, and transferring and discarding a corresponding cell according to an output of the user parameter control processing unit; After receiving the ATM cell of the predetermined byte with the routing header inputted from the routing processor, CRC is added to form a cell of a predetermined size, connected to the switch network, and then the CRC is checked from the data received from the switch network. A switch matching unit for outputting an ATM cell of bytes; ATM cell reception processing for receiving an ATM cell from the switch matching unit, extracting a VPI / VCI index from an index table by VPI / VCI of a corresponding cell, assigning a link number of the corresponding cell, and demultiplexing to a receiving FIFO of the link. Way; And receiving an OAM cell dropped from the routing processing unit, outputting an OAM cell to the ATM cell receiving processing unit, transmitting and receiving an IPC cell with the switch matching unit, and matching to control the operation of each block and each block. Characterized in that the control unit is provided.

1 is a block diagram showing a general ATM switch.

Figure 2 is a block diagram showing a medium to low speed subscriber matching device according to the present invention.

FIG. 3 is a block diagram showing an ATM transmission layer processing apparatus of the medium subscriber registration device shown in FIG. 2. FIG.

4 is a format diagram showing a structure of a reception index table.

5 is a diagram showing the structure of a reception cam interface register;

6 is a diagram illustrating a format of an OAM cell to be dropped;

7 shows a routing field for an OAM cell.

8 illustrates a routing field for a point-to-point access cell.

9 illustrates a routing field for multicasting.

FIG. 10 is a block diagram showing an ATM receiving layer processing apparatus of the medium subscriber registration device shown in FIG.

* Explanation of symbols for main parts of the drawings

110: DS3 frame processing unit 122: multiplexing unit

126: demultiplexer 130: matching controller

140: UPC processing unit 150: routing processing unit

160: switch matching unit

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Broadband Telecommunication Network (B-ISDN) is a high-speed Telecommunication Network that accommodates not only voice and low-speed data communications supported by narrowband Telecommunication Networks, but also high-speed data transmission, still picture, moving picture, and video conferencing services. The ATM switching system used in the broadband telecommunication network is composed of UNI / NNI matching and access switching module to connect between ALS and ATM local switching subsystem (ALS) that provides subscriber and other services with subscribers or other exchanges. It consists of an ATM Central Switching Subsystem (ACS) to provide the services of the switching system. At this time, the UNI / NNI accessible in the ATM switching system includes 155Mbps STM-1 level UNI, DS3 level, DS1E medium and low speed UNI, and 155Mbps STM-1 level and 622Mbps STM-4 level NNI, respectively.

As shown in FIG. 1, such an ATM switch is divided into a plurality of ATM Local Switching / Subscriber subsystems (ALS) 10-0 to 10-n and an ATM central switching subsystem (ACS). ATM Central Switching Subsystem; The ALS 10-0 to 10-n includes a plurality of subscriber interface modules (SIMs), an access switching network module (ASNM: 17), and a subscriber call processing processor (SCP: 18). In the embodiment of the present invention, the subscriber module (SIM) is a medium to low speed subscriber module (MSIM: 12-0 to 12-n) for connecting a medium to low speed subscriber, and may connect three DS3 classes. 12-0 ~ 12-n) is a medium speed line board (MSLA: 14-0,14-1,14-2) that provides three DS3 level connection lines and IMI connection by connecting three links. It consists of a medium speed subscriber matching device (MSAA: 16).

An Access Switching Network Module (ASNM) accesses a plurality of medium and low speed subscriber modules (MSIM: 12-0 to 12-n) as well as subscriber call control modules that control the ATM local switching subsystem. It is connected to the parser (SCP: Subscriber, Call Processor) 18 and IMI.

In addition, the ACS 20 is composed of an interconnection switch network module (ISNM) 22 and an operation preservation processor (OMP: 24), and the OMP 24 is not shown in the drawings, but the cell multiplexing and deactivation is performed. Connected to the multiplexing block (CMDH: Cell Mux / Demux H / W Assembly), Sbus interface processor communication board assembly (SPCA), ATM main processor block (AMPA), and AMPA Disk, cartridge tape CT, and the like.

As shown in FIG. 2, the middle speed subscriber matching device of the present invention includes a DS3 frame processor 110, an ATM processor 120, a UPC processor 140, a routing processor 150, a match controller 130, and a switch. It is composed of a matching unit 160. The DS3 frame processor 110 is composed of three physical layer chips (PLPP) 112, 114, and 116, and the ATM processor 120 includes a multiplexer 122, a loopback FIFO 124, and a demultiplexer 126. The matching controller 130 includes a processor unit 132, an OAM processor 134, and an IPC processor 136. In this case, reference numeral 120 denotes a processing block for the ATM layer, and the detailed block diagram of the reception processing apparatus is shown in FIG. 10, and the detailed block diagram of the transmission processing apparatus is shown in FIG. That is, the middle speed subscriber matching device interfaces with a DS3 frame via a middle speed line board (MSLA: 14-0,14-1,14-2), which is a DS3 line interface board, and extracts an ATM cell from an DS3 frame or selects an ATM cell. Physical layer processing that maps to DS3 frame format, routing layer attach / extract function for ATM cell, and ATM layer process that performs maintenance related function from subscriber. In addition, it is a device that performs control function for the entire middle speed subscriber matching module by matching with the upper processor (SCP) and the switch network by IMI.

Referring to FIG. 2, the DS3 frame processing unit 110 extracts an ATM cell from a DS3 frame format, removes an unassigned cell and an invalid cell from a received ATM cell, and multiplexes the multiplexer through a transmission FIFO. And transmits an ATM cell transmitted from the demultiplexer 126 to a DS3 frame format. At this time, the DS3 frame processing unit 110 accommodates three DS3 links Link0, Link1, and Link2.

The multiplexer 122 arbitrates three transmit FIFOs and one loopback FIFO 124 located according to three DS3 links of the DS3 frame processor 110 to convert and multiplex into 187 Mbps byte strings. An index address is obtained from the VPI / VCI extracted from the ATM cell, and the index address is transmitted to the UPC processor 140 and the routing processor 150. LAN CAM is used to obtain the index address from the VPI / VCI of the receiving cell.The maximum number of available connections is 1024 (VP connections up to 128, VC connections up to 1024, The maximum number of connections per link is 1024).

The UPC processor 140 performs a discard function for a user cell in a reception direction directed to a network by a leaky bucket method.

The routing processor 150 performs routing header attachment and VPI / VCI conversion on the user cell transmitted from the multiplexer 122, and controls transmission of the cell according to whether or not a discard signal is received from the UPC processor 140. And drop or pass the OAM cell from the subscriber according to the routing header table.

The switch matching unit 160 transmits a user cell from the routing processor 150 and an internal message cell (IPC cell) to be transmitted to the upper processor to the switch through IMI, and transmits the user cell transmitted from the switch through IMI to the user cell. The user cell is output to the demultiplexer 126 and the internal message cell (IPC cell) is transmitted to the internal message processor 136.

The matching controller 130 includes an OAM processing unit 134, an IPC processing unit 136, and a processor unit 132. The IPC processing unit 136 generates an interrupt when receiving an FIFO, which is a path for transmitting and receiving internal message cells. Hardware and a software function block for processing the CRC check and analysis functions of the cell. In this case, data processing is a 56-byte unit with a 3-byte routing header attached. The OAM processing unit 134 includes a FIFO which is a path for transmitting and receiving an OAM cell, a hardware logic for generating an interrupt when receiving, and a software function block for processing a CRC check and analysis function of the cell. At this time, the data processing is 53 bytes.

Meanwhile, the ATM layer receiving processing apparatus for demultiplexing and distributing ATM cells received through the switching matching unit to the corresponding physical link according to the present invention, as shown in FIG. 10, the index processing unit 200 and the index table 210. , Physical link selection table 232, multicast cell copy tables 234, 246, 238, demultiplexer 220, receive FIFOs 242, 244, 246, and loopback FIFO 248. The index unit 210 receives a VPI, and outputs a VCI index (CAM data) by receiving a VP index table 214 for outputting a VPI index and a value obtained by adding VCI to the VPI index (VPI index + VCI). (CAM: 212).

Referring to FIG. 10, the index processing unit 200 accesses the reception VP index table 214 using the VPI of the received cell as an address to obtain the reception VP index data. At this time, the VP index table stores the received VP index data in bits 0 through 6, and bit 7 (CON.) Indicates a VP connection when "1" and a VC connection when "0". Subsequent VP indexing, VC indexing controls the cam (CAM: 212) using the VP index data (VPI index) obtained through VP indexing and the VCI extracted from the cell, thereby enabling 10-bit VC index data (cam data). Get

The demultiplexer 220 monitors the command (com7) of the internal register by dividing the time of 64 clocks (23.474 Mbps) and searches for processor cycles. The demultiplexer 220 monitors the VP cycle according to the control operation of the command [6..0]. The VCI value is written to the CAM 212, and the VC index value output from the CAM 212 is recorded in bit 1 to bit 10 of the status 1 (Status 1). The VCI value written to each of the receive cam registers differs depending on whether the most significant bit of the received VP index data is set. For example, VCI = 0x0000H at VP connection (bit7 = 1), and VCI = vci (VCI extracted from user cell) at VC connection (bit7 = 0). 'INIT' means CAM initialization cycle immediately after reset if '0', and '1' indicates normal operation after CAM initialization is completed. 'FF' and 'MF' continue to 23.474MHz. Is updated, and 'command [12..8]' shows the result of executing the processor cycle by setting command 7 to '1'. If '00H', the execution of command [6..0] is normal. '01H' indicates that the command execution result is abnormal. Command 7 indicates a user cell flow cycle, and 0 indicates a processor cycle. Normally, the command [6..0] is set to 1 after setting. The command [6..0] represents '01H' for index addition, '02H' for index delete, and '03H' for index search. The VP index indicates a VP connection if '1 ×××××× B', sets the VCI area to '00H' when writing to CAM, and indicates a VC connection for '0 ×××××× B'. Write to VCAM with VCI. VCI represents the VCI extracted from the cell, Status 1 represents the search result VC index 10 bits, and State 2 is not used.

In this manner, the index processing unit 200 accesses the reception VP index table 214 using the VPI of the transmitted ATM cell as an address to obtain a transmission VP index, and obtains a VCI index (CAM data) using the VPI index and the VCI. .

The demultiplexer 220 sets a link of a point-to-point access cell or a link of a point-to-multiple access cell and converts VPI / VCI based on the index data received from the index processing unit 200. That is, when the received ATM cell is a point-to-point connection, the corresponding physical link is selected according to the physical link selection table 232 by the reception VC index, and data is written to the corresponding FIFO. At this time, the link is determined according to bits 4 to 7 in 8-bit data (TXSELD [7..1]) output according to the VC index. For example, if TXSELD [] is “8XH”, link 7 is '1'. 3 is selected, and therefore the data of the cell is stored in the FIFO of link 3. Also, looking at the point-to-multi-link configuration, the link-specific data from the bulkcasting cell copy tables 234, 236, and 238 are extracted by the MCN extracted from the ATM cell. If the 'M' bit is set in the multicasting cell copy table, the operation according to the C bit and the conversion to VPI / VCI are performed and the 'M' bit is set. If not, there is no cell copy for the link, if the 'C' bit is clear, only VPI is converted, and if it is set, VPI / VCI is performed.

The cell data of the demultiplexer 220 is written to the FIFO selected by the cell copy table or the link selection table and transferred to the physical layer. The cell for loopback is written to the loopback FIFO 248 and transferred to the multiplexer.

On the other hand, according to the present invention, the ATM transmission layer processing apparatus for multiplexing the ATM cells received through the physical layer, attaching a routing header, and outputting them to the switch side, as shown in FIG. Three receive FIFOs 310, 312, 314 for storing and one loopback FIFO 316 for loopback; An index table 330 for providing a preset VPI index or VCI index data according to the input VPI / VCI; A multiplexer (320) for arbitrarily receiving and multiplexing the outputs of the received FIFOs, extracting the VPI / VCI of the received cells, outputting the VPI / VCI indexes, and obtaining the VPI index or the VCI index together with ATM cell data; A user parameter controller 350 which receives a VPI index or a VCI index from the multiplexer 320 and determines a transfer or discard of corresponding cell data by examining a user parameter (UPC) for a corresponding connection; And a routing processor 340 which receives the VPI index or the VCI index from the multiplexer, attaches a routing header for the corresponding connection, and delivers or discards the corresponding cell according to the output of the parameter controller.

The index unit 330 is composed of a VP index table 332 that receives VPI and outputs a VPI index, and a cam (CAM: 334) that receives a 'VPI index + VCI' and outputs a VCI index (CAM data). do.

Referring to FIG. 3, the multiplexer 320 monitors the transmission FIFOs (RXF1-3: 310, 312, 314) and the loopback FIFO 316 in a round robin manner, and reads data of the corresponding FIFO. The system clock is 23.474MHz, the read condition of the FIFO is that at least one cell must be in the FIFO, and the end of the read cycle is when “0” is output to the bit 8 signal of the last received cell data. The multiplexer 320 accesses the transmission VP index table 332 using the VPI of the received cell as an address to obtain transmission VP index data. That is, as shown in FIG. 4, the VP index table stores the received VP index data in bits 0 to 6, and bit 7 (CON.) Indicates a VP connection when “1” and VC when “0”. Represents a connection. Subsequent VP indexing, VC indexing controls the cam (CAM0 334) using the VP index data (VPI index) obtained through the VP indexing and the cellbooker extracted VCI, thereby providing a 10-bit VC index jitter (cam data). Get

FIG. 5 illustrates a structure of a receive cam (CAM) register, which is a VC index table. The multiplexer 320 monitors a command cycle of an internal register by dividing a time of 64 clocks (23.474 Mbps) to determine whether a processor cycle is performed. Bit 1 to bit 1 of the status 1 (Status 1) and the VC index value outputted from the CAM 334 by writing the VP index and the VCI value to the CAM 334 according to the control operation of the command [6..0]. Record at 10. The VCI value written to each of the reception cam registers differs depending on whether the most significant bit (CON .; bit7 in FIG. 4) of the reception VP index data is set. For example, VCI = 0x0000H at VP connection (bit7 = 1) and VCI = vci (VCI extracted from user cell) at VC connection (bit7 = 0).

Referring to FIG. 5, when 'INIT' is 0, it indicates that the cam is in the CAM initialization cycle immediately after the reset, and when 1, the normal operation is performed after the CAM initialization is completed. 'FF' and 'MF' continue to update to 23.474 MHz, and 'command [12..8]' shows the result of performing a processor cycle by setting Command7 to '1', where '00H' If the execution of the command [6..0] is normal, '01H' indicates that the execution of the command is abnormal. Command 7 indicates a user cell flow cycle, and 0 indicates a processor cycle. Normally, the command [6..0] is set to 1 after setting. The command [6..0] represents '01H' for index addition, '02H' for index delete, and '03H' for index search. VP index indicates VP connection if '1 ×××××× B', VCI area is set to '00H' when writing to CAM, and 'VC connection' for '0 ×××××× B'. , Write VCI to CAM. VCI represents the VCI extracted from the cell, Status 1 represents the search result VC index 10 bits, and State 2 is not used.

After the VP and VC indexing is completed, the multiplexer 320 determines whether the VP connection or the VC is connected, the user cell by the VPI and the VCI, the F4 or F5 OAM cell, respectively, from the most significant bit 7 of the transmission VP index data. The cell is classified and transmitted to the routing processor based on cell indication information as shown in Table 1 below.

In addition, when the cell classification is completed, the unassigned cell and the invalid cell are discarded internally as shown in Table 2 below, and the four signal cells are not classified by the multiplexer, and are processed in the same manner as the user cell in the router.

In Table 2, a represents bits usable by the ATM layer, x represents money care bits, y represents any number other than '00000000', and c represents the subject of signaling as "0". It is set and converted to “1” by the network.

The routing processor 340 receives the cell display signal CELL IND [1..0] and the transmission VP index from the multiplexer 320 and applies a header output from the routing table to the cell flow (with a routing header, VPI / VCI conversion). That is, the user cell determines whether a VP / VC connection is made by CELL IND [1..0] and attaches a routing header.In case of point-to-point connection, the VP connection uses only VPI and the VC connection Both VPI and VCI are converted into the corresponding values in the routing table. In the case of point-to-multipoint, only the routing header is attached.

OAM cell attaches both routing header and converted VPI / VCI like point-to-point access user cell in case of pass mode (SP, EP) according to Segment Eenpoint or Connection Endpoint setting. In case of the drop mode according to the SD or CD setting, as shown in FIG. 6, a physical link number (Link No.) corresponding to bit 1 and bit 0 of the first byte is attached and received as 56 bytes as a receiving OAM FIFO. Drop in form The link number at this time is for informing the OAM cell transmission source. The signal cell is recognized as a user cell with CELLIND [] = 1,0b, and converted into a user point-to-point user cell and a shape as shown in Table 2.

7 shows a routing field for OAM cells, FIG. 8 shows a routing field for point-to-point access cells, and FIG. 9 shows a routing field for point-to-multiple access cells.

Referring to FIG. 7, the OAM cell routing field is composed of SD, SP, ED, EP, Link No, IDL, MTC, ASW _- ORG, CDP, CSW, ASW _- DES, VPI, and VCI fields. The routing field for point-to-point access cells of FIG. 8 consists of SD, SP, ED, EP, IDL, MTC, ASW _- ORG, CDP, CSW, ASW _- DES, VPI, and VCI fields. The routing field is composed of SD, SP, ED, EP, IDL, MTC, ASW _- ORG, CDP, MCN [10..6], CET, MCN [5..0], VPI, and VCI fields.

As described above, the medium-speed subscriber matching apparatus according to the present invention enables a plurality of DS3 level subscribers to be connected to an ATM network, thereby allowing the ATM switch to accommodate various subscribers.

Claims (3)

A DS3 frame processor for extracting an ATM cell from a DS3 frame inputted from a subscriber side, discarding an invalid cell, and mapping the received ATM cell to a DS3 frame and transmitting the same to the subscriber side; ATM cell transmission processing means for receiving ATM cell data from the DS3 frame processing unit through a transmission FIFO, obtaining a VPI index and a VCI index from an index table by VPI / VCI of a corresponding cell, and multiplexing ATM cells; A user parameter control processor configured to receive a VPI / VCI index from the ATM cell transmission processing unit and process user parameter control on a connection of a corresponding cell to determine transfer or discard of the corresponding cell; A routing processing unit for finding and attaching a routing header from a routing table by a VPI / VCI index received from the ATM cell transmission processing unit, and transferring and discarding a corresponding cell according to an output of the user parameter control processing unit; After receiving the ATM cell of the predetermined byte with the routing header inputted from the routing processor, the CRC is added to form a cell of a predetermined size, connected to the switch network, and the CRC is checked from the data received from the switch network. A switch matching unit for outputting an ATM cell of bytes; ATM cell receiving processing receiving ATM cell from the switch matching unit, extracting the VPI / VCI index from the index table by VPI / VCI of the corresponding cell, assigning the pink number of the corresponding cell, and demultiplexing to the receiving FIFO of the link. Way; And a matching controller for receiving an OAM cell dropped from the routing processor, outputting an OAM cell to the ATM cell receiving processing means, transmitting and receiving an IPC cell with the switch matching unit, and controlling an operation of each block. Medium-speed subscriber matching device at an ATM exchange. 2. The system of claim 1, wherein said ATM cell transmission processing means comprises: a plurality of transmit FIFOs for storing ATM cells received from DS3 subscribers; An index table for providing preset VPI index or VCI index data according to the input VPI / VCI; And a multiplexer for arbitrating the output of the transmission FIFOs, multiplexing them, extracting the VPI / VCI of the received cells, outputting them to the index table, and obtaining the VPI index or the VCI index together with the ATM cell data. Intermediate subscriber matching device at an ATM exchange. 2. The system of claim 1, wherein the ATM cell receiving processing means comprises: an index table for providing a preset VPI index or VCI index data according to an input VPI / VCI; An index processing unit which receives an ATM cell from a switch and extracts the VPI / VCI of the received cell and outputs the index data to the index table to obtain index data; A demultiplexer which receives index data from the index processor and selects a physical link according to an index and outputs data; And a receiving FIFO for storing an ATM cell inputted from the demultiplexing unit.