KR19980054668A - Intermediate subscriber matching device at ATM switch - Google Patents

Abstract

The present invention relates to a medium speed subscriber matching device for connecting a medium speed subscriber (DS3 class speed subscriber) to an ATM switching network in an ATM switch.

The apparatus of the present invention comprises: a DS3 frame processor 110 for extracting an ATM cell from a DS3 frame input from a subscriber side, mapping the ATM cell to a DS3 frame, and transmitting the ATM cell to the subscriber side; A multiplexer 122 which receives ATM cell data through a reception FIFO, obtains a VPI index and a VCI index from an index table from a VPI / VCI of the corresponding cell, and then multiplexes the multiplexer 122; A user parameter control processor 140 which receives a VPI / VCI index from the multiplexer and processes user parameter control on a connection of a corresponding cell to determine transfer or discard of the corresponding cell; A routing processor (150) for finding and attaching a routing header from the routing table by the VPI / VCI index and delivering and discarding a corresponding cell according to an output of the user parameter control processor; Switch matching unit 160; A demultiplexer 126 that receives an ATM cell, extracts a VPI / VCI index from an index table by VPI / VCI of the cell, assigns a link number of the cell, and demultiplexes the transmission FIFO of the link; And a matching controller 130 to connect the medium speed subscriber to the ATM switch network.

Description

Intermediate subscriber matching device at ATM switch

The present invention relates to a medium speed subscriber matching device for connecting a medium speed subscriber (DS3 class speed subscriber) to an ATM switching network in an ATM switch.

In general, an ATM switch is a system that performs a node function to connect an ATM network, an ATM network, or a subscriber to an ATM network when configuring a public network using an ATM method. A virtual channel (VC) switch according to its function And Virtual Path (VP) exchanges.

The ATM switching system is implemented with a subscriber matching device, a switch network, a relay line matching device, and the like and processors that control them.

The subscriber matching device performs traffic control function according to user parameter control (UPC) along with UNI physical layer matching, ATM layer processing, signal cell and user cell separation transfer, header conversion, and OAM processing. Subscriber matching devices can also include low- and medium-speed subscriber matching for existing subscriber services, as well as ATM subscribers. The low-speed subscriber matching provides DS1E (approximately 2.048 Mbps) level access, and the subscriber registration feature provides DS3 (approx. 44.736 Mbps) level of connectivity.

ATM switch networks are realized by multiple stages of unit switches capable of high-speed switching of hundreds of Mbits. ATM unit switches are divided into input buffers, output buffers, common memories, common buses, cross-point switches, and the like according to configuration.

ATM trunk line matching device performs NNI interface, physical layer processing, ATM layer processing, OAM processing, and the traffic control function works in conjunction with switch network. It also includes interworking functions with other networks such as existing telephone network, narrowband (N) -ISDN, packet network, frame relay network, etc.

However, in the ATM switch, a matching device for connecting the intermediate subscriber to the switch has not been specifically presented in the related art, and thus an apparatus for implementing the matching device is required.

Accordingly, an object of the present invention is to provide an intermediate subscriber matching device for accessing an existing DS3 level intermediate subscriber in an ATM switch.

In order to achieve the above object, the apparatus of the present invention extracts an ATM cell from a DS3 frame input from a subscriber side, discards an invalid cell, and maps the ATM cell received from the demultiplexing side to a DS3 frame and transmits it to the subscriber side. DS3 frame processing means; Multiplexing means for receiving ATM cell data from the DS3 frame processing means through a receiving FIFO, obtaining a VPI index and a VCI index from an index table from a VPI / VCI of a corresponding cell, and multiplexing an ATM cell; User parameter control processing means for receiving a VPI / VCI index from the multiplexing unit and processing user parameter control for access of a corresponding cell to determine transfer or discard of the corresponding cell; Routing processing means for finding and attaching a routing header from a routing table by a VPI / VCI index received from the multiplexing unit, and transferring and discarding a corresponding cell according to an output of the user parameter control processing unit; After receiving 56 byte ATM cell with routing header inputted from the routing processor, 8 byte CRC is added to form a 64 byte cell, connected to switch network by IMI, and receiving IMI from switch network. Switch matching means for outputting an ATM cell of 56 bytes after checking; A demultiplexer which receives an ATM cell from the switch matching means, extracts a VPI / VCI index from an index table by VPI / VCI of the cell, assigns a link number of the cell, and demultiplexes the transmission FIFO of the link; And a matching controller for receiving the OAM cell dropped from the routing processor, outputting the OAM cell to the demultiplexer, transmitting and receiving an IPC cell with the switch matching unit, and controlling the operation of each block.

1 is a block diagram showing a general ATM switch suitable for application of the present invention;

2 is a block diagram showing a medium speed subscriber matching device according to the present invention;

3 is a detailed block diagram of the processor unit illustrated in FIG. 2.

* Explanation of symbols for main parts of the drawings

10-0,10-n: ATM Local Exchange Subsystem (ALS)

12-0,12-n: MSIM

14-0,14-1,14-2,14-3: Medium Speed Subscriber Line Board (MSLA)

16: Medium Speed Subscriber Matching Device (MSAA)

17: access switching network module (ASNM) 18: subscriber call processing processor (SCP)

20: ATM Central Switching Subsystem (ACS)

22: Interconnect Switch Network Module (ISNM)

24: Operation and Maintenance Processor (OMP) 26: Workstation

110: DS3 frame processing unit 122: multiplexing unit

126: demultiplexer 130: matching controller

140: UPC processing unit 150: routing processing unit

160: switch matching unit

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Broadband Integrated Information Network (B-ISDN) is a high-speed integrated information network that accommodates not only voice and low-speed data communications supported by narrow-band integrated information networks, but also high-speed data transmission, still picture, telephony and video conferencing services. In addition, ATM switching system used in broadband information communication network is composed of UNI / NNI matching and access switching module that connects between ALS and ATM local switching subsystem (ALS) that provides subscriber and other services with subscribers or other exchanges. It consists of an ATM Central Switching Subsystem (ACS) to provide the services of the switching system. At this time, the UNI / NNI accessible in the ATM switching system includes 155Mbps STM-1 level UNI, DS3 level, DS1E medium and low speed UNI, and 155Mbps STM-1 level and 622Mbps STM-4 level NNI, respectively.

In addition, as shown in FIG. 1, such an ATM switch includes a plurality of ATM Local Switching / Subscriber subsystems (ALS) 10-0 to 10-n, and an ATM central switching subsystem (ACS: ATM). Central Switching Subsystem;

In addition, the ALS 10-0 to 10-n includes a plurality of subscriber interface modules (SIMs), an access switching network module (ASNM: 17), and a subscriber call processing processor (SCP: 18). In the embodiment of the present invention, the subscriber module (SIM) is a medium to low speed subscriber module (MSIM: 12-0 to 12-n) for connecting a medium to low speed subscriber, and among them, medium speed subscriber matching for connecting three DS3 classes. Module.

And an Access Switching Network Module (ASNM) 17 accesses a plurality of medium and low speed subscriber modules (MSIM: 12-0-12-n) and controls a subscriber call that controls an ATM local switching subsystem. A subscriber call processor (SCP) 18 is connected to the IMI.

The medium and low speed subscriber module (MSIM: 12-0 to 12-n) is a medium speed line board (MSLA: 14-0, 14-1, 14-2) providing three DS3 level connection lines, and three links. It is composed of a medium speed subscriber matching device (MSAA: 16) that provides IMI access by connecting to the network.

In addition, the ACS 20 is composed of an Interconnection Switch Network Module (ISNM) 22 and an Operation Preservation Processor (OMP: 24). The OMP 24 is not shown in the drawings, but the cell multiplexing and deactivation is performed. Connected to multiplexing blocks (CMDH: Cell Mux / Demux H / W Assembly), Sbus interface Processor Communication board Assembly (SPCA), ATM Main Processor board Assembly (AMPA), and AMPA Disk, cartridge tape CT, and the like.

As shown in FIG. 2, the middle speed subscriber matching device according to the present invention includes a DS3 frame processor 110, a multiplexer 120, a loopback FIFO 124, a demultiplexer 126, a UPC processor 140, The routing processor 150, the controller 130, and the switch matching unit 160, the DS3 frame processor 110 is composed of three physical layer chips (PLPP: 112, 114, 116), the controller 130 The processor 132 includes an OAM processing unit 134 and an IPC processing unit 136. In this case, 120 is a processing block for the ATM layer.

That is, the medium speed subscriber matching device 16 interfaces with a DS3 frame via three medium speed line boards (MSLAs 14-0, 14-1, 14-2), which are DS3 line interface boards, and connects an ATM cell from the DS3 frame. Processes physical layer processing to extract or map ATM cells to DS3 frame format. In addition, it performs ATM layer processing for attaching a routing header or extracting a routing header to an ATM cell and performing maintenance related functions from subscribers. In addition, the upper processor (SCP) and the switch network match the IMI to perform the control function for the entire middle speed subscriber matching module.

Referring to FIG. 2, the DS3 frame processor 110 extracts an ATM cell from a DS3 frame format, and then removes an unassigned cell and an invalid cell from a received ATM cell and multiplexes it through a received FIFO. And transmits an ATM cell transmitted from the demultiplexer 126 to a DS3 frame format. At this time, the DS3 frame processing unit 110 accommodates three DS3 links Link0, Link1, and Link2.

The multiplexer 122 arbitrates three receive FIFOs and one loopback FIFO 124 located according to three DS3 links of the DS3 frame processor 110 to convert and multiplex into 187 Mbps byte strings. An index address is obtained from the VPI / VCI extracted from the ATM cell, and the index address is transmitted to the UPC processor 140 and the routing processor 150.

LAN CAM is used to obtain the index address from the VPI / VCI of the receiving cell.The maximum number of available connections is 1024 (VP connections up to 128, VC connections up to 1024, The maximum number of connections per link is 1024).

The UPC processing unit 140 performs a function of determining a transfer or discard for a user cell in a transmission direction directed to a network by a leaky bucket method. That is, in the process of performing call up, the user and manganese enter into agreements on parameters such as traffic. The UPC checks whether the user cell is keeping these agreements and discards the corresponding cell if the agreement is violated.

The routing processor 150 attaches a routing header to the user cell transmitted from the multiplexer 122 or performs VPI / VCI conversion, and transmits a corresponding cell when a cell discard signal is input from the UPC processor 140. It analyzes the OAM cell received from the subscriber according to the routing header table to drop or pass (drop or pass). At this time, the OAM cell received and dropped from the subscriber is delivered to the OAM processing unit 134 through the FIFO.

The switch matching unit 160 transmits a user cell from the routing processor 150 and an internal message cell (IPC cell) to be transmitted to the upper processor to the switch through IMI, and the user transmitted from the switch through IMI. The cell is classified into a user cell and an internal message cell (IPC cell), and the user cell is output to the demultiplexer 126, and the internal message cell (IPC cell) is transmitted to the internal message processor 136. At this time, the ATM cell inputted from the routing processor is 56 bytes of 3 bytes attached to a 53 byte cell, and a CRC byte is attached to every 8 bytes to form a 64 byte cell. In addition, in the 64-byte cell received from the switch, 56-byte cells are transferred to the demultiplexer after the CRC is checked.

Meanwhile, the matching controller 130 is composed of an OAM processing unit 134, an IPC processing unit 136, and a processor unit 132. The IPC processing unit 136 is an interrupt when receiving a FIFO, which is a path for transmitting and receiving internal message cells. It consists of hardware for generation and a software function block that handles CRC checking and analysis functions of the cell. At this time, the IPC cell is a 56-byte unit with a 3-byte routing header attached thereto.

The OAM processing unit 134 includes an FIFO that provides a path for transmitting and receiving an OAM cell, hardware for generating an interrupt when receiving, and software for processing CRC check and analysis of the cell to analyze the OAM cell received from the subscriber. In addition to processing, it delivers the OAM cell to the subscriber. At this time, the data processing is 53 bytes.

In addition, as illustrated in FIG. 3, the processor unit 132 includes a clock generator 210, a reset unit 220, a processor 230, a local ROM 240, a local RAM 250, and a register unit 260. And the matching unit 270, and the processor 230 has an operating frequency of 25 MHz as Motorola's MC68EN360RC25 (QUICC) in an embodiment of the present invention, and provides Ethernet and serial communication ports.

In this case, the main signal lines of the processor used in the embodiment of the present invention are shown in Table 1 below.

TABLE 1

In FIG. 3, the clock generator 210 is composed of a 25 MHz crystal oscillator, a 44.736 MHz crystal oscillator and a divider to generate a 25 MHz clock, 44.736 MHz, and 5.592 MHz, respectively.

Here, 25MHz is used to maintain the basic operation of the CPU, long hold supervisory control circuit implemented in the local arbiter, local timeout circuit, and additionally select MCLK and IMI. 44.736MHz is used for DS3 frame processing unit and MLSA line interface. It is used as PLCLK, which is a clock for use, and 5.592MHz is used as CLK_PL5, which is a physical layer interface clock divided by 8 times of PLCLK.

The reset unit 220 generates a signal for resetting the CUP. At this time, the reset signal of the processor includes a power-on-reset, a manual reset, a watch dog timer reset, and a system reset by software. Each reset signal generation logic is composed of LM555 timer IC and peripheral circuit to secure more than 512 clock time required by the processor. The time is determined by the time constant by resistor and capacitor.

After the reset signal is applied, the processor 230 starts the program by bringing the stack pointer and the program counter (PC) at addresses 0 to 7H. When the power is turned on and when the manual reset or the processor is abnormal, the processor 230 is applied. The hardware is configured.

In addition, the processor 230 includes a restart function, and when a local long timeout or a bus error occurs, the processor 230 simultaneously gives a bus error (BERR *) and a hold (HALT *) signal to the CPU. Waits for both signals to negate and retry the previously performed bus cycle.

At this time, there are write error and local long timeout. The write error is an error signal generated when writing to a ROM that cannot be written. The local long timeout signal has no response when accessing internal resources. It is a signal generated in the case.

If the BERR * and HALT * signals are applied to the processor at the same time, the same cycle as the current cycle is performed regardless of software. If only the BERR * signal is applied, A bus error vector is generated internally in the processor, causing the program to perform a predefined bus error exception operation.

The map decoder circuit converts an address of an on-board device into a selection signal. The processor (QUICC) 230 used in the present invention uses an internal register to transmit an external device using six chip selection signals. In this case, the ROM is assigned to the boot area and the first operation is performed immediately after the reset.

In the embodiment of the present invention, the chip select signal is generated according to the address area as shown in Table 2 below.

TABLE 2

Interrupt handler handles interrupt priority level decoding and automatic vector generation for the interrupt source inputted in QUICC.WDTOUT (Watch Dog Time Out) signal generated internally is the highest level as 7 Has priority. An IRQ (level 2 or 3) occurs on receipt of an internal message or on receipt of an OAM cell, and is built into the local arbiter to find the source when an interrupt occurs.

Local ROM (EPROM: 240) consists of two 128K byte x 8 bit EPROMs, consisting of 256K bytes, with a weight cycle inserted for timing in access by the processor. The ROM stores various boot programs.

The local RAM (SRAM) 250 is composed of a 1M byte module and is a high speed RAM capable of operating without a weight when accessed by a processor. RAM stores various data and programs.

The register section 26 includes an interrupt status register, an interrupt mask register, a PBA OFF status register, and a PBA function status register. These registers store various board-related information so that the processor can recognize them.

The matching unit 270 provides an interface for the processor to access each block of the board.

As described above, the medium-speed subscriber matching device according to the present invention enables a plurality of DS3 level subscribers to be connected to an ATM network, thereby allowing the ATM switch to accommodate various subscribers.

Claims (4)

A DS3 frame processing means (110) for extracting an ATM cell from a DS3 frame input from the subscriber side and then discarding the invalid cell, and mapping the ATM cell received from the demultiplexing side to a DS3 frame and transmitting it to the subscriber side; Multiplexing means (122) for receiving ATM cell data from the DS3 frame processing means through a receiving FIFO, obtaining a VPI index and a VCI index from an index table from a VPI / VCI of a corresponding cell, and multiplexing ATM cells; User parameter control processing means (140) for receiving a VPI / VCI index from the multiplexer to process user parameter control for access of a corresponding cell to determine transfer or discard of the corresponding cell; Routing processing means (150) for finding and attaching a routing header from the routing table by the VPI / VCI index received from the multiplexing unit, and transferring and discarding the corresponding cell according to the output of the user parameter control processing unit; After receiving 56 byte ATM cell with routing header inputted from the routing processor, 8 byte CRC is added to form a 64 byte cell, connected to switch network by IMI, and receiving IMI from switch network. A switch matching means 160 for outputting an ATM cell of 56 bytes after checking; A demultiplexer 126 which receives an ATM cell from the switch matching means, extracts a VPI / VCI index from an index table by VPI / VCI of a corresponding cell, assigns a link number of the corresponding cell, and demultiplexes the transmission FIFO of the link. ); And An ATM switch receiving the OAM cell dropped from the routing processing unit, outputting the OAM cell to the demultiplexer, transmitting and receiving an IPC cell with the switch matching unit, and a matching control unit 130 for controlling the operation of each block. Intermediate subscriber matching device. The medium speed subscriber matching device according to claim 1, wherein the medium speed subscriber matching device further comprises a loopback FIFO for demultiplexing the test cell input through the switch network and looping back to the multiplexing unit. 2. The apparatus of claim 1, wherein the DS3 frame processing means is implemented with three physical layer chips to accommodate three DS3 frames. The apparatus of claim 1, wherein the matching controller receives an IPC processing unit for transmitting and receiving an IPC cell with the switch matching unit, an OAM cell dropped from the routing processing unit, and transmits an OAM cell to be delivered to a subscriber to the demultiplexer. And a processor unit configured to perform an OAM processing unit and a predetermined sequence to control each block.