KR100219214B1 - Apparatus for interfacing atm cells to switch network in an atm exchange - Google Patents

Abstract

The present invention relates to an ATM cell and a switch matching device for transmitting ATM cells with multiplexing and routing headers in an ATM transmission layer to a switch network and delivering IMI data received from the switch network to an ATM receiving layer.

The apparatus of the present invention includes a receiving FIFO 210 for receiving and storing an ATM user cell from an ATM transmission layer; A message transmission FIFO 212 that stores an IPC cell for delivery to a higher processor via a switch; A transmission FIFO 214 for receiving and storing an ATM user cell received from the switch side; A message receiving FIFO 216 storing an IPC cell received from a higher processor via a switch; After multiplexing the user cell and the IPC cell of the receiving FIFO, generating and outputting a CRC byte every predetermined byte, CRC checking the IMI data received from the switch side, and outputting the IPC cell to the message receiving FIFO, the user cell is the A network matching unit 220 outputting a transmission FIFO; And an IM matching unit 230 for converting the output of the network matching unit into a differential ECL level suitable for a switch network, outputting the received IMI data of the differential EC level, converting the TTL level, and transmitting the converted ITL data to the network matching unit. Two DS3 level subscribers can be efficiently connected to the switch network, increasing the efficiency of the ATM network.

Description

ATM Cell and Switch Matching Device in ATM Switching System

The present invention relates to a medium-speed subscriber matching device for connecting a medium-speed subscriber (DS3-class subscriber) to an ATM switching network in an ATM switch. Particularly, the present invention provides an ATM cell with multiplexing and routing headers in the ATM transmission layer to a switch network. The present invention relates to an ATM cell and a switch matching device for delivering IMI data received from a switch network to an ATM receiving layer.

In general, an ATM switch is a system that performs a node function to connect an ATM network, an ATM network, or a subscriber to an ATM network in the case of a public network based on an ATM method. (VP) is divided into exchanges.

The ATM switching system is implemented with a subscriber matching device, a switch network, a relay line matching device, and the like and processors for controlling them.

The subscriber matching device performs traffic control function according to user parameter control (UPC) along with UNI physical layer matching, ATM layer processing, signal cell and user cell separation transfer, header conversion, and OAM processing. Subscriber matching devices can also include low- and medium-speed subscriber matching for existing subscriber services, as well as ATM subscribers. The low-speed subscriber matching provides DS1E (approximately 2.048 Mbps) level access, and the subscriber registration feature provides DS3 (approx. 44.736 Mbps) level of connectivity.

ATM switch networks are realized by multiple stages of unit switches capable of high-speed switching of hundreds of Mbits. ATM unit switches are divided into input buffers, output buffers, common memories, common buses, cross point switches, and the like according to the configuration.

ATM trunk line matching device performs NNI interface, physical layer processing, ATM layer processing, OAM processing, and the traffic control function works in conjunction with switch network. It also includes interworking functions with other networks such as existing telephone network, narrowband (N) -ISDN, packet network, frame relay network, etc.

However, in the ATM switch, a matching device for connecting the intermediate subscriber to the switch has not been specifically presented in the related art, and thus an apparatus for implementing the matching device is required.

Accordingly, an object of the present invention is to provide a switch matching device for connecting multiplexed cells in an ATM layer to a switch network in order to access an existing DS3 level medium-speed subscriber in an ATM switch.

In order to achieve the above object, the apparatus of the present invention outputs ATM cells with multiplexing and routing headers through a physical layer and an ATM transmission layer to accommodate a plurality of DS3 subscribers to a switch network, and receives the data from the switch network. In an ATM switch configured to deliver IMI data to an ATM receiving layer,

A reception FIFO for receiving and storing an ATM user cell from the ATM transmission layer;

An IPC transmit FIFO that stores an IPC cell for delivery to a higher processor through the switch;

A transmission FIFO for receiving and storing an ATM user cell received from a switch side;

An IPC receive FIFO storing an IPC cell received from a higher processor via a switch;

After multiplexing the user cell and the IPC cell of the receiving FIFO, generating and outputting a CRC byte every predetermined byte, CRC checking the IMI data received from the switch side, the IPC cell outputs to the IPC receiving FIFO and the user cell is the A network matching unit for outputting a transmission FIFO; And

The output of the network matching unit is converted into a differential ECL level suitable for the switch network, and outputs, and receives the IMI data of the differential EC level, and converts into a TTL level, characterized in that the IM matching unit for delivering to the network matching unit.

1 is a block diagram showing a general ATM switch;

2 is a block diagram showing a medium-low speed subscriber matching device to which the present invention is applied;

3 is a block diagram illustrating a switch matching device according to the present invention;

4 is a timing diagram showing a matching timing between a network matching unit and an IM matching unit in the switch matching device;

5 illustrates a 56 byte ATM cell structure.

* Explanation of symbols for main parts of the drawings

10-0,10-n: ATM Local Exchange Subsystem (ALS)

12-0,12-n: Medium and low speed subscriber registration module (MSIM)

14-0,14-1,14-2,14-3: Medium Speed Subscriber Line Board (MSLA)

16: Medium Speed Subscriber Matching Device (MSAA)

17: access switching network module (ASNM) 18: subscriber call processing processor (SCP)

20 ATM Central Switching Subsystem (ACS) 22 Interconnect Switch Network Module (ISNM)

24: Operation and Maintenance Processor (OMP) 26: Workstation

110: DS3 frame processing unit 122: multiplexing unit

126: demultiplexer 130: matching controller

140: UPC processing unit 150: routing processing unit

160: switch matching unit

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Broadband Integrated Information Network (B-ISDN) is a high-speed integrated information network that accommodates not only voice and low-speed data communications supported by narrow-band integrated information networks, but also high-speed data transmission, still picture, telephony and video conferencing services. In addition, ATM switching system used in broadband information communication network is composed of UNI / NNI matching and access switching module that connects between ALS and ATM local switching subsystem (ALS) that provides subscriber and other services with subscribers or other exchanges. It consists of an ATM Central Switching Subsystem (ACS) to provide the services of the switching system. At this time, the UNI / NNI accessible in the ATM switching system includes 155Mbps STM-1 level UNI, DS3 level, DS1E medium and low speed UNI, and 155Mbps STM-1 level and 622Mbps STM-4 level NNI, respectively.

In addition, as shown in FIG. 1, such an ATM switch includes a plurality of ATM Local Switching / Subscriber subsystems (ALS) 10-0 to 10-n, and an ATM central switching subsystem (ACS: ATM). Central Switching Subsystem;

In addition, the ALS 10-0 to 10-n includes a plurality of subscriber interface modules (SIMs), an access switching network module (ASNM: 17), and a subscriber call processing processor (SCP: 18). In the embodiment of the present invention, the subscriber module (SIM) is a medium to low speed subscriber module (MSIM: 12-0 to 12-n) for connecting a medium to low speed subscriber, and among them, medium speed subscriber matching for connecting three DS3 classes. Module.

And an Access Switching Network Module (ASNM) 17 accesses a plurality of medium and low speed subscriber modules (MSIM: 12-0-12-n) and controls a subscriber call that controls an ATM local switching subsystem. A subscriber call processor (SCP) 18 is connected to the IMI.

The medium and low speed subscriber module (MSIM: 12-0 to 12-n) is a medium speed line board (MSLA: 14-0, 14-1, 14-2) providing three DS3 level connection lines, and three links. It is composed of a medium speed subscriber matching device (MSAA: 16) that provides IMI access by connecting to the network.

In addition, the ACS 20 is composed of an Interconnection Switch Network Module (ISNM) 22 and an Operation Preservation Processor (OMP: 24). The OMP 24 is not shown in the drawings, but the cell multiplexing and deactivation is performed. Connected to multiplexing blocks (CMDH: Cell Mux / Demux H / W Assembly), Sbus interface Processor Communication board Assembly (SPCA), ATM Main Processor board Assembly (AMPA), and AMPA Disk, cartridge tape CT, and the like.

As shown in FIG. 2, the middle speed subscriber matching device according to the present invention includes a DS3 frame processor 110, a multiplexer 120, a loopback FIFO 124, a demultiplexer 126, a UPC processor 140, The routing processor 150, the controller 130, and the switch matching unit 160, the DS3 frame processor 110 is composed of three physical layer chips (PLPP: 112, 114, 116), the controller 130 The processor 132 includes an OAM processing unit 134 and an IPC processing unit 136. In this case, 120 is a processing block for the ATM layer.

That is, the middle speed subscriber matching device 16 interfaces with the DS3 frame via the middle speed line board (MSLA: 14-0, 14-1, 14-2), which is a DS3 line interface board, and extracts an ATM cell from the DS3 frame or ATM. A physical layer process for mapping a cell to a DS3 frame format and an ATM layer process for performing routing header attachment / extraction for an ATM cell and maintenance related functions from a subscriber are performed. In addition, it is a device that performs control function for the entire middle speed subscriber matching module by matching with the upper processor (SCP) and the switch network by IMI.

Referring to FIG. 2, the DS3 frame processing unit 110 extracts an ATM cell from a DS3 frame format, and then removes an unassigned cell and an invalid cell from the received ATM cell to the multiplexer 122 through the FIFO. And the ATM cell transmitted from the demultiplexer 126 is mapped to the DS3 frame format. At this time, the DS3 frame processing unit 110 accommodates three DS3 links Link0, Link1, and Link2.

The multiplexer 122 arbitrates three receive FIFOs and one loopback FIFO 124 located according to three DS3 links of the DS3 frame processor 110 to convert and multiplex into 187 Mbps byte strings. An index address is obtained from the VPI / VCI extracted from the ATM cell, and the index address is transmitted to the UPC processor 140 and the routing processor 150.

LAN CAM is used to obtain the index address from the VPI / VCI of the receiving cell.The maximum number of available connections is 1024 (VP connections up to 128, VC connections up to 1024, The maximum number of connections per link is 1024).

The UPC processing unit 140 performs a function of determining a transfer or discard for a user cell in a transmission direction directed to a network by a leaky bucket method. That is, in the process of performing call up, the user and manganese enter into agreements on parameters such as traffic. The UPC checks whether the user cell is keeping these agreements and discards the corresponding cell if the agreement is violated.

The routing processor 150 attaches a routing header to the user cell transmitted from the multiplexer 122 or performs VPI / VCI conversion, and transmits a corresponding cell when a cell discard signal is input from the UPC processor 140. It analyzes the OAM cell received from the subscriber according to the routing header table to drop or pass (drop or pass). At this time, the OAM cell received and dropped from the subscriber is delivered to the OAM processing unit 134 through the FIFO.

The switch matching unit 160 transmits a user cell from the routing processor 150 and an internal message cell (IPC cell) to be transmitted to the upper processor to the switch through IMI, and the user transmitted from the switch through IMI. The cell is classified into a user cell and an internal message cell (IPC cell), and the user cell is output to the demultiplexer 126, and the internal message cell (IPC cell) is transmitted to the internal message processor 136. At this time, the ATM cell inputted from the routing processor is 56 bytes of 3 bytes attached to a 53 byte cell, and a CRC byte is attached to every 8 bytes to form a 64 byte cell. In addition, in the 64-byte cell received from the switch, 56-byte cells are transferred to the demultiplexer after the CRC is checked.

Meanwhile, the matching controller 130 includes an OAM processing unit 134, an IPC processing unit 136, and a processor unit 132. The IPC processing unit 136 receives an FIFO and an IPC cell for transmitting and receiving an internal message cell. It consists of hardware for generating an interrupt and a software function block for handling the CRC check and analysis functions of the cell. In this case, data processing is a 56-byte unit with a 3-byte routing header attached.

The OAM processing unit 134 includes a FIFO for transmitting and receiving an OAM cell, hardware for generating an interrupt when receiving the OAM cell, and a software function block for processing a CRC check and analysis function of the cell. At this time, the data processing is 53 bytes.

On the other hand, the switch matching device according to the present invention, as shown in Figure 3, the receiving FIFO (210) for receiving and storing the ATM user cell from the ATM transmission layer; A transmit message FIFO 212 that stores an IPC cell for delivery to the upper processor via the switch; A transmission FIFO 214 for receiving and storing an ATM user cell received from the switch side; A received message FIFO 216 storing an IPC cell received from a higher processor via a switch; After multiplexing the user cell and the IPC cell of the receiving FIFO 210, generating and outputting a CRC byte every predetermined byte, CRC checking the IMI data received from the switch side, the IPC cell outputs the message receiving FIFO and the user The cell outputs the network matching unit 220 to the transmission FIFO; And an IM matching unit 230 converting the output of the network matching unit into a differential ECL level suitable for a switch network, and outputting the IMI data of the differential ECL level to a TTL level to be transferred to the network matching unit 220. Consists of.

Referring to FIG. 3, the network matching unit 220 arbitrates and multiplexes a 56-byte user cell stored in the reception FIFO 210 and an IPC cell stored in the transmission message FIFO 212 by a processor via a routing processing unit. In this case, the arbitration rules are used to monitor the write signal lines (/ RUFFWR and / TMFFWR) and the FIFO amplifier flags (/ RUFFFEF and / TMFFEF) of the two FIFOs 210 and 212 so that one or more cells of data are written to each FIFO 210 and 212. When more than one cell has been read and processed, the internal counter generates the FIFO lead enable signal (RURDEN, TMRDEN), and the network matching unit 220 recognizes the signal and arbitrates the round robin method. do.

In addition, when the network matching unit 220 reads a 56-byte cell from the reception FIFO 210 or the transmission message FIFO 212, 8, 16, 24, 32 in the system clock MCLKP to satisfy the SLIDI [] type. The clocks at the 40, 48, 56, and 64 byte positions are read according to the read clock which is gapped.

The network matching unit 220 reads an ATM cell of 56 bytes, inserts a CRC byte of 1 byte every 7 bytes, converts it into a 64 byte SLID [] form, and outputs it to the IM matching unit 230. At this time, the data transfer between the network matching unit 220 and the IM matching unit 230, 64 bytes are transmitted by 64 clocks as shown in Figure 4, MCS signal line is used to indicate the start of the cell.

In addition, the network matching unit 220 transmits a 56-byte cell to the subscriber as shown in FIG. 5 after the CRC checks the cell, and PT_I and PT_O are 8 bits of SLIDI [] or SLIDO []. Parity bit that makes the number of '1's even in the data.

Referring to FIG. 5, the idle cell with IDL set to '1' is discarded in the network matching unit, the message cell with CET equal to '11' is dropped to the received message FIFO 216, and the remaining cells are sent to the sending user FIFO 214. Is passed)

The IM matching unit 230 is interfaced with the switch in a redundant redundant dual line, the level is Pseudo ECL. The selection of the active link in the redundant link is determined by monitoring the active signal line. For example, when IMI_SEL is '1', link 1 is selected, and in case of '0', link 2 is selected.

In addition, the IM matching unit 230 generates an alarm signal L_F_ALM if synchronization fails while performing synchronization from the MCLKP and the MCS from the network matching unit 220, and generates an alarm signal when synchronization is lost during clock regeneration and data extraction from the switch. RL_F_ALM).

As described above, the switch matching device of the middle speed subscriber matching board according to the present invention can efficiently connect a plurality of DS3 level subscribers to the switch network, thereby increasing the efficiency of the ATM network.

Claims (2)

In an ATM exchanger that outputs ATM cells with multiplexing and routing headers through a physical layer and an ATM transmission layer to accommodate a plurality of DS3 subscribers, and transmits IMI data received from the switch network to the ATM receiving layer. , A reception FIFO 210 for receiving and storing an ATM user cell from the ATM transmission layer; A message transmission FIFO 212 that stores an IPC cell for delivery to a higher processor via a switch; A transmission FIFO 214 for receiving and storing an ATM user cell received from the switch side; A message receiving FIFO 216 storing an IPC cell received from a higher processor via a switch; After multiplexing the user cell and the IPC cell of the receiving FIFO, generating and outputting CRC bytes every predetermined byte, CRC checking the IMI data received from the switch side, and outputting the IPC cell to the message receiving FIFO. A network matching unit 220 outputting the transmission FIFO; And ATM switch having an IM matching unit 230 which converts the output of the network matching unit to a differential ECL level suitable for a switch network, outputs the IMI data of the differential EC level, converts it to a TTL level, and delivers it to the network matching unit. ATM cell and switch matching device. 2. The ATM switch and ATM switch of claim 1, wherein the IM matching unit 230 is configured to generate an alarm when the synchronization received from the network matching unit is broken or the synchronization received from the switch network is broken. Matching device.