KR0131850B1 - Apparatus for switching of atm with output butter type - Google Patents

Abstract

The present invention utilizes a two-stage buffering method, a speed gain method, and a method of operating the input cell regardless of the synchronization / asynchronous state of the input cells in a small output buffer type ATM switching device having a dedicated broadcast bus structure. A small output buffer type ATM switching device with an input port number of 16 or less can be used to reduce the number of buffers required for device configuration, and to provide excellent burst traffic handling and simple internal control. In the present invention, while providing a reduction effect of a required buffer than a general output buffer type switching device, the conventional knockout switching device is relatively complicated in configuration than the advantage of the control method, but the present invention provides a device having a capacity of 16. It is possible to simplify the configuration of the device while limiting the output to a smaller case. In part enhance the processing characteristics of the traffic cells are driven at the same time.

Description

Output buffer type asynchronous transfer mode switching device

1 is a general configuration diagram of a buffer type switching device having a dedicated broadcast bus.

2 is a block diagram of an output processor using a knockout concentrator.

3 is a block diagram of a switching device according to the present invention.

4 is an exemplary diagram of a cell configuration form.

5 is an operational state diagram of the selector.

* Explanation of symbols for main parts of the drawings

1: Input Connection 2: Input Header Converter

3: dedicated broadcast bus 4: cell filter

5: internal buffer 6: selector

7: common output buffer 8: output processing unit

9: output header converter 10: output connection

The present invention relates to a two-stage buffering method, a speed gain method, and a synchronous / asynchronous input cell configuration in a small output buffer type asynchronous transfer mode (ATM) switching device having a dedicated broadcast bus structure. The present invention relates to a small output buffer type ATM switching device having an input port number of 16 or less configured using a method that operates regardless of state, so that the number of buffers required for device configuration, burst traffic processing, and excellent internal control are simplified. An output buffer type ATM switching device.

One of the key functional elements in building a broadband integrated information network is an ATM switching device. Countless structures have been proposed and announced for this ATM switching device. Among them, an output buffer type switching device using a dedicated broadcast bus has been studied as one of the switching devices that can provide excellent performance. Modified structures have been proposed for improvement and ease of implementation, but the proposed structures may be halved or rather unnecessary depending on the switch capacity to be implemented. Therefore, the proposal of a more suitable structure according to the switch capacity to be implemented is very important for practical implementation.

On the other hand, a representative of the output buffer type switching device is a knockout switching device proposed by the United States. This switching device has the advantage of reducing the number of buffers required for the implementation compared to the general output buffer type switching device. However, when the capacity of the switching device is small, this effect is insignificant. The complexity of R is relatively complicated compared to the capacity of the switching device. In addition, due to the knockout concentrator in the structure, when a large number of input cells destined for one output connection are generated at the same time, there is a disadvantage such as a rapid increase in cell loss. When described in detail through the drawings as follows.

1 is a general configuration diagram of an output buffer type ATM switching apparatus using a dedicated broadcast bus.

In this configuration, each input connector of the system is connected to all output processors through a dedicated broadcast bus, and each output processor is connected one to one with each output connector. Here, in the case of N input connection parts of the system, each output processing part is basically composed of a multiplexer having N inputs and one output, and each output processing part simultaneously accepts up to N ATM information cells to support the internal buffer service method. Therefore, the cells are output one by one. In this way, in the United States, as shown in FIG. 2, the output processing unit using the knockout concentrator (US, in particular, US Pat. No. 4,754,451) is proposed as a switching device.

The device consists of a packet filter, a concentrator and a shared buffer. The packet filter compares a destination address of an information cell input through a dedicated broadcast bus with a unique address of a corresponding output processor, and accepts an information cell if two addresses are correct and discards the information cell immediately if it is wrong. The concentrator uses a so-called knockout concentrator that selects only L cells (only LN) out of N information cells and transmits them to a shared buffer, which significantly reduces the total number of buffers required for device configuration. On the contrary, it is a fact that the hardware required for the centralizer to have the knockout function is complicated, and the control is complicated, and the hardware used to control the shared buffer is more complicated than the dedicated buffer method.

The concentrator used in this device is a structure that can be compared between input cells only when all input cells are synchronized due to its characteristics. Therefore, the concentrator has a complexity of synchronizing input cells at the input stage. Moreover, the concentrator can process up to L cells simultaneously. Therefore, when a phenomenon that L or more cells are simultaneously output from one input connection to one output connection occurs, only L of them can receive an output service, and the remaining cells are lost in the concentrator. In other words, if the traffic to a particular output connection is heavy compared to the traffic to the other output connection in the communication network configuration, the performance that the entire system can provide may drop sharply.

This phenomenon may occur even more in consideration of the characteristic that the traffic applied to the trunk line is relatively larger than the traffic generated in each subscriber line in the local exchange or the private exchange.

In addition, in the configuration method of the device, when the required number of input / output connections of the switch is large, the number of outputs L of the concentrator can be configured relatively small compared to the number of inputs N, so the amount of hardware required in the shared buffer, etc. is relatively high. If the number of inputs N is small, that is, 16 or less, the L value of the concentrator is not relatively small, so the reduction effect of the buffer required for the shared buffer configuration is halved. The configuration of the concentrator and the control of the shared buffer have the disadvantage of being relatively complicated compared to the number of inputs.

After all, the method of simplifying the configuration and control method while maintaining the buffer reduction effect even when the number of inputs N is small is a very important requirement in terms of the development period of the device, the difficulty of using technology, and the stability and reliability of the device. would.

The present invention devised to solve the above-mentioned problems with the prior art simplifies the control according to the reduction effect and configuration of the buffer when the number of inputs N is less than 16 and improves the performance even when traffic is concentrated to a specific output connection. It is a structure of a switching device that can be maintained, that is, a small switching device having a capacity of 16 or less, which is easier to implement and retains the advantages provided by existing switching devices. The purpose of the present invention is to provide an ATM switching device which reduces the demand for buffers used in the switching device configuration, briefly configures the internal control method, and has excellent traffic handling characteristics.

In order to achieve the above object, the present invention provides a plurality of input connection means for receiving an asynchronous transfer mode (ATM) cell from an external device; One-to-one connection to the plurality of input access means, add routing information using the virtual path identifier / virtual channel identifier (VPI / VCI) value of the information cell input through the input access means, and the virtual path identifier / gasing channel A plurality of input header converting means for allocating internal connection identification information in an identifier (VPI / VCI) area; A plurality of broadcast buses connected one-to-one to the plurality of input header converting means; A plurality of output processing means connected to each broadcast bus and outputting a plurality of cells to be outputted using a two-stage buffering method and a speed gain method; It is connected one-to-one to the plurality of output processing means and outputs an output virtual path identifier / virtual channel identifier (VPI / VCI) value using internal connection identification information in the header of an inner cell. A plurality of output header converting means for allocating to the area and for deleting the routing information area; And a plurality of output means connected to the output header converting means one-to-one and for outputting an asynchronous transfer mode (ATM) cell input from the output header converting means to the outside.

Hereinafter, an embodiment according to the present invention will be described in detail with reference to FIG. 3.

3 is a configuration diagram of a switching device according to the present invention, Figure 4 is an exemplary view of a modified cell form inside the device.

In the drawing, 1 is a plurality of input connections, 2 is a plurality of input header converter, 3 is a dedicated broadcast bus, 4 is a cell filter, 5 is an internal buffer, 6 is a selector, 7 is a common output buffer, 8 is a plurality of output processors, 9 represents a plurality of output header converters, and 10 represents a plurality of output connections, respectively.

Referring to the configuration of the switching device shown in the drawings for each functional unit as follows.

The ATM cell, which is input to the device through the input connection unit 1, is input to an input header converter 2 assigned to each input connection unit 1, and the input virtual path identifier / virtual channel identifier (VPI / Check the information of the output connection unit 10 to be outputted by the cell using the VCI) value and additionally attach h routing information 11 bytes to the header part of the input cell as shown in FIG. The cell is sent to the dedicated broadcast bus 3 connected to the converter 2. In this case, since one input cell may be a cell to be output to the plurality of output connection units 10, all desired output connection units 10 should be represented in the newly configured routing information area. For this purpose, the routing information 11 specifies the output connection 10 for which the output is desired using the position of each component bit and the value of each bit. In addition, the input VCI / VCPI area of the input cell is replaced by internal connection identification 12 in order to assign a cell-specific division within the device and a new output VPI / VCI value at the output header converter 9.

4 shows the cell shape inside the device when the output of the switching device is eight. Here, each bit position of the routing information 11 represents the output connection unit 10, and a bit having a value of 0 means that an output to the corresponding output connection unit 10 is desired. Therefore, the present apparatus simultaneously provides a point-to-point and point-to-multipoint switching function with only the configuration of the routing information 11 area without the need for additional functional modules. In FIG. 4, the spare two byte area is a spare area considering when the device's input / output expands to 16, and the total length of the cells in the device is 56, that is, in this example, h has a value of 3 and an output. Is when the number of the desired output connection 10 is 1,2,4.

In addition to the input header converter 2, the header converter also has an output header converter 9 between the output processing section 8 and the output connecting section 10. The output header converter 9 is configured for allocating different output VPI / VCI at each output connection 10 in a point-to-multipoint connection. Here, the new output VPI / VCI is assigned by the internal connection identification information 12 in the header portion of the cell input to the output header converter 9.

The dedicated broadcast buses 3 are configured in parallel in consideration of the processing speed of the device configuration hardware. That is, when the bus is configured in 8-bit parallel, the ATM cell input to the device with the speed of 155.52 Mbps is reduced to 19.44 Mbps in the device to facilitate hardware configuration.

The output processing unit 8 required by the number of output connection units 10 is composed of a cell filter 4, an internal buffer 5, a selector 6, and a common output buffer 8.

The cell filter 4 stores the cell in the internal buffer 5 when the bit position value of the routing information of the cell input through the dedicated broadcast bus 3 is 0 using the output processor 8 number in the apparatus. If 1, the cell is discarded.

The internal buffer 5 is composed of First In First Out (FIFO) elements, and the total number of input connections 1 in the apparatus is configured in each output processing section 8.

The selector 6 has a processing speed of at least twice the processing speed of the cell speed input through the dedicated broadcast bus 3, and the internal storage 5 is used as a variable for each cell storage rate. Two high internal buffers (5) are sequentially selected, and each cell of the two internal buffers (5) is sequentially read and stored in the common output buffer (7) in order. If the speed input to the internal buffer 5 is Vw, the speed at which the selector 6 reads the internal buffer 5 and stores it in the common output buffer 7 is Vr (however, Vr2Vw is related). At least two cells are stored in the common buffer 7 during the cell input time.

5 is an operational state diagram of the selector 6.

The selector 6 measures the storage of each buffer according to the up / down clock signal from each of the internal buffers 5, and selects two or more internal buffers 5 having the most storages and sequentially selects the corresponding internal buffers 5. In addition to sending the read signal to the terminals, the data signal line of the corresponding internal buffer 5 is connected to the data signal line of the common output buffer 7, and the write signal is sent to the common output buffer 7 so that the cell is connected to the internal buffer 5. To the common output buffer (7). Such a cell transfer operation is performed at least twice during the time when one cell is input to the internal buffer 5. That is, the read / write operation by the selector 6 is at least twice as fast as the cell is used in the internal buffer 5 and the speed at which the read operation is performed in the common output buffer 7.

The common output buffer 7 is constructed using a first-in first-out circuit (FIFO) having a larger capacity than the respective internal buffers 5. This is because the common output buffer 7 inputs more than twice as many cells as the amount of cells input into each internal buffer 5 within a unit time. The cells stored in the common output buffer 7 are sequentially sent to the output header converter 9 with a speed equal to the speed Vw of the cells input to the internal buffer 5. Therefore, the input / output speed of the output processing part 8 is the same, and the speed inside it operates more than twice the input / output speed. This is called speed gain.

A brief overview of the overall operation of such a device is that at least two cells passed through a cell filter are stored in an internal buffer allocated to each input of the output processor and operated at least two times per cell by a selector operating at more than twice the input rate. The above cells are extracted from the internal buffer and a large capacity is stored in the common output buffer. Cells stored in the common output buffer are sent out to the output connection one by one in the order inputted at every cell transmission time. The operation of each of these functional components is performed simultaneously asynchronously to minimize the time delay in processing time.

The effect of the present invention as described above, first, it is possible to reduce the amount of hardware required for the buffer configuration compared to the general output buffer type switching device consisting of a dedicated buffer for each input. Second, even if traffic congestion occurs in one output connection unit 10 in the switching device, processing can be performed without excessive cell loss. Third, according to the speed gain effect, not only the reduction effect of the required buffer but also the function capable of smoothly processing when the input traffic to the internal buffer 5 has a burst characteristic. Fourth, the device configuration is simple and the control logic of each functional unit is simplified because it uses a small dedicated buffer and a relatively large common buffer and speed gain method rather than using a knockout concentrator and shared buffer method such as a knockout switching device. This is simpler and easier to implement. In addition, since the output processing unit 8 of the present apparatus has a fully modular structure, the switching device can be expanded by connecting these modules in a multi-stage network. That is, the present invention is limited to the case where the capacity of the device is smaller than 16 or less, while simplifying the configuration of the device, while enhancing the processing characteristics for traffic that is simultaneously driven by a cell to one output connection.

Claims (7)

A plurality of input connection means for receiving an asynchronous transfer mode (ATM) cell from an external device; One-to-one connection to the plurality of input access means, adding routing information using virtual path identifier / virtual channel identifier (VPI / VCI) values of the information cells input through the input access means, and adding virtual path identifier / virtual channel. A plurality of input header converting means for allocating internal connection identification information in an identifier (VPI / VCI) area; A plurality of broadcast buses connected one-to-one to the plurality of input header converting means; A plurality of output processing means connected to each broadcast bus and outputting a plurality of cells to be outputted using a two-stage buffering method and a speed gain method; It is connected one-to-one to the plurality of output processing means and outputs an output virtual path identifier / virtual channel identifier (VPI / VCI) value using internal connection identification information in the header of an inner cell. A plurality of output header converting means for allocating to the area and deleting the routing information area; And a plurality of output connection means connected to the output header conversion means one-to-one and outputting an asynchronous transfer mode (ATM) cell input from the output header conversion means to the outside. 2. The apparatus of claim 1, wherein the output processing means comprises: a plurality of cell filters for storing or discarding cells by comparing routing information of cells inputted through the broadcast buses with unique addresses; A plurality of internal buffers connected to the plurality of cell filters one-to-one to store cells input from the cell filter; Is connected to each of the plurality of internal buffers to process cells from the internal buffers at a rate at least a predetermined multiple or more than a cell rate input through the broadcast bus, and stores the cell storage degree of each of the plurality of internal buffers as a variable A selector for selecting high internal buffers and reading and outputting cells from the internal buffers; And a common output buffer for storing a cell selected and output by the selector. The output buffer type ATM switching device according to claim 1 or 2, wherein the routing information is assigned the same location number as the output connection means. 4. The output buffer type ATM switching device according to claim 3, wherein each of the plurality of components is 16 or less. The output buffer type ATM switching device according to claim 4, wherein the broadcast bus is configured in parallel. 6. The output buffer type ATM switching device according to claim 5, wherein the predetermined multiple is twice the speed. The output buffer type ATM switching device of claim 6, wherein the selector selects two internal buffers having high storage and reads one cell from the corresponding internal buffer and outputs one cell.