JPH03172044A - Packet switch - Google Patents

Abstract

PURPOSE:To enable the broadcast of a packet in a switch by the read control of simple algorithm by dividing a memory circuit, which temporarily stores the input packet, into segments and storing the packet, which is outputted to each outgoing line, into the segment corresponding to the said outgoing line. CONSTITUTION:The packets to be inputted from plural incoming lines 107-108 are multiplexed with time division by a time-division multiplexer 101 and outputted to an internal bus 109. On the internal bus 109, the input cycle of this packet is divided into unit times with the same number as that of the plural incoming lines 107-108 and the packets multiplexed with time division are allocated to respective time slots. A memory circuit 103 is divided into the segments for each outgoing line of the switch. The packet allocated to the time slot on an internal bus 110 is temporarily stored in the segment corresponding to the outgoing line to output the packet. At such a time, when outputting the packet to the plural outgoing lines, the same packet is written into the plural correspondent segments.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a packet switch, and particularly to a structure of a packet switch that allows one packet to be output to a plurality of outgoing lines.

[Conventional technology]

Conventionally, as a method of switching packets input from multiple input lines and outputting them to multiple output lines, there is a method of elliptical packet switching using a time division multiplexing/demultiplexing circuit and a memory circuit for temporarily storing packets. ．． FIG. 3 is a block diagram for explaining the operation of an example of a conventional packet switch. In the figure, 201 is a time division multiplexer, 202 is a memory circuit, and 203 is a separation circuit that distributes and outputs packets to destination outgoing lines. A plurality of packets input to the packet switch from a plurality of input lines 204 and 205 are time-division multiplexed by a time-division multiplexer 201 and output to an internal bus 206. After temporarily storing this time-division multiplexed packet in the memory circuit 202,
The NrnJFl8203 reads out the packets temporarily stored in the memory circuit 202 via the internal bus 207 in an appropriate order according to a certain algorithm, and transfers the packets to a predetermined outgoing line 208.
, 209. This allows any incoming line 204.
This realizes a packet switch that outputs packets from 205 to arbitrary outgoing lines 208 and 209.

[Problem to be solved by the invention]

In the conventional bucket 1 switch described above, the memory block 2
The key to 4G is to extract packets temporarily stored in 02 using a certain algorithm, and a function to output (broadcast) one packet to multiple outgoing lines inside the switch is particularly required, but the algorithm is complex. There is a drawback.

〔Example〕

Next, the present invention will be explained with reference to FIGS. 1 and 2.

FIG. 1(a) is an overall configuration diagram showing an embodiment of the packet switch of the present invention. In the figure, 101 is a time division multiplexer, 102 is an address filter that determines to which output line the time division multiplexed packet is sent based on its address information, and 103 is an address filter that temporarily sends the packet. 04 is a separation circuit that distributes and outputs packets to the destination line.105,~1
06 is a segment obtained by dividing the memory circuit 103 for each outgoing line, and ■07. 108 are a plurality of incoming lines through which packets are input, 109, 110, and 111 are buses inside the switch, and 112 and 113 are outgoing lines through which packets l. are output.

FIG. 1(b) is a diagram for explaining the operation of the time division multiplexer in FIG. 1(a). In FIG. 1(b), packets 114 and 115 input from a plurality of input lines 107 and 108 are time-division multiplexed by a time-division multiplexer 101 and output to an internal bus 109 (time-division multiplexed packets 118, to 119). Here, address information 116, 117 indicating the destination outgoing line is added to each packet 114, 115. Packet 114,1
15, one packet is input to the switch from each input line in the packet input cycle.

On the internal bus 109, this packet input cycle is divided into the same number of unit times (hereinafter referred to as time slots) as the plurality of input lines 107, - 108, and time-division multiplexed packets 118, - 119 are divided into each time slot. FIG. 1(C) is a diagram for explaining the operation of the address filter in FIG. 1(a).Buckets time-division multiplexed on the internal bus 109?-1 18, to 119 are address filters. 102, address filter 10
2, the address information 116, - 117 (Fig. 1(b)
The outgoing line to be output is determined based on the following. At this time,
The same determination is made for packets to be output to multiple outgoing lines. The address filter 102 then sends the bucket }-1 2 0 . to the internal bus 110 . ~10 is sent.

FIG. 1(d) is a diagram for explaining the write operation to the memory circuit in FIG. 1(a).Memory circuit 18 1
03 is divided into segments for each outgoing line of the switch. Segment 105 (106) is shown in FIG.
) Temporarily stores the packets to be output to the outgoing line 112 (113). Packets assigned to the time slots 120 (121) on the internal bus 110 mentioned above are temporarily stored in the segment corresponding to the outgoing line to be output. At this time, if a packet is output to multiple outgoing lines, the same packet is written to multiple corresponding segments. Here, the memory circuit Fl@103 is designed such that data can be simultaneously written into arbitrary address positions independently in a plurality of segments.

FIG. 1(e) is a diagram for explaining the read operation from the memory circuit in FIG. 1(a).Memory circuit 10
Segment 105 on 3. The packets accumulated in ~106 are outputted to the internal bus 111 one by one from each segment. Packets 122 from segment 105 and packets 123 from segment 106 are routed to internal bus 111.
are sequentially output to the separation circuit 104. Each packet is time-division multiplexed on the internal bus 111. The order of the time slots defined on the internal bus 111 corresponds to the outgoing line, and packets are read out one by one from each segment of the memory circuit 103 in order. Separation circuit 10
4, depending on the order of the time slots, the packets 122 and 123 input in each time slot are sent to the outgoing line 11.
2, to output to 113. Output packet 124 (12
5> is packet 1 time-division multiplexed on the internal bus 111.
22 (123) extracted by the separation circuit 104. FIG. 2 is a circuit block diagram showing an example of the memory circuit in FIG. 1(a). Although only the write circuit is shown in FIG. 2 and the read circuit is omitted, the read circuit is similar to the conventional memory circuit 20 shown in FIG.
It should be the same as 2. In Figure 2, 301, 302, 3
03 is an address decoder and write control circuit;
304, 305, and 306 are memory cell areas for storing actual data; 307, 308, and 309 are word lines for selecting one of a plurality of addresses; 310,
A driver 311 drives write data of the memory circuit to the bit line 312. Also, 313,315,
317 is an address signal that specifies one of the word lines 307, 308, and 309;
318 is a write control signal that specifies whether or not to write data into the memory cell areas 304, 305, and 306, and 319 and 320 are write data of the memory circuit. Address decoder and write control circuit 301
(302 or 303) and memory cell area 304
(305 or 306) and word line 307 (30
8 or 309〉 forms one segment. now,
The segment of memory cell 304 (305, 306) will be referred to as segment 1 (segment 2. segment N). On the other hand, drivers 310, 311 and bit line 312 are shared by all segments. Write data 319, 320 are driven to bits !3 1 2 by drivers 319 and 320. If it is necessary to write data to segment l, the write control signal 314 and address signal 313 are used to write to segment 1 and determine the address location where the data is to be written. The designation is performed from outside the memory circuit.The address decoder and write control circuit 301 decodes the address signal 313 and activates one of the word lines 307.As a result, the data on the bit line 312 is activated. It is written into the memory cell in the memory cell area 304 connected to the word line.At the same time, write control signals 316, 318 and address signals 315, 3 are also transmitted in segment 2 and segment N.
17, by specifying the address position where the data is to be written, the same data can be written to any desired address position. This allows data to be written to any address location in any number of segments at once, if necessary. [Effects of the Invention] As explained above, the present invention divides the memory circuit that temporarily stores input packets into segments, and divides the packets to be output to each outgoing line into Nm segments corresponding to the corresponding outgoing line. Since it is possible to write in all segments, there is an effect that packets can be broadcast within the switch by read control using a simple algorithm.

[Brief explanation of the drawing]

FIG. 1(a) is an overall configuration diagram showing one embodiment of the packet switch of the present invention, and FIGS. 1(b) and (C) are respectively the first embodiment of the packet switch.
A diagram for explaining the operation of the time division multiplexer and address filter in Figure 1(a), Figures 1(d) and 1(e) are for the first
Figure 2 is a diagram for explaining the write operation to the memory circuit and the read operation from the memory circuit in Figure (a).
FIG. 3 is a circuit block diagram showing an example of a memory circuit in FIG. 3A, and FIG. 3 is a block diagram for explaining the operation of an example of a conventional packet switch. 1 0 1, -2
0 1... Time division multiplexer, 102... Address filter, 103, 202... Memory circuit, 104,
203... Separation circuit, 105, 106... Segment corresponding to the outgoing line, 107, 108, 204, 205.
...Incoming line, 112,113,208,209...Outgoing line, 114,115...Input packet, 116,11.
7... Address information, 118, 119120, 121
, 122, 123... time division multiplexed packet, 1
24, 125... Output packet, 301, 302, 3
03...Address decoder and write control circuit, 3
04,305,306...Memory cell area divided into segments, 307,308,309...Word line for each segment, 310,311...Data driver.

Claims (1)

[Claims] A time division multiplexer that time division multiplexes packet signals from multiple input lines, an address filter that determines which output line to output a packet based on the address information of the time division multiplexed packets, and a memory circuit that temporarily stores packets. and a separation circuit that distributes packets read out after being temporarily stored in the memory circuit for each destination outgoing line, the memory circuit is divided into segments for each outgoing line of the switch, and the address filter divides the packets into output lines to be outputted. After temporarily accumulating packets in segments on the memory circuit corresponding to has an address decoder and a write control circuit, the same data is simultaneously written to arbitrary address positions of an arbitrary number of segments, and the time-division multiplexed packet is simultaneously written to a plurality of segments of the memory circuit. packet switch.