JPS6372294A - Variable band time switch - Google Patents

Abstract

PURPOSE:To exchange information of various communication speeds unitarily under less hardware by setting a communication channel variably and attaining write/read in/from a channel memory accordingly. CONSTITUTION:Communication information sent via an incoming highway 12 is written in a channel memory 30 by a channel memory write means 2. The boundary of each communication channel is detected by a detection means 4 and the channel memory write address at that time is stored in the conversion means 6 at each detection. The channel memory 30 allows the conversion means 6 to generate a read address sequentially from a head address coprresponding to the communication channel at each communication channel in an output communication information stream to an outgoing highway 14 in the head address corresponding to the communication channel stored therein by using an address generation start means 9 and the read address is read by allowing to the channel memory read means 8 to correspond thereto.

Description

[Detailed Description of the Invention] [Summary] While writing information units on the incoming highway into the communication path memory, the communication path memory write address at the time of detection of each communication channel identifier in the information stream is retained. , causes the generation of sequential read addresses for the information units within the communication channel from each of the retained write addresses to output the exchanged communication information stream from the channel memory to the output highway.

[Industrial application field]

The present invention relates to a variable bandwidth switch, and more particularly to a variable bandwidth switch that allows unified exchange of communication channels of different communication speeds.

The characteristics of the information to be exchanged by an exchange system are wide-ranging, and these characteristics can be expressed in particular by its communication speed (bandwidth), holding time, and burst nature. Burst nature refers to a state in which valid information is not communicated even though communication is in progress.For example, in still image services, users generally do not request the next still image until they have finished viewing the still image. During this time, no significant information is flowing through the communication path formed in the communication network. Also, the communication speed for voice is usually 64K b
/s, but when it comes to video images, it is several hundred Mb/s.
s, and covers a wide range.

Therefore, in an exchange system, there is a need for a function to efficiently exchange information having a large difference in communication speed as described above in the communication path where information is actually exchanged.

[Conventional technology]

Conventionally, the time-division circuit switching method and the packet switching method are known as technologies for configuring digital switched communication paths.

The time-division circuit switching method uses a unit called a time slot as the unit of switching. FIG. 6 shows an example of the configuration of a basic time switch used in this method. The time switch consists of a channel memory 100, a holding memory 102, counters 104, 106, a selector 108, and data holding flip-flops FF110, 102. This time slot has a function of changing the time order of time slots on the highway where multiple time slots are time-division multiplexed. FIG. 7 shows a time chart for the main highway and the exit highway, and there are n + l III time slots from O to n in a frame that is repeated every 125tI3. The information on the time slots of the input highway is sequentially written into the communication path memory 100 according to the value of the counter 104 that has passed through the selector 108. The destination of the time order is stored in advance in the holding memory. The counter 106 corresponds to (synchronizes with) the time slot number of the outgoing highway, and the counter 106 is O when the time slot is O of the outgoing highway. Holding memory 1 specified by the value of counter 106
The contents of 02 are read out, and the contents of the address in the channel memory 100 pointed to by that value are read out and output onto the outbound highway. As a result, the time order of the incoming highway and the outgoing highway can be interchanged according to the holding memory 102.

[Problem that the invention seeks to solve]

In the above-mentioned conventional time-division line system, the communication path consists of a communication path memory 100 . It is formed by holding memory 102. In order to exchange faster information, for example 64 Kb/s x 1, under this scheme, multiple time slots must be used simultaneously. Mere expansion thereof not only makes the exchange possible only after taking measures to preserve the order of time slots, but also requires the use of large-capacity channel memory and holding memory. For example, 64 Mb
/ To exchange information on s, for that purpose 64
As much as 1001 holding memories are required for the Kb/S information.

The present invention was made to solve such problems,
An object of the present invention is to provide a variable bandwidth switch that enables unified exchange of information on various communication speeds with less hardware.

[Means for solving problems]

FIG. 1 shows a block diagram of the principle of the present invention. As shown in the figure, the present invention includes a communication path memory 3o connected to an incoming highway 2 and an outgoing highway 14, a communication path memory writing means 2 for writing information units into the communication path memory 30, and a communication path memory 3o connected to an incoming highway 2 and an outgoing highway 14. detection means 4 for detecting each of the boundaries of the communication channels, holding the start address of the communication channel corresponding to the detection written by the communication path memory writing means 2 for each detection, and writing from each of the start addresses within the communication channel. converting means 6 for generating read addresses for sequentially reading information units of , communication path memory reading means 8 for outputting an output communication information stream onto the outgoing highway 14 in response to the sequential read addresses; address generation starting means 9 for starting generation of read addresses sequentially from the held head address corresponding to sequential communication channels in the output communication information stream to the output highway 14 for each communication channel order; A variable bandwidth time switch is constructed from the following.

[For production]

The communication information transmitted via the input highway 12 is sequentially written into the communication path memory 30 by the communication path memory writing means 2 in predetermined information units. The boundary of each communication channel in the communication information stream to be written is detected by the detection means 4, and each time the boundary of each communication channel is detected, the communication path memory write address (the start address of the communication channel) at that time is held in the conversion means 6. (.

Then, the address generation start means 9 converts the communication path memory into the conversion means 6 and outputs the start address corresponding to the communication channel held therein for each successive communication channel in the output communication information stream to the output highway 14. Readout is performed by sequentially generating readout addresses from the first address corresponding to the communication channel, and causing the communication path memory readout means 8 to respond to the readout addresses.

Therefore, communication channels having different communication speeds on the incoming highway 12 can be exchanged to the outgoing highway 14 in a unified manner. Furthermore, it is possible to quickly respond to changes in communication speed and realize highly flexible exchange.

〔Example〕

FIG. 2 shows an embodiment of the invention. In this embodiment, two variable bandwidth time switches IOA and IOB, which are switched by a switching clock, are provided between the main highway 12 and the outbound highway 14. Both of these variable band time switches 10A and i0B include a boundary identifier detector 16, a counter 18, a counter 22, a holding memory 24, and a counter 26.
, selectors 28 and 29 are shared.

Other corresponding components of both the variable bandwidth time switches IOA and IOB will have the same reference numerals with additional letters A and B for each variable bandwidth time switch to distinguish these components. Only the components of the switch IOA will be described.

30A is a communication path memory whose input is input highway 12.
The output can be connected to the output highway 14 via the selector 29.

Its storage formant is shown in FIG. 32A is a selector that provides the count output of the counter 18 or the output of the holding memory 20 to the conversion memory 34A as an address for the conversion memory 34A; the switching means is not shown for clarity of the drawing. . Conversion memory 34A has the output of counter 22 connected to its stored data input. The output of the translation memory 34A is connected to a counter 36A which sets the translation memory (34A) output value in response to the boundary identifier output from the channel memory (30A) and sets the output value once every time slot on the highway. It is configured so that the count is only counted up. The output value of counter 36A or the output value of counter 22 is alternatively supplied via selector 38A as an access address for channel memory 30A. This alternative control is effected by the write/read control signal on line 40A. In conjunction with this, switching between writing and reading of the communication path memory 30A occurs, but the details are omitted because it would unnecessarily complicate the drawings.

Further, the alternative control of the selector 38A and the selector 38B, that is, the switching between the time switch IOA and the time switch IOB is effected by the switching clock as described above.
The selector 38A receives the switching clock via the inverter 20, and the selector 38B receives the switching clock directly.

28 is a selector that provides the counter 26 with the boundary identifier output from the channel memory 30A or 30B.

In addition, in the figure, 2A and 2B are 2 in FIG. 1, and 6A.

6B corresponds to 6 in FIG. 1, and 8A and 8B correspond to 8 in FIG. 1, respectively.

The operation of the variable bandwidth time switch of the present invention having the above configuration will be explained below.

The formant of the time division multiplexed signal transmitted via the input highway 12 is as shown in FIG. 3, which is just an example, in which one frame is formed every 125 μs. And Bl.

B2. B3. . . . is a communication channel boundary identifier, which is placed in the signal stream using, for example, a violation of the encoding rules of the CMI code. The information from one identifier to the next constitutes one communication channel (basket), and each communication channel is configured to have a plurality of variable time slots each having a length of 8 pints as a unit of channel operation.

The signals in each basket of the time-division multiplexed signal stream in the formant as described above are processed by a counter that is counted up for each time slot while the variable bandwidth time switch IOA is switched by the switching clock (4!-1z). Each of the 22 count values is sequentially given to the communication path memory 30A via the selector 38A as a write address to the communication path memory 30A, so that they are sequentially written into the communication path memory 30A. As the writing progresses, each time the boundary identifier included in the time division multiplexed signal is detected by the boundary identifier detector 16, a detection signal is generated and the counter 18 is incremented by one. Each time the counter 18 counts up, the count value (basket number) is supplied as an address to the conversion memory 34A via the selector 32A, and the count value of the counter 22 is written to that address. Thus,
The basket start address on the frame is in the conversion memory 34
Stored in A.

The above was about writing to the variable bandwidth switch IOA, but when the switching clock turns the write control to writing to the variable bandwidth switch IOB, writing to the channel memory 30B is performed using the count value of the counter 22. is caused by being supplied as an address to the channel memory 32B via the selector 38B, and writing of the basket start address on the frame to the conversion memory 34B is caused by supplying the count value of the counter 18 to the selector 32B.
This is achieved by supplying the address as an address to the conversion memory 34B via the address and writing the count value of the counter 22 at that time to that address.

Reading of the exchanged signal written to the channel memory as described above is carried out as follows.

Prior to the readout, addresses corresponding to the communication channel strings constituting the exchange frame format on the outgoing highway are sequentially written into the holding memory 24 by a call processing function (not shown) that is activated when an exchange call occurs. ing.

At the start of the above-mentioned readout, the counters 26 and 36A are reset to the readout start address, for example, zero, and when the above-mentioned readout starts, the contents of the memory (24) holding the readout start address are transferred to the conversion memory via the selector 32A.
(34A) The start address of the frame start communication channel (basket) on the outgoing highway is supplied to the conversion memory 34A as a read address, and from there the start address of the frame start communication channel (basket) on the outgoing highway is supplied to the conversion memory 34A.
A and set in the counter 36A.

Every time the communication path memory 30A is read from the address read by the counter 36A (every time slot), the counter 36A counts up.
The count value is then used for reading the communication path memory 36A, and the communication channel information stream is sent to the output highway 14.

The next communication channel (basket) is read by reading out the basket boundary signal (stored in the format shown in FIG. 4 for each time slot) indicating the end of the channel being read from the communication path memory 30A. will be started. When the basket boundary signal is detected, the counter 26 is incremented by the signal passed through the selector 28, and the next communication channel number is read from the next address in the holding memory.

This is input to the conversion memory 34A, and the start address of the communication channel is output and loaded into the counter 36A. Reading of each time slot occurs in a manner similar to the reading of the leading communication channel described above.

The above reading explanation was about reading from the communication path memory 30A, but by controlling the switching clock, the communication path memory 3
The reading of 0A is switched to the reading of the communication path memory 30B, but after the switching, the holding memory 24
The read contents are sent to the conversion memory 34 via the selector 32B.
The contents read from the conversion memory 34B are set in the counter 36B and counted and amplified, while each value is sequentially applied as a wash address to the channel memory 30B via the selector 38B and the readout is performed. The output highway 1 is generated via the selector 29.
The time division multiplexed signal stream after the exchange is output onto 4.

FIG. 5 shows another embodiment of the invention. This example is the second
The two variable bandwidth time switches in the illustrated embodiment are expanded to a plurality of variable bandwidth time switches 10. . . . The switching means for 1ON is configured to output selection information corresponding to the communication channel on the outgoing highway from the holding memory 24 from the switching clock in the embodiment of FIG. 2, and the decoder 5 receives the selection information.
0, and the output signal of the decoder 50 is connected to the selectors 38A and 38B which receive the switching clock in the embodiment of FIG.
381 (not shown) (i=1 to N) corresponding to the selection inputs, and the other time switch configurations are the same as in FIG. 52.54 is an OR circuit. 52 is 2 in Figure 2
9, and 54 corresponds to 28 in FIG.

Note that in the above embodiments, the holding memory and the conversion memory may be addressable registers.

〔Effect of the invention〕

As described above, according to the present invention, communication channels can be set variably, and writing and reading to and from communication path memory can be performed accordingly. This makes it possible to perform centralized exchange to highways, and also realizes flexible exchange that can quickly respond to changes in communication speeds.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention; FIG. 2 is a diagram showing an embodiment of the present invention; FIG. 3 is a diagram showing the format of the input highway; FIG. 4 is a diagram showing the format of the communication path memory; FIG. 5 is a diagram showing another embodiment of the present invention, FIG. 6 is a configuration diagram of a conventional time switch, and FIG. 7 is a time chart for the time switch shown in FIG. In FIGS. 1, 2, and 5, 10, IOA, IOB, 10. ~10? J is a variable bandwidth time switch; 2.2A and 2B are channel memory writing means; 4 is a detection means; 6.6A and 6B are conversion means; 8.8A and 8B are channel memory reading means; 12 is an input highway; 14 is an output highway, and 30. 30A and 30B are communication path memories. Ichiyahme Otori F'guchi, 77th man, Figure 1

Claims (2)

[Claims] (1) Incoming highway (12) and outgoing highway (14)
a communication path memory (30) connected to the communication path memory (30), a communication path memory writing means (2) for writing each predetermined information unit into the communication path memory (30), and a communication channel boundary on the input highway (12). Detection means (4) for detecting each of the above, and holding the start address of the communication channel corresponding to the detection written by the communication path memory writing means (2) for each detection, and writing from each of the start addresses in the communication channel. converting means (6) for generating read addresses for sequentially reading out information units; and channel memory reading means (8) for outputting an output communication information stream onto the output highway (14) in response to said sequential read addresses. and converting means (6) to generate sequential read addresses from the held head address corresponding to sequential communication channels in the output communication information stream to the output highway (14) for each communication channel order. and address generation initiating means (9) for initiating address generation. (2) A plurality of the communication path memories (30) are provided, and means is provided for switching and using the communication path memory writing means, conversion means, and communication path memory reading means for each communication path memory, and 2. The variable bandwidth time switch according to claim 1, wherein the write address generating means for each communication path memory writing means is common to each communication path memory writing means.