JPS6190542A - Frame aligner - Google Patents

Abstract

PURPOSE:To generate a multiple signal allocated concentratedly at an interval of frames on a small scale circuit by providing two plastic storage memories, a control section discriminating which of read signals to be outputted and a selecting output circuit of the said signal. CONSTITUTION:A frame synchronizing circuit 12 write reset signals WR1, WR2 having double period of the frame period and shifted by 1/2 period. An input signal WD is written on the elastic memories 13, 14 by one frame's share, which use a read reset signal RR as a high-speed lumped burst signal to output signals RD1, RD2. The logical level of a selection signal SEL of a selection control circuit 16 is changed at each period being twice the period of the signal RR, the circuit 15 selects one of the signals RD1, RD2 based on the logical level and gives it to a multiplex section. When the phase relation between the selected memory signal WR1 and the signal RR enters an inadequate time region, the phase comparison circuit 17 gives a trigger signal to the selection control circuit 16. Thus, the circuit 16 inverts the signal SEL and the circuit 15 switches an output signal RD.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a frame aligner (phase synchronized memory) provided in a switching center in a digital communication network.

[Conventional technology]

In the current digital communications field, there is a need to perform various signal processing at the digital signal level. Alternatively, a frame aligner circuit is usually provided that transfers the digital signal transmitted from the device to a clock signal within its own station or device and determines the phase to the reference phase, that is, performs phase synchronization. .

The configuration of the conventional interface section equipped with a frame aligner and the multiplexing section and the signals of each section are shown in Fig. 4(a),
Shown in (C) and (d). Each interface section 41.42
．． A claim aligner (not shown) installed in 43.
Y,,HY,, HY,,f(signals A, B, C input with arbitrary frame phases via Y4.

D (see Figure 4(b)), the clock signal is transferred to the same speed clock signal or a clock signal close to it, so that all the output signals from each interface section 41, 42, 43, and 44 have the same frame phase. (Figure 4 (C)
Furthermore, the multiplexing unit 45 performs multiplexing in units of 1 bit (bit multiplexing) or multiplexing in units of 8 bits (octet multiplexing) to generate high-speed digital multiplexed signals (
(see FIG. 4(d)).

Therefore, in conventional frame aligners, the speed of the digital input signal is shifted to the same speed or a speed close to it. Since the incorrect area where the write frame phase approaches the read frame phase of the elastic store memory and the data within the same frame moves back and forth between frames is only a fraction of the frame length, the digital input signal A delay circuit of one scale type is provided for the ElastiStore memory, and the write frame phase to the Elastlast store memory can be written in two types of phases, with and without delay. We were able to satisfy the function with a configuration in which the phase is corrected so that it falls into the appropriate region by inserting or removing it.

[Problem that the invention seeks to solve]

Nowadays, signal processing at the high-speed digital multiplex signal level has become popular, and it is becoming necessary for signal multiplexers to centrally arrange multiplexed signals at frame intervals.

The configuration method for generating the high-speed digital multiplexed signal with the above-mentioned concentrated arrangement involves further changing the arrangement of each bit for the bit multiplexed or octet multiplexed distributed multiplexed signal shown in FIG. 4(d). There is a method of centrally deploying the hardware to do so. However, it is necessary to add hardware for converting the bit arrangement, and such hardware requires a high-speed operation memory element, which has the disadvantage of lowering economic efficiency.

An object of the present invention is to provide a frame aligner that can generate high-speed digital multiplexed signals centrally arranged at frame intervals with a small hardware scale.

[Means for solving problems]

FIGS. 3(a), (b), (C), and (d) are diagrams showing the configuration of an interface section and a multiplexing section including a frame aligner according to the present invention, and signals of each section. From the opposite station or device to each highway HY1. HY,,HY3,
Signals A, B, C, and D (see FIG. 3(b)) input with arbitrary frame phases via HY4 are connected to the frames provided in the respective interface sections 31, 32, 33, and 34. An aligner (not shown) generates a signal that can be easily multiplexed by the multiplexer 35 at the next stage, that is, a concentrated burst signal faster than this input signal (see FIG. 3(C)).
reference) and sent to the multiplexer 35. Then, the multiplexing unit 35 generates high-speed digital multiplexed signals arranged centrally at frame intervals.

One feature of the 7-frame aligner according to the present invention is that it uses two elastic store memories for writing input signals. The writing of input signals to these two elastic store memories is shifted by half a period from each other with a period twice the frame period of the signal inputted from the opposing station or device with an arbitrary 7-frame phase. Each is performed by two different write reset signals. Further, reading from these two elastic store memories is performed simultaneously by a read reset signal issued from within the own station or within the own device. However, as mentioned above, due to the phase relationship between the write reset signal and the read reset signal, there may be an inappropriate time region in which data within the same frame moves back and forth between frames. Depending on this phase relationship, one of the read signals from the two may fall into an inappropriate time domain. In other words, depending on the phase relationship of the other signal, both signals exist in the appropriate time domain and are informationally accurate signals.

Therefore, the phases of the write reset signal and the read reset signal are compared, and based on the comparison, it is determined which of the above two read signals (high-speed concentrated burst signals) from the elastic store memory should be output. The above object can be achieved by providing a control section that issues a selection signal and further providing a selection circuit that selectively outputs one of the high-speed concentrated burst signals based on the selection signal.

That is, the 7-frame aligner according to the present invention receives a digital input signal transmitted from an opposing station with a frame synchronization signal in the frame at an arbitrary frame phase, detects the frame synchronization signal, and performs the processing based on the detected frame synchronization signal. A frame synchronization circuit that establishes frame synchronization of the input signal described above and generates first and second write reset signals that are shifted by half a period from each other with a period twice the frame period. From the time when the 2 write reset signals are respectively input, the above input signals are written for one frame, respectively, and from the time when the read-out from the own station side - the reset signal is input, the written input signals are read respectively. Te!1!1. Compare the phases of the first and second elastic store memories that are output as the second high-speed concentrated burst signal and the above-mentioned first or second write reset signal and read reset signal, and Based on the comparison, the first
, a control unit that determines which of the second high-speed concentrated burst signals should be output and issues a selection signal; and a control unit that determines which of the second high-speed concentrated burst signals should be output and issues a selection signal; and a selection circuit that selectively outputs one of the two. [Example] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

- FIG. 1 is a block diagram of an embodiment of a frame aligner according to the present invention, and this frame aligner is provided in each interface section 31, 32, 33, and 34 shown in FIG. 3(a). The input terminal 11 is connected to each highway HY,, HYl, HY,, HY, (Fig. 3) from the opposite station or device.
This is a terminal for a digital input signal WD which is input with an arbitrary frame phase via a). This input signal WD includes a frame synchronization signal in the frame, and is input to the frame synchronization circuit 12 as well as to the elastic stores 13 and 14 that store signals for one frame. Ru.

The frame synchronization circuit 12 detects a frame synchronization signal in the input signal WD, establishes frame synchronization of the input signal WD based on it, and also outputs write reset signals WR1 and WR that are shifted by half a cycle from each other with a period twice the frame period. , and each elastic store memory 13.1
Send to 4.

In the elastic store memories 13 and 14, when the respective write reset signals WR and WR are input, from that point on, the aforementioned input signal WD is written for one frame, and the read reset signal RR from the input terminal 18 is written. When input, from that point on, the signals for four I-frames written above are output as high-speed concentrated burst signals as read data signals RD, RD, respectively, and both are sent to the selection circuit 15.

The selection control circuit 16 generates a selection signal, signal SEL, and this selection signal SEL changes its logic level to @O# every twice the period of this signal RR in synchronization with the read reset signal RR. from @1” or from @1# to ’”0
It is changed to #. The selection signal SEL is sent to the selection circuit 15 and the phase comparator circuit lt, and the selection circuit 15 selects either one of the above-mentioned read data signals RD1 and RD based on the theoretical level of the selection signal SEL, and selects one of the read data signals RD1 and RD as a high-speed concentrated burst. Output signal RD is output as a signal. This output signal RD is sent to the multiplexer 35 (see FIG. 3(1)) through the output terminal 19.

The phase comparison circuit 17 receives a write reset signal WR.

A circuit for comparing the phase relationship between the selection signal SEL and the selection signal SEL,
If the phase relationship changes and the phase relationship of the elastic store memory selected as the output signal RD, for example, the write reset signal WR of 13 and the read reset signal RR, enters the above-mentioned inappropriate time region, another A trigger signal TS is applied to the selection control circuit 16 to select the output signal RD of the elastic store memory 14. In response to this trigger signal TS, the selection control circuit 16 inverts the selection signal SEL and sends it to the selection circuit 15. As a result, the output signal RD is switched from RDl to RD.

Figure 2 is a diagram showing the relationship between the signals of each part mentioned above.
The operation will be explained with reference to FIG.

First, the input signal WD transmitted from the opposing device or station is written into the elastic store memories 13 and 140, respectively, in synchronization with the write reset signals WR1 and WR from the frame synchronization circuit 12.

Next, in synchronization with the successive reset signal RR, read data signals RD, RD! from each elastic store memory 13, 14, respectively. is output. Write reset signal WR1 and selection signal SEL shown in FIG.

That is, in terms of the phase relationship with the read reset signal RR, in frame #l, the read data signal RD2 is
In frame #2, the read data signal RD is in a more appropriate time domain, so the selection circuit 15 outputs the output signal R.
As D, RD is selectively output in frame #1, and RD is selectively output in frame #2.

If the relationship between signals WR1 and RR changes, in other words, if the input signal phase and the internal phase of the device shift and the signal RD in 7th frame #l enters an inappropriate time domain, the phase comparator circuit 17 and the selection control circuit 16 function, the selection signal SEL is inverted, and as a result, frame #1I
RDl is better in C, but RD in frame #2
, is selected and output.

In other words, regardless of the relationship between the input signal phase and the internal phase of the device, the high-speed concentrated burst signal R is informationally accurate.
D is output. Therefore, it is possible to reduce the circuit scale of the multiplexing unit 35 that post-processes this signal RD, and considering that the elastic store memory 13. Since the interface parts 31 to 3 can be realized
This is also advantageous from the viewpoint of downsizing or increasing the density of 4.

〔Effect of the invention〕

As explained above, the present invention makes it possible to generate high-speed digital multiplexed signals centrally arranged at frame intervals with a small hardware scale, and therefore has the effect of preventing a decrease in economic efficiency.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a 7-frame aligner according to the present invention, FIG. 2 is a diagram showing signals of each part of the frame aligner shown in FIG. 1, and FIGS. 3(a), (b), (C ), (d)
4 is a diagram showing the configuration of an interface unit equipped with a frame aligner and a multiplexing unit according to the present invention, and signals of each part;
Figures (a), 0), (0), and (d) are diagrams showing the configurations of an interface section and a multiplexing section including a conventional 7-frame aligner, and the signals of each section.

Claims (1)

[Scope of Claims] A digital input signal transmitted from an opposing station with a frame synchronization signal in the frame at an arbitrary frame phase is received, the frame synchronization signal is detected, and the input signal is transmitted based on the frame synchronization signal. a frame synchronization circuit that establishes frame synchronization of the frame synchronization and generates first and second write reset signals that are shifted by half a cycle from each other with a period twice that of the frame synchronization; The input signal is written for one frame each from the time of input, and the written input signal is read from the time of inputting the read reset signal from the local station side, respectively, as the first and second high-speed concentrated burst signals. The first output
, a second elastic store memory, and compares the phases of the first or second write reset signal and the read reset signal, and determines which of the first and second high-speed concentrated burst signals is selected based on the comparison. a control unit that determines whether the signal should be output and issues a selection signal; and a selection circuit that selects and outputs either the first or second high-speed concentrated burst signal based on the selection signal from the control unit. A frame aligner characterized by: