JPH0936846A - Clock reproducting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the frequency jitter of a reproduced clock generated by the fluctuation of a voltage control signal inputted to a voltage control oscillator when a clock reproduction mode is switched. SOLUTION: When a clock reproduction mode informing signal 117 is an SRTS clock reproduction mode, a selector 134 outputs an intermediate value signal 132 to an adaptive clock reproduction low pass filter 135. The adaptive clock reproduction low pass filter 135 sets an adaptive clock reproduction voltage control signal 116 to a middle signal level between a high level and a low level. Thus, the fluctuation amount of the voltage control signal 118 when the clock reproduction mode is switched from the SRTS clock reproduction mode to an adaptive clock reproduction mode is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of reproducing a transmission clock of fixed speed data transferred via a network in an asynchronous transfer mode, using a synchronous time stamp residual indicating frequency information of the transmission clock. The present invention relates to a clock regenerator which is performed by combining two methods of using a buffer amount of a buffer for storing fixed speed data.

[0002]

2. Description of the Related Art A conventional clock recovery device will be described below. FIG. 7 shows the configuration of a conventional clock recovery device. In FIG. 7, reference numeral 701 denotes a reception protocol data unit including a header part and an information part, in which the information part describes fixed speed data, and the header part describes synchronization time stamp residual information indicating frequency information of a transmission clock of the fixed speed data. , 702 is a network clock, 703 is a header pulse indicating the arrival timing of the reception protocol data unit 701, and 704 is the reception protocol data unit 70.
No. 1 information part stores a received data storage part, 705 a write control part for controlling data writing to the received data storage part 704, and 706 detects synchronous time stamp residual information from the header part of the reception protocol data unit 701. SRTS detection unit, 707 is received data storage unit 70
A data write signal for writing data to 4;
8 is a data storage amount notification signal indicating the amount of data stored in the received data storage unit 704, and 709 is the lower 4 bits of the transmission time value measured every N bits of fixed speed data transmitted on the fixed speed data transmission side. This is a part of the synchronization time stamp residual information notification signal.

Reference numeral 710 is a clock reproduction mode switching unit for switching between two modes, SRTS clock reproduction mode and adaptive clock reproduction mode, according to the amount of data stored in the received data storage unit 704, 711 is a selector which is a voltage control signal switching means, 712. Is a voltage controlled oscillator, and 713 controls the frequency of the output signal of the voltage controlled oscillator 712 according to the frequency information indicated by the synchronization time stamp residual information.
An RTS clock recovery control unit 714 controls the output of the voltage oscillator 712 so that the data storage amount of the received data storage unit 704 maintains a reference value.
Reference numeral 715 denotes an SRTS clock reproduction voltage control signal generated by the SRTS clock reproduction control unit 713, and 716.
Is an adaptive clock reproduction voltage control signal generated in the adaptive clock reproduction control unit 714, 717 is a clock reproduction mode notification signal, 718 is a voltage control signal, 719 is a reproduction clock, and 720 is data read from the received data storage unit 704. A read control unit 721 is a data read signal for reading data from the received data storage unit 704, and 722 is fixed speed data read from the received data storage unit 704.

Reference numeral 723 is a reception protocol data unit 7
A phase comparison pulse having N bits of fixed speed data stored in the information section 01 as one cycle, 724 is a reference pulse reproduced every N cycles of the reproduction clock 719, and 725 is a synchronous time stamp residual information notification signal. 709 is used to generate the phase comparison pulse 723, 726 is a frequency dividing circuit for generating the reference pulse 724 using the recovered clock 719, and 727 is the phase comparison pulse 723 and the reference pulse 724. Of the phase comparison output signal indicating the phase difference between the phase comparison pulse 723 and the reference pulse 7
24 is a phase comparator that compares the phases of 24, 729 is a low-pass filter for SRTS that removes high frequency components of the phase comparison output signal 727, and 730 is data that indicates that the amount of data stored in the received data storage unit 704 exceeds the reference value. A storage level notification signal, 731 is a data storage level notification signal output section that outputs a data storage level notification signal 730 using the data storage amount notification signal 708, and 732 is an adaptive clock reproduction that removes high frequency components of the data storage level notification signal 730. It is a low pass filter for.

Next, the operation of the above conventional example will be described. FIG.
A timing chart for explaining the operation is shown in FIG. In FIG. 8, 81 is a data storage amount notification signal (708), and 82 is a voltage control signal (718).

In the write control unit 705, the information part of the reception protocol data unit 701 is the reception data storage unit 70.
At the timing of arriving at 4, the write signal 707 is activated and output. The reception data storage unit 704 stores the received reception protocol data unit 701 when the write signal 707 is active and stores the read signal 7
When 21 is active, the stored data is output as fixed speed data 722 at the speed of the reproduction clock 719. Further, the reception data storage unit 704 outputs the stored data amount as a data storage amount notification signal 708. The SRTS detection unit 706 detects the synchronization time stamp residual information described in the header part of the reception protocol data unit 701, and outputs it as the synchronous time stamp residual information notification signal 709 to the phase comparison pulse generation unit 725. The read control unit 720 activates the data read signal 721 when the amount of data stored in the received data storage unit 704 exceeds the reference value for the first time, and reads the data until the data stored in the received data storage unit 704 is exhausted. Activate 721.

The clock reproduction mode switching section 710 is
When the data storage amount indicated by the input data storage amount notification signal 708 is larger than the upper limit value of the data storage amount of the reception data storage unit 704 or smaller than the lower limit value of the data storage amount of the reception data storage unit 704, the clock The clock recovery mode notification signal 717 indicates the adaptive clock recovery mode, and the clock recovery mode notification signal 717 indicates when the data storage amount is smaller than the upper limit value and larger than the lower limit value of the data storage amount of the received data storage unit 704. The clock reproduction mode is referred to as SRTS clock reproduction mode.

The phase comparison pulse generation unit 725 restores the time stamp indicating the transmission time for each N bits of the fixed speed data based on the input synchronization time stamp residual information notification signal 709, and the fixed speed data N A pulse is generated at each bit time and output as a phase comparison pulse 723. The frequency divider circuit 726 uses the input reproduction clock 71.
A pulse is generated every N cycles of 9 and is output as a reference pulse 724. The phase comparator 728 compares the phases of the input phase comparison pulse 723 and the reference pulse 724, and the phase of the reference pulse 724 is the phase comparison pulse 72.
When it is ahead of the phase of 3, the phase comparison output signal 7
When the phase of the reference pulse 724 is delayed from the phase of the phase comparison pulse 723, the phase comparison output signal 727 is output as a high level. SR
The TS low-pass filter 729 removes the high frequency component of the input phase comparison output signal 727 and outputs it as an SRTS voltage control signal 715.

Data storage level notification signal output unit 731
Compares the input data storage amount notification signal 708 with a reference value, and when the data storage amount exceeds the reference value, sets the data storage level notification signal 730 to a high level and the data storage amount exceeds the reference value. If not, the data storage level notification signal 730 is output as a low level. The adaptive clock reproduction low-pass filter 732 removes the high frequency component of the input data storage level notification signal 730 and outputs it as an adaptive clock reproduction voltage control signal 716.

When the clock reproduction mode is the adaptive clock reproduction mode, the selector 711 selects the adaptive clock reproduction voltage control signal 716 and outputs it as the voltage control signal 718. When the clock reproduction mode is the SRTS reproduction mode, the SRTS reproduction is performed. The voltage control signal 715 is selected and output as the voltage control signal 718.

When the input voltage control signal 718 has a signal level equal to an intermediate value between a high level and a low level, the voltage control oscillator 712 generates a clock having a center frequency and outputs it as a reproduction clock 719, and outputs the voltage control signal. 71
The frequency of the reproduction clock 719 is increased according to the increase of the signal level with respect to the intermediate value between the high level and the low level of 8 and the decrease of the signal level with respect to the intermediate value between the high level and the low level of the voltage control signal 718 is increased. Then, the frequency of the reproduction clock 719 is decreased.

As described above, also in the above-described conventional case, when the data storage amount of the reception data storage unit 704 continues to increase or decrease and the data storage amount exceeds the upper limit value or the lower limit value, the adaptive clock reproduction control unit 714 operates. By controlling the frequency of the reproduction clock 719 so as to return the data storage amount to the reference value, the clock reproduction can be performed without causing an underflow or overflow in the reception data storage unit 704.

[0013]

However, in the above-described conventional clock regenerator, the selector 111, which is the voltage control signal switching means, changes the voltage control signal from the SRTS clock regeneration voltage control signal 715 to the adaptive clock regeneration voltage control signal. When switched to 716, the signal level of the SRTS clock reproduction voltage control signal 715 is substantially equal to the intermediate value between the high level and the low level, and the signal level of the adaptive clock reproduction voltage control signal 716 becomes the high level or the low level. Therefore, there is a problem in that the signal level of the voltage control signal 718 fluctuates greatly and a large frequency jitter occurs in the reproduced clock 719 output from the voltage control oscillator 712.

The present invention solves the above-mentioned problems of the prior art. When the voltage control signal is switched from the SRTS clock reproduction voltage control signal to the adaptive clock reproduction voltage control signal, the frequency jitter generated in the reproduction clock is eliminated. An object of the present invention is to provide a clock recovery device that can be reduced.

[0015]

In order to achieve the above object, the first configuration of the clock reproducing apparatus of the present invention is such that when the data storage amount of the received data storage means is between the upper limit value and the lower limit value. , An intermediate value signal equal to an intermediate signal level between the high level and the low level is selected and output, and when the data storage amount of the reception data storage means exceeds the upper limit value or falls below the lower limit value, the data storage amount notification signal Is provided with an intermediate value signal selection output means for selecting and outputting.

In order to achieve the above object, in the second configuration of the clock regenerating apparatus of the present invention, an ARTS clock regenerating voltage control signal and an adaptive clock regenerating voltage control signal are used instead of the intermediate value signal selecting and outputting means. Compare the signal levels, S
A signal level comparison means that outputs a signal level comparison result notification signal that becomes a high level when the RTS clock reproduction voltage control signal has a higher signal level and a low level when the adaptive clock reproduction voltage control signal has a higher signal level. When the data storage amount of the received data storage means is between the upper limit value and the lower limit value, the reference value is decreased when the signal level comparison result notification signal is high level, and the signal level comparison result notification signal is low level. Sometimes, it is provided with data storage amount reference value control means for increasing the reference value and outputting it to the data storage level notification signal generation means.

In order to achieve the above-mentioned object, in the third configuration of the clock reproducing apparatus of the present invention, instead of the intermediate value signal selecting and outputting means, the data storage amount of the reception data storing means is between the upper limit value and the lower limit value. If the data storage level of the received data storage means exceeds the upper limit value or falls below the lower limit value, the SRTS clock recovery voltage control signal is selected and output. Is provided with a SRTS clock reproduction voltage control signal selection and output means for selecting and outputting.

[0018]

According to the first aspect of the present invention, the intermediate value signal selecting and outputting means outputs the intermediate value signal to the adaptive clock reproducing low pass filter when the clock reproducing mode is the SRTS clock reproducing mode, and the clock reproducing mode. Is SR
The voltage at the time of switching the voltage control signal by making the signal level of the voltage control signal for adaptive clock reproduction at the time of switching from the TS clock reproduction mode to the adaptive clock reproduction mode equal to the intermediate signal level between the high level and the low level. SRTS in which the fluctuation of the signal level of the control signal is almost equal to the intermediate signal level between the high level and the low level
The difference can be made equal to the difference between the reproduction voltage control signal and the intermediate value between the high level and the low level, which has the effect of reducing the frequency jitter generated in the reproduction clock when the voltage control signal is switched.

According to the second aspect of the present invention, the signal level comparison means sets the signal level comparison result notification signal high when the signal level of the SRTS reproduction voltage control signal is higher than the adaptive clock reproduction voltage control signal. When the signal level of the SRTS reproduction voltage control signal is lower than the adaptive clock reproduction voltage control signal, the signal level comparison result notification signal is output as a low level, and the reference value control means sets the SRTS clock reproduction in the clock reproduction mode. Mode and the signal level comparison result notification signal is high level at the rising edge of the reproduction clock, the reference value is decreased by 1, and the clock reproduction mode is SRTS clock reproduction mode and the signal level comparison result notification signal is low level at the rising edge of the reproduction clock. , The standard value is increased by 1 and the data By outputting to the level notification signal output unit, the signal level of the adaptive clock reproduction voltage control signal becomes equal to the SRTS reproduction voltage control signal, and the frequency jitter generated in the reproduction clock when the voltage control signal is switched is reduced. Has the effect of

The present invention also provides the S according to the third configuration.
When the clock reproduction mode is the SRTS clock reproduction mode, the RTS reproduction voltage control signal selection output means outputs the SRT.
The S clock recovery voltage control signal is output to the adaptive clock recovery low-pass filter so that the clock recovery mode is SR.
A signal of the voltage control signal when the voltage control signal is switched by making the signal level of the voltage control signal for adaptive clock reproduction at the time of switching from the TS clock reproduction mode to the adaptive clock reproduction mode equal to the voltage control signal for SRTS reproduction Level variation can be equal to 0,
This has the effect of reducing the frequency jitter that occurs in the reproduced clock when the voltage control signal is switched.

[0021]

【Example】

(Embodiment 1) An embodiment of the clock recovery device of the present invention will be described below. FIG. 1 shows the configuration of a first embodiment of a clock recovery device of the present invention. The configuration of the applied clock reproduction control unit 114 is different from the conventional example shown in FIG. In FIG. 1, reference numeral 101 denotes a reception protocol data unit in which a header portion and an information portion are included, fixed speed data is described in the information portion, and synchronization time stamp residual information indicating frequency information of a transmission clock of the fixed speed data is described in the header portion. , 102 is a network clock, 103 is a header pulse indicating the arrival timing of the reception protocol data unit 101, 104 is a reception data storage unit for storing the information part of the reception protocol data unit 101, 105
Reference numeral 106 is a write control unit for controlling data writing to the received data storage unit 104, 106 is an SRTS detection unit for detecting synchronous time stamp residual information from the header portion of the reception protocol data unit 101, and 107 is data for the received data storage unit 104. , 108 is a data storage amount notification signal indicating the data storage amount in the received data storage unit 104, and 109 is measured at the fixed speed data transmission side every N bits of fixed speed data are transmitted. It is a synchronization time stamp residual information notification signal which is the lower 4 bits of the transmission time value.

Reference numeral 110 is a clock reproduction mode switching unit for switching between two modes, SRTS reproduction mode and adaptive clock reproduction mode, according to the amount of data stored in the received data storage unit 104, 111 is a selector which is a voltage control signal switching means, and 112 is A voltage-controlled oscillator, 113 is an SRTS clock recovery control unit that controls the frequency of the output signal of the voltage-controlled oscillator 112 according to the frequency information indicated by the synchronization time stamp residual information, and 114 is a data storage amount of the reception data storage unit 104 that is a reference value. Voltage oscillator 11 to maintain
An adaptive clock reproduction control unit for controlling the output signal 2;
Reference numeral 5 is an SRTS clock reproduction voltage control signal generated in the SRTS clock reproduction control unit 113, 116 is an adaptive clock reproduction voltage control signal generated in the adaptive clock reproduction control unit 114, 117 is a clock reproduction mode notification signal, and 118 is A voltage control signal, 119 is a reproduction clock, 120 is a read control unit for controlling data read from the received data storage unit 104, 121 is a data read signal for reading data from the received data storage unit 104, and 122 is a received data storage unit. It is the fixed speed data read from 104.

Reference numeral 123 is a reception protocol data unit 1
A phase comparison pulse having N bits of fixed speed data stored in the information section 01 as one cycle, 124 is a reference pulse generated every N cycles of the reproduction clock 119, and 125 is a synchronous time stamp residual information notification signal 109. A phase comparison pulse generator that generates a phase comparison pulse 123 using
Reference numeral 12 denotes a reference pulse 12 using the reproduction clock 119.
The frequency dividing circuit 127 generates a phase comparison pulse 12
3 is a phase comparison output signal indicating the phase difference between the reference pulse 124 and 128, and 128 is the phase comparison pulse 123 and the reference pulse 124.
A phase comparator for comparing the phases of 129, 129 is a low-pass filter for SRTS that removes high frequency components of the phase comparison output signal 127, and 130 is data storage indicating that the data storage amount of the reception data storage unit 104 exceeds a reference value. A level notification signal, 131 is a data storage level notification signal output section that outputs a data storage level notification signal 130 using the data storage amount notification signal 108, and 132 is an intermediate value signal equal to the intermediate signal level between high level and low level, Reference numeral 133 denotes an adaptive clock reproduction low-pass filter input signal, and reference numeral 134 denotes an intermediate value signal selection output unit which selects either the data storage level notification signal 130 or the intermediate value signal 132 and outputs it as the adaptive clock reproduction low-pass filter input signal 133. A selector, 135 is a low-pass filter input signal for adaptive clock recovery 33 is a low pass filter for adaptive clock recovery for removing a high frequency component of.

Next, the operation of the first embodiment will be described. FIG. 2 shows a timing chart for explaining the operation.
In FIG. 2, reference numeral 21 denotes a data storage amount notification signal (10
8) and 22 are voltage control signals (118).

In the write control section 105, the information section of the reception protocol data unit 101 is the reception data storage section 10
At the timing of arriving at 4, the write signal 107 is activated and output. The reception data storage unit 104 stores the received reception protocol data unit 101 when the write signal 107 is active and stores the read signal 1
When 21 is active, the stored data is output as the fixed speed data 122 at the speed of the reproduction clock 119. Further, the reception data storage unit 104 outputs the stored data amount as a data storage amount notification signal 108. The SRTS detection unit 106 detects the synchronization time stamp residual information described in the header part of the reception protocol data unit 101, and outputs it as the synchronization time stamp residual information notification signal 109 to the phase comparison pulse generation unit 125. The read control unit 120 activates the data read signal 121 when the data storage amount of the received data storage unit 104 exceeds the reference value for the first time, and the data read signal 121 is kept until the data stored in the received data storage unit 104 is exhausted. To activate.

The clock reproduction mode switching unit 110 is
When the data storage amount indicated by the input data storage amount notification signal 108 is larger than the upper limit value of the data storage amount of the reception data storage unit 104 or smaller than the lower limit value of the data storage amount of the reception data storage unit 104, the clock The clock reproduction mode indicated by the reproduction mode notification signal 117 is an adaptive clock reproduction mode, and when the data storage amount is smaller than the upper limit value and larger than the lower limit value of the data storage amount of the received data storage unit 104, the clock reproduction mode notification signal 117 indicates. The clock reproduction mode is referred to as SRTS clock reproduction mode.

The phase comparison pulse generator 125 restores the time stamp indicating the transmission time for each N bits of the fixed speed data based on the input synchronization time stamp residual information notification signal 109, and the fixed speed data N A pulse is generated at each bit time and output as a phase comparison pulse 123. The frequency dividing circuit 126 receives the input reproduction clock 11
A pulse is generated every N cycles of 9 and is output as a reference pulse 124. The phase comparator 128 compares the phases of the input phase comparison pulse 123 and the reference pulse 124, and the phase of the reference pulse 124 is the phase comparison pulse 12
When it is ahead of the phase of 3, the phase comparison output signal 12
When the phase of the reference pulse 124 is delayed from the phase of the phase comparison pulse 123, the phase comparison output signal 127 is output as a high level. SRT
The S low-pass filter 129 removes the high frequency component of the input phase comparison output signal 127 and outputs it as the SRTS voltage control signal 115.

Data storage level notification signal output unit 131
Compares the input data storage amount notification signal 108 with a reference value, and when the data storage amount exceeds the reference value,
The data storage level notification signal 130 is set to the high level, and when the data storage amount does not exceed the reference value, the data storage level notification signal 130 is output to the low level.
The selector 134 outputs the clock reproduction mode notification signal 117.
When the clock reproduction mode indicated by is the adaptive clock reproduction mode, the data storage level notification signal 130 is selected and output, and when the clock reproduction mode indicated by the clock reproduction mode notification signal 117 is the SRTS clock reproduction mode, the intermediate value signal is output. 132 is selected and output as the low-pass filter input signal 133 for adaptive clock reproduction. When the intermediate value signal 132 is input as the adaptive clock reproducing low-pass filter input signal 133, the adaptive clock reproducing low-pass filter 135 outputs the intermediate value signal 132 as it is as the adaptive clock reproducing voltage control signal 116 to reproduce the adaptive clock. Low pass filter input signal 1
When the data storage level notification signal 130 is input as 33, the high frequency component is removed and output as the adaptive clock reproduction voltage control signal 116.

When the clock reproduction mode is the adaptive clock reproduction mode, the selector 111 selects the adaptive clock reproduction voltage control signal 116 and outputs it as the voltage control signal 118. When the clock reproduction mode is the SRTS clock reproduction mode, the SRTS is selected. The voltage control signal 115 for use is selected and output as the voltage control signal 118.

When the signal level of the input voltage control signal 118 is equal to the intermediate value between the high level and the low level, the voltage control oscillator 112 generates a clock having a center frequency and outputs it as a reproduction clock 119, and the voltage control signal 112 is generated. 11
The frequency of the reproduction clock 119 is increased according to the increase in the signal level with respect to the intermediate value between the high level and the low level of 8 and the decrease in the signal level with respect to the intermediate value between the high level and the low level of the voltage control signal 118 is increased. Thus, the frequency of the reproduction clock 119 is reduced.

As described above, according to the first embodiment,
The adaptive clock reproduction control unit 114 is provided with the selector 134, and when the clock reproduction mode is the SRTS clock reproduction mode, the intermediate value signal 132 is input to the adaptive clock reproduction low-pass filter 135 and output by the adaptive clock reproduction low-pass filter 135. When the signal level of the adaptive clock regeneration voltage control signal 116 is set to an intermediate value between the high level and the low level, the clock regeneration mode becomes SR.
The fluctuation value of the signal level of the voltage control signal 118 at the timing of changing from the TS clock reproduction mode to the adaptive clock reproduction mode becomes equal to the difference between the signal levels of the SRTS voltage control signal 115 and the intermediate value signal 132, and the voltage control oscillator 112 It is possible to reduce frequency jitter generated in the output reproduction clock 119.

(Second Embodiment) Next, a second embodiment of the present invention will be described. FIG. 3 shows the configuration of the second embodiment of the clock recovery device of the present invention. It differs from the conventional example shown in FIG. 7 only in that the number of inputs to the applied clock recovery controller 314 increases. In FIG. 3, reference numeral 301 denotes a reception protocol data unit including a header part and an information part, in which the information part describes fixed speed data, and the header part describes synchronous time stamp residual information indicating frequency information of a transmission clock of the fixed speed data. , 302 is a network clock, 303 is a reception protocol data unit 301
, 304 is a header pulse indicating the arrival timing of the received protocol data unit 301, 305 is a received data storage unit that stores the information section of the received protocol data unit 301, 305 is a write control unit that controls writing of data to the received data storage unit 304, and 306 is a received protocol data unit. SRTS detection unit for detecting synchronization time stamp residual information from the header part of 301, 3
Reference numeral 07 is a data write signal for writing data in the received data storage unit 304, and 308 is the received data storage unit 30.
4, a data storage amount notification signal indicating the data storage amount in 4,
Reference numeral 309 denotes a synchronization time stamp residual information notification signal which is the lower 4 bits of the transmission time value measured every N bits of the fixed speed data transmitted on the fixed speed data transmission side.

Reference numeral 310 denotes a clock reproduction mode switching unit for switching between two modes of the SRTS reproduction mode and the adaptive clock reproduction mode according to the amount of data stored in the received data storage unit 304, 311 a selector which is a voltage control signal switching means, and 312 a The voltage controlled oscillator 313 controls the frequency of the output signal of the voltage controlled oscillator 312 according to the frequency information indicated by the synchronous time stamp residual information, and the SRTS clock recovery controller 314 sets the data storage amount of the received data storage unit 304 to the reference value. Voltage oscillator 31 to maintain
An adaptive clock regeneration control unit for controlling the output signal of 2;
5 is an SRTS clock reproduction voltage control signal generated in the SRTS clock reproduction control unit 313, 316 is an adaptive clock reproduction voltage control signal generated in the adaptive clock reproduction control unit 314, 317 is a clock reproduction mode notification signal, and 318 is A voltage control signal, 319 is a reproduction clock, 320 is a read control unit for controlling data read from the received data storage unit 304, 321 is a data read signal for reading data from the received data storage unit 304, and 322 is a received data storage unit. The fixed speed data read from 304.

323 is a reception protocol data unit 3
A phase comparison pulse having N bits of the fixed speed data stored in the information section 01 as one cycle, 324 is a reference pulse generated every N cycles of the reproduction clock 319, and 325 is a synchronous time stamp residual information notification signal 309. A phase comparison pulse generator that generates a phase comparison pulse 323 using
326 is a reference pulse 72 using the recovered clock 319.
The frequency divider circuit 327 generates a phase comparison pulse 32
3 and the reference pulse 324, the phase comparison output signal 328 indicates the phase difference, and 328 indicates the phase comparison pulse 323 and the reference pulse 324.
A phase comparator for comparing the phases of the three, 329 is a low-pass filter for SRTS that removes high frequency components of the phase comparison output signal 327, and 330 is data storage indicating that the data storage amount of the reception data storage unit 304 exceeds the reference value. A level notification signal, 331 is a data storage level notification signal output section that outputs a data storage level notification signal 330 using the data storage amount notification signal 308, and 332 is a SRTS clock recovery voltage control signal 315 and an adaptive clock recovery voltage control signal. A signal level comparison unit for comparing the signal levels of 316, 3
33 is a signal level comparison result notification signal indicating the magnitude of the signal levels of the SRTS clock reproduction voltage control signal 315 and the adaptive clock reproduction voltage control signal 316, and 334 is the reference value of the data storage amount of the reception data storage unit 304. The data storage amount reference value control unit 335, which controls according to the signal level of the clock reproduction voltage control signal 316 and the SRTS clock reproduction voltage control signal 315, is a reference value signal,
Reference numeral 336 is an adaptive clock low-pass filter that removes high frequency components of the data storage level notification signal 330.

Next, the operation of the second embodiment will be described. FIG. 4 shows a timing chart for explaining the operation.
In FIG. 4, 41 is a data storage amount notification signal (30
8) and 42 are voltage control signals (318).

In the write control unit 305, the information part of the reception protocol data unit 301 is the reception data storage unit 30.
At the timing of arriving at 4, the write signal 307 is activated and output. The reception data storage unit 304 stores the received reception protocol data unit 301 when the write signal 307 is active, and stores the read signal 3
When 21 is active, the stored data is output as fixed speed data 322 at the speed of the reproduction clock 319. Further, the received data storage unit 304 outputs the stored data amount as a data storage amount notification signal 308. The SRTS detection unit 306 detects the synchronization time stamp residual information described in the header portion of the reception protocol data unit 301, and outputs it as the synchronous time stamp residual information notification signal 309 to the phase comparison pulse generation unit 325. The read control unit 320 activates the data read signal 321 when the amount of data stored in the received data storage unit 304 exceeds the reference value for the first time, until the data stored in the received data storage unit 304 is exhausted. To activate.

The clock reproduction mode switching unit 310 is
When the data storage amount indicated by the input data storage amount notification signal 308 is larger than the upper limit value of the data storage amount of the reception data storage unit 304 or smaller than the lower limit value of the data storage amount of the reception data storage unit 304, the clock A clock recovery mode notification signal 317 indicates that the clock recovery mode indicated by the recovery mode notification signal 317 is an adaptive clock recovery mode and the data storage amount is smaller than the upper limit value and larger than the lower limit value of the data storage amount of the received data storage unit 304. The clock reproduction mode is referred to as SRTS clock reproduction mode.

The phase comparison pulse generator 325 restores the time stamp indicating the transmission time for each N bits of the fixed speed data based on the input synchronization time stamp residual information notification signal 309, and the fixed speed data N A pulse is generated at each bit time and output as a phase comparison pulse 323. The frequency dividing circuit 326 receives the input reproduction clock 31.
A pulse is generated every N cycles of 9 and output as a reference pulse 324. The phase comparator 328 compares the phases of the input phase comparison pulse 323 and the reference pulse 324, and the phase of the reference pulse 324 is the phase comparison pulse 32.
3 leads the phase comparison output signal 3
When the phase of the reference pulse 324 is delayed from the phase of the phase comparison pulse 323, the phase comparison output signal 327 is output as a high level. SR
The TS low-pass filter 329 removes the high frequency component of the input phase comparison output signal 327 and outputs it as an SRTS voltage control signal 315.

When the signal level of the SRTS clock recovery voltage control signal 315 is higher than the signal level of the adaptive clock recovery voltage control signal 316, the signal level comparison unit 332 sets the signal level comparison result notification signal 333 to high level, and SRTS. When the signal level of the clock reproduction voltage control signal 315 is lower than the signal level of the adaptive clock reproduction voltage control signal 316, the signal level comparison result notification signal 333 is output as a low level. The data storage amount reference value control unit 334 reduces the reference value of the data storage amount of the received data storage unit 304 by 1 when the signal level comparison result notification signal 333 is at the high level at the rising of the reproduction clock 319, and the reproduction clock 319 When the signal level comparison result notification signal 333 is low level at the rising edge of
The reference value of the data storage amount of the reception data storage unit 304 is increased by 1 and output as the reference value signal 335 to the data storage level notification signal output unit 331. The data storage level notification signal output unit 331 compares the input data storage amount notification signal 308 with the reference value signal 335, and when the data storage amount exceeds the reference value, sets the data storage level notification signal 330 to the high level. When the data storage amount does not exceed the reference value, the data storage level notification signal 3
30 is output as a low level.

When the clock reproduction mode is the adaptive clock reproduction mode, the selector 311 selects the adaptive clock reproduction voltage control signal 316 and outputs it as the voltage control signal 318, and when the clock reproduction mode is the SRTS clock reproduction mode, the SRTS. The voltage control signal 315 for use is selected and output as the voltage control signal 318.

When the signal level of the input voltage control signal 318 is equal to the intermediate value between the high level and the low level, the voltage control oscillator 312 generates a clock having a center frequency and outputs it as a reproduction clock 319, 31
The frequency of the reproduction clock 319 is increased according to the increase in the signal level with respect to the intermediate value between the high level and the low level of 8 and the decrease in the signal level with respect to the intermediate value between the high level and the low level of the voltage control signal 318 is increased. Then, the frequency of the reproduction clock 319 is decreased.

As described above, according to the second embodiment,
A signal level comparison unit 332 and a data storage amount reference value control unit 334 are provided for the adaptive clock reproduction control unit 314, and the signal level of the SRTS clock reproduction voltage control signal 315 is adapted even when the clock reproduction mode is the SRTS clock reproduction mode. When it is larger than the clock recovery voltage control signal 316, the reference value is decreased to increase the signal level of the adaptive clock recovery voltage control signal 316, and the SRT
When the signal level of the S clock recovery voltage control signal 315 is lower than the adaptive clock recovery voltage control signal 316, the reference value is increased to decrease the signal level of the adaptive clock recovery voltage control signal 316, and thereby the clock recovery mode is set. In the SRTS clock reproduction mode, the signal levels of the SRTS reproduction voltage control signal 315 and the adaptive clock reproduction voltage control signal 316 become equal,
Since the fluctuation value of the signal level of the voltage control signal 318 becomes 0 at the timing when the clock reproduction mode changes from the SRTS clock reproduction mode to the adaptive clock reproduction mode, the frequency jitter generated in the reproduction clock 319 output from the voltage oscillator 312 is reduced. be able to.

(Embodiment 3) Next, a third embodiment of the present invention will be described. FIG. 5 shows the configuration of a third embodiment of the clock recovery device of the present invention.
The conventional example shown in FIG. 7 is different from the applied clock reproduction control unit 51.
Only the configuration of 4 is different. In FIG. 5, 501 is composed of a header part and an information part, and the information part has fixed speed data,
A reception protocol data unit in which header information contains synchronous time stamp residual information indicating frequency information of a transmission clock for fixed speed data, 502 is a network clock, and 50 is a network clock.
Reference numeral 3 is a header pulse indicating the arrival timing of the reception protocol data unit 501, 504 is a reception data storage unit that stores the information portion of the reception protocol data unit 501, and 505 is a write control unit that controls data writing to the reception data storage unit 504. Reference numeral 506 denotes an SRTS detection unit that detects synchronous time stamp residual information from the header portion of the reception protocol data unit 501, 507 a data write signal for writing data in the reception data storage unit 504, and 508 in the reception data storage unit 504. A data storage amount notification signal indicating the data storage amount, and 509 is a sync time stamp residual which is the lower 4 bits part of the transmission time value measured every N bits of fixed speed data transmitted on the transmission side of the fixed speed data. This is an information notification signal.

Reference numeral 510 is a clock reproduction mode switching section for switching between two modes, SRTS clock recovery mode and adaptive clock recovery mode, according to the amount of data stored in the received data storage section 504, and 511 is a selector 512 which is a voltage control signal switching means. Is a voltage controlled oscillator, and 513 controls the frequency of the output signal of the voltage controlled oscillator 512 according to the frequency information indicated by the synchronous time stamp residual information.
The RTS clock recovery control unit 514 controls the output signal of the voltage oscillator 512 so that the data storage amount of the received data storage unit 504 maintains the reference value. The adaptive clock recovery control unit 515 generates the SRTS clock recovery control unit 513. SRTS clock recovery voltage control signal, 5
Reference numeral 16 is an adaptive clock reproduction voltage control signal generated in the adaptive clock reproduction control unit 514, 517 is a clock reproduction mode notification signal, 518 is a voltage control signal, 519 is a reproduction clock, 520 is data read from the received data storage unit 504. A read control unit 521 for controlling the data read signal 521 for reading data from the received data storage unit 504 and a fixed speed data 522 read from the received data storage unit 504.

523 is a reception protocol data unit 5
A phase comparison pulse having N bits of fixed speed data stored in the information section 01 as one cycle, 524 is a reference pulse generated every N cycles of the reproduction clock 519, and 525 is a synchronous time stamp residual information notification signal 509. A phase comparison pulse generator that generates a phase comparison pulse 523 using
526 is a reference pulse 52 using the recovered clock 519.
The frequency divider circuit 527 generates a phase comparison pulse 52.
3 is a phase comparison output signal indicating a phase difference between the reference pulse 524 and the reference pulse 524. Reference numeral 528 is a phase comparison pulse 523 and a reference pulse 524.
A phase comparator for comparing the phases of the signals, 529 is a low-pass filter for SRTS that removes high frequency components of the phase comparison output signal 527, and 530 is data storage indicating that the data storage amount of the reception data storage unit 504 exceeds a reference value. A level notification signal, 531 is a data storage level notification signal output section for outputting a data storage level notification signal 530 using the data storage amount notification signal 508, 532 is a low pass filter input signal for adaptive clock reproduction, and 533 is a data storage level notification signal. 530 and SRTS clock recovery voltage control signal 5
A selector 53, which is an SRTS clock reproduction voltage control signal selection output unit, which selects any one of 15 and outputs it as an adaptive clock reproduction low-pass filter input signal 532.
4 is a low-pass filter input signal 53 for adaptive clock reproduction
It is an adaptive clock low pass filter that removes the high frequency component of 2.

Next, the operation of the third embodiment will be described. FIG. 6 shows a timing chart for explaining the operation.
In FIG. 6, 61 is a data storage amount notification signal (50
8) and 62 are voltage control signals (518).

In the write control unit 505, the information part of the reception protocol data unit 501 is the reception data storage unit 50.
At the timing of arriving at 4, the write signal 507 is activated and output. The reception data storage unit 504 stores the received reception protocol data unit 501 when the write signal 507 is active and stores the read signal 5
When 21 is active, the stored data is output as fixed speed data 522 at the speed of the reproduction clock 519. Further, the reception data storage unit 504 outputs the stored data amount as a data storage amount notification signal 508. The SRTS detection unit 506 detects the synchronization time stamp residual information described in the header part of the reception protocol data unit 501, and outputs it to the phase comparison pulse generation unit 525 as a synchronization time stamp residual information notification signal 509. The read control unit 520 activates the data read signal 521 when the amount of data stored in the received data storage unit 504 exceeds the reference value for the first time, until the data stored in the received data storage unit 504 is exhausted. To activate.

The clock reproduction mode switching unit 510 is
When the data storage amount indicated by the input data storage amount notification signal 508 is larger than the upper limit value of the data storage amount of the reception data storage unit 504 or smaller than the lower limit value of the data storage amount of the reception data storage unit 504, the clock The clock recovery mode notification signal 517 indicates that the clock recovery mode indicated by the recovery mode notification signal 517 is an adaptive clock recovery mode and the data storage amount is smaller than the upper limit value and larger than the lower limit value of the data storage amount of the received data storage unit 504. The clock reproduction mode is referred to as SRTS clock reproduction mode.

The phase comparison pulse generator 525 restores the time stamp indicating the transmission time for every N bits of the fixed speed data based on the input synchronization time stamp residual information notification signal 509, and the fixed speed data N A pulse is generated at each bit time and output as a phase comparison pulse 523. The frequency divider circuit 526 uses the input reproduction clock 51.
A pulse is generated every N cycles of 9 and output as a reference pulse 524. The phase comparator 528 compares the phases of the input phase comparison pulse 523 and the reference pulse 524, and the phase of the reference pulse 524 is the phase comparison pulse 52.
When it is ahead of the phase of 3, the phase comparison output signal 5
When the phase of the reference pulse 524 is delayed from the phase of the phase comparison pulse 523, the phase comparison output signal 527 is output as a high level. SR
The TS low-pass filter 529 removes the high frequency component of the input phase comparison output signal 527 and outputs it as a SRTS voltage control signal 515.

Data storage level notification signal output section 531
Compares the input data storage amount notification signal 508 with a reference value, and when the data storage amount exceeds the reference value, sets the data storage level notification signal 530 to a high level and the data storage amount exceeds the reference value. If not, the data storage level notification signal 530 is output as a low level. The selector 533 selects the data storage level notification signal 530 when the clock reproduction mode indicated by the clock reproduction mode notification signal 517 is the adaptive clock reproduction mode, and the clock reproduction mode indicated by the clock reproduction mode notification signal 517 is the SRTS clock reproduction mode. , The SRTS clock recovery voltage control signal 515 is selected, and the adaptive clock recovery low-pass filter input signal 5 is selected.
Output as 32. When the SRTS clock reproduction voltage control signal 515 is input as the adaptive clock reproduction low-pass filter input signal 532, the adaptive clock reproduction low-pass filter 534 retains the SRTS clock reproduction voltage control signal 515 as it is. When the data storage level notification signal 530 is output as the adaptive clock reproduction low-pass filter input signal 532, the high frequency component is removed and the adaptive clock reproduction voltage control signal 516 is output.

When the clock reproduction mode is the adaptive clock reproduction mode, the selector 511 selects the adaptive clock reproduction voltage control signal 516 and outputs it as the voltage control signal 518. When the clock reproduction mode is the SRTS clock reproduction mode, the SRTS is selected. The voltage control signal 515 for use is selected and output as the voltage control signal 518.

When the signal level of the input voltage control signal 518 is equal to the intermediate value between the high level and the low level, the voltage control oscillator 512 generates a clock having a center frequency and outputs it as a reproduction clock 519, and the voltage control signal 512 is generated. 51
The frequency of the reproduction clock 519 is increased according to the increase of the signal level with respect to the intermediate value between the high level and the low level of 8 and the decrease of the signal level with respect to the intermediate value between the high level and the low level of the voltage control signal 518 is increased. Then, the frequency of the reproduction clock 519 is decreased.

As described above, according to the third embodiment,
A selector 533 is provided in the adaptive clock reproduction control unit 514, and when the clock reproduction mode is the SRTS clock reproduction mode, the SRTS clock reproduction voltage control signal 515 is input to the adaptive clock reproduction low-pass filter 534 to input the adaptive clock reproduction low-pass filter. By making the signal level of the adaptive clock recovery voltage control signal 516 output by 534 equal to the SRTS clock recovery voltage control signal 515, the voltage control signal at the timing when the clock recovery mode changes from the SRTS clock recovery mode to the adaptive clock recovery mode. Since the fluctuation value of the signal level of 518 becomes 0, it is possible to reduce the frequency jitter generated in the reproduction clock 519 output from the voltage oscillator 512.

[0054]

As is apparent from the first embodiment of the present invention, when the clock reproduction mode is the SRTS clock reproduction mode, the intermediate value signal is input to the adaptive clock reproduction low-pass filter to reproduce the adaptive clock. Voltage control signal at the timing when the clock reproduction mode is changed from the SRTS clock reproduction mode to the adaptive clock reproduction mode by changing the signal level of the adaptive clock reproduction voltage control signal output from the low-pass filter for use between the high level and the low level. The fluctuation value of the signal level of SRTS
It becomes equal to the difference between the signal levels of the reproduction voltage control signal and the intermediate value signal, and has the effect of reducing the frequency jitter generated in the reproduction clock output from the voltage controlled oscillator.

As is apparent from the second embodiment, the present invention is such that, when the clock reproduction mode is the SRTS clock reproduction mode, the signal level of the SRTS reproduction voltage control signal is higher than that of the adaptive clock reproduction voltage control signal. When it is larger, the reference value is decreased to increase the signal level of the adaptive clock reproduction voltage control signal, and when the signal level of the SRTS reproduction voltage control signal is smaller than the adaptive clock reproduction voltage control signal, the reference value is increased. By reducing the signal level of the adaptive clock recovery voltage control signal, the signal levels of the SRTS clock recovery voltage control signal and the adaptive clock recovery voltage control signal when the clock recovery mode is the SRTS clock recovery mode become equal, Playback mode is adapted from SRTS clock playback mode Since the variation of the signal level of the voltage control signal in the timing of change to lock reproduction mode is 0, has the effect of reducing the frequency jitter of the reproduction clock by the voltage-controlled oscillator outputs.

As is apparent from the third embodiment of the present invention, the SRTS reproduction voltage control signal selection output means outputs the SRTS clock reproduction voltage control signal when the clock reproduction mode is the SRTS clock reproduction mode. Outputting to the low-pass filter for adaptive clock reproduction, and making the signal level of the voltage control signal for adaptive clock reproduction equal to the voltage control signal for SRTS reproduction when the clock reproduction mode is switched from the SRTS clock reproduction mode to the adaptive clock reproduction mode. This makes it possible to equalize the fluctuation of the signal level of the voltage control signal when the selector switches the voltage control signal to 0, and to reduce the frequency jitter generated in the reproduction clock when the voltage control signal is switched. Have.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a clock recovery device according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the device.

FIG. 3 is a block diagram showing a schematic configuration of a clock recovery device according to a second embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation of the device.

FIG. 5 is a block diagram showing a schematic configuration of a clock recovery device according to a third embodiment of the present invention.

FIG. 6 is a timing chart for explaining the operation of the device.

FIG. 7 is a block diagram showing a schematic configuration of a conventional clock recovery device.

FIG. 8 is a timing chart for explaining the operation of the device.

[Explanation of symbols]

101, 301, 501 reception protocol data unit 102, 302, 502 network clock 103, 303, 503 header pulse 104, 304, 504 reception data storage unit 105, 305, 505 write control unit 106, 306, 506 SRTS detection unit 107, 307, 507 Data write signal 108, 308, 508 Data storage amount notification signal 109, 309, 509 Synchronous time stamp residual information notification signal 110, 310, 510 Clock reproduction mode switching unit 111, 311, 511 Selector (voltage control signal switching) Means) 112, 312, 512 Voltage controlled oscillator 113, 313, 513 SRTS clock recovery control section 114, 314, 514 Adaptive clock recovery control section 115, 315, 515 SRTS voltage control signal 1 6, 316, 516 Adaptive clock reproduction voltage control signal 117, 317, 517 Clock reproduction mode notification signal 118, 318, 518 Voltage control signal 119, 319, 519 Reproduction clock 120, 320, 520 Read control unit 121, 321, 521 Data read signal 122, 322, 522 fixed speed data 123, 323, 523 phase comparison pulse 124, 324, 524 reference pulse 125, 325, 525 phase comparison pulse generator 126, 326, 526 frequency divider 127, 327 527 Phase comparison output signal 128, 328, 528 Phase comparator 129, 329, 529 SRTS low-pass filter 130, 330, 530 Data storage level notification signal 131, 331, 531 Data storage level notification signal output unit 132 Intermediate value signal 133, 532 Adaptive clock reproduction low-pass filter input signal 134 Selector (intermediate value signal selection output unit) 135, 336, 534 Adaptive clock reproduction low-pass filter 332 Signal level comparison unit 333 Signal level comparison result notification signal 334 Data storage Quantity reference value control unit 335 Reference value signal 533 Selector (SRTS clock reproduction voltage control signal selection output unit)

Claims (3)

[Claims] 1. A reproduction clock having a center frequency is output when an input voltage control signal is equal to an intermediate voltage value between a high level and a low level, and the voltage control signal is increased with respect to an intermediate voltage value between the high level and a low level. Frequency control oscillator that increases or decreases the frequency of the recovered clock output according to the amount of decrease or decrease, the header part and the information part, and the frequency information of the transmission clock of the fixed speed data in the information part and the fixed speed data in the header part. The received data storage means for receiving the protocol data unit in which the time stamp residual is described, storing only the information part of the protocol data unit and outputting the data at the speed of the reproduction clock, and the frequency indicated by the time stamp residual. Generating a SRTS clock recovery voltage control signal for controlling the frequency of the recovery clock according to the information SR output to the voltage controlled oscillator
TS clock reproduction control means and data storage level quantity notification that outputs a data storage level quantity notification signal that becomes high level when the data storage quantity of the received data storage means exceeds a reference value and low level when it does not exceed the reference value A signal generating means, an adaptive clock reproducing low-pass filter for removing a high frequency component of the data storage level notification signal and outputting it as an adaptive clock reproducing voltage control signal, and the data storage amount of the received data storing means has an upper limit value. If it exceeds or falls below, the adaptive clock recovery voltage control signal is selected and output, and if the data storage amount is between the upper limit value and the lower limit value, S
In a clock regeneration device having a voltage control signal switching means for selecting and outputting a voltage control signal for RTS clock regeneration, if the data storage amount of the reception data storage means is between the upper limit value and the lower limit value, a high level is set. When the intermediate value signal equal to the intermediate signal level between the low level and the low level is selected and output, and the data storage amount of the reception data storage means exceeds the upper limit value or falls below the lower limit value, a data storage amount notification signal is output. A clock regenerator having an intermediate value signal selection and output means for selecting and outputting. 2. An SR instead of the intermediate value signal selecting and outputting means
The signal levels of the TS clock recovery voltage control signal and the adaptive clock recovery voltage control signal are compared, and the SRTS clock recovery voltage control signal is at a high level when the signal level is higher, and the adaptive clock recovery voltage control signal is at a higher level. When the signal level comparison means outputs a signal level comparison result notification signal which becomes a low level when the signal level is high, and a signal level comparison result notification when the data storage amount of the reception data storage means is between the upper limit value and the lower limit value. When the signal is at the high level, the reference value is decreased, and when the signal level comparison result notification signal is at the low level, the reference value is increased, and the data storage amount reference value control means is respectively output to the data storage level notification signal generating means. The clock recovery device according to claim 1, further comprising: 3. In place of the intermediate value signal selection and output means, when the data storage amount of the reception data storage means is between the upper limit value and the lower limit value, the SRTS clock recovery voltage control signal is selected and output. When the data storage amount of the received data storage means exceeds the upper limit value or falls below the lower limit value, the SRTS clock recovery voltage control signal selection output means for selecting and outputting the data storage level amount notification signal is provided. The clock reproduction device according to claim 1.