JPS5939191A - Control signal distributing system - Google Patents

Control signal distributing system

Info

Publication number
JPS5939191A
JPS5939191A JP14892182A JP14892182A JPS5939191A JP S5939191 A JPS5939191 A JP S5939191A JP 14892182 A JP14892182 A JP 14892182A JP 14892182 A JP14892182 A JP 14892182A JP S5939191 A JPS5939191 A JP S5939191A
Authority
JP
Japan
Prior art keywords
memory
control information
identification code
line control
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14892182A
Other languages
Japanese (ja)
Inventor
Shoji Nojiri
野尻 昭二
Hiroki Katano
加田野 博喜
Tetsuaki Sumida
哲明 隅田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP14892182A priority Critical patent/JPS5939191A/en
Publication of JPS5939191A publication Critical patent/JPS5939191A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04QSELECTING
    • H04Q11/00Selecting arrangements for multiplex systems
    • H04Q11/04Selecting arrangements for multiplex systems for time-division multiplexing

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)

Abstract

PURPOSE:To simplify a digital exchange and to transmit control information at a high speed, by adding an identification code to voice and line control information and selecting either the voice information or the line control information read out from a control memory based on the identification code. CONSTITUTION:The line control information (d) transmitted from the central controller CC to each subscriber circuit LC is stored in a prescribed address L of a control memory CM. Each address of the memory CM is provided with an area storing the identification code (i) in addition to the areas storing the readout address of a channel memory SPM and the information (d). Further, a selecting circuit SEL3 is provided between the memory SPM and a selecting circuit SEL2, and the circuit SEL3 is controlled with the identification code (i) read out together with the read-out address and the information (d) from the memory CM. Then, the voice information read-out from the memory SPM and the line control information read-out from the memory CM are selected with the identification codes (d), (i), allowing to transmit the control information at high speed without reducing the allocated line.

Description

【発明の詳細な説明】 ta)  発明の技術分野 本発明は制御信号分配方式、特に通話路メモリと制御メ
モリとを有する1段時分割スイッチから回線対応部に、
ディジタル化された音声情報と回線制御情報とを時分割
多重通話路を介して伝送するディジタル交換機におりる
制御信号分配方式に関す。
DETAILED DESCRIPTION OF THE INVENTION ta) Technical Field of the Invention The present invention relates to a control signal distribution system, in particular, a method for distributing control signals from a one-stage time division switch having a channel memory and a control memory to a line corresponding section.
This invention relates to a control signal distribution system in a digital exchange that transmits digitized voice information and line control information via a time division multiplex communication path.

lb)  従来技術と問題点 第1図は、この種ディジタル交換機における従来ある制
御信号分配方式の一例を示す図である。
lb) Prior Art and Problems FIG. 1 is a diagram showing an example of a conventional control signal distribution system in this type of digital exchange.

第1図において、1段時分割スイッチT S Wは、回
線対応部として収容される加入者回路L Cから、多重
化回路MPXを介して到来するデフfジタル化された音
声情報を、針数回路CN Tから供給される書込アドレ
スに従い通話路メモリSPMに順次格納し、制御メモリ
CMから供給される続出アドレスに従い通話路メモリS
PMから続出し、選択回路5EL2、時分割多重通話路
HWおよび多重分離回路DMPXを介して対応する加入
者回路LCに送出する。また制御信号保持メモリSSM
は、中央制御装置CCから伝達される回線制御情報dを
一旦M積した後、選択回路SEL 2、時分割多重通話
路HWおよび多重分離回路DMPXを介して前記加入者
回路LCとは独立に設けられた(B号分配装置SDに送
出すや。該信号分配装置SDは、受信した回線制御情報
dを総ての加入者回路LCの回線制御情報レジスタRE
Gに分配する。なお前記信号分配装置SDO数は、収容
加入者回路数を圧迫せぬ為に通品1乃至数個に限定され
、総ての加入者回路LCにより時分割使用される。従っ
て信号分配装置SDにより伝達可能な回線制御情報dの
伝送速度には限度がある。第2図は従来ある制御信号分
配方式の他の一例を示す図である。
In FIG. 1, a one-stage time-division switch TSW divides the differential f-digitized voice information that arrives via a multiplexing circuit MPX from a subscriber circuit LC accommodated as a line corresponding section into a number of hands. The circuit CNT sequentially stores the write address in the communication path memory SPM according to the write address supplied from the control memory CM, and stores the communication path memory S in accordance with the successive addresses supplied from the control memory CM.
The signal is output from the PM and sent to the corresponding subscriber circuit LC via the selection circuit 5EL2, the time division multiplexing path HW and the demultiplexing circuit DMPX. Also, control signal holding memory SSM
is provided independently of the subscriber circuit LC via a selection circuit SEL 2, a time division multiplexing channel HW, and a demultiplexing circuit DMPX after once multiplying the line control information d transmitted from the central control unit CC. The signal distribution device SD sends the received line control information d to the line control information register RE of all subscriber circuits LC.
Distribute to G. The number of signal distribution devices SDO is limited to one to a few in order not to overwhelm the number of accommodated subscriber circuits, and is used by all subscriber circuits LC in a time-sharing manner. Therefore, there is a limit to the transmission speed of the line control information d that can be transmitted by the signal distribution device SD. FIG. 2 is a diagram showing another example of a conventional control signal distribution system.

第2図においては、前記限度以上に高速の回線制御情報
dを多重分離回路DMPXのアドレスしに収容される特
殊加入者回路SLCに伝達する為に、多重化回路MPX
の所定アドレスKに収容される加入者回路LCO代りに
高速信号分配装置HS Dを収容し、中央制御装置CC
から伝達される音声情報と同一の伝送速度を有する高速
の回線制御情報dを通話路メモリSPMの所定アドレス
Kに格納し、制御メモリCMの所定アドレスLに中央制
御装置CCにより格納される続出アドレスKにより指定
される、多重分離回路DMPXの所定アドレスLに収容
される特殊加入者回1iSLCに伝送することが出来る
In FIG. 2, in order to transmit line control information d faster than the above-mentioned limit to the special subscriber circuit SLC accommodated in the address of the multiplexer/demultiplexer circuit DMPX, the multiplexer circuit MPX
A high-speed signal distribution device HSD is accommodated in place of the subscriber circuit LCO accommodated at a predetermined address K of the central control device CC.
high-speed line control information d having the same transmission speed as the voice information transmitted from the communication channel memory SPM is stored at a predetermined address K of the communication path memory SPM, and a subsequent address is stored by the central controller CC at a predetermined address L of the control memory CM. It can be transmitted to the special subscriber circuit 1iSLC designated by K and accommodated at a predetermined address L of the demultiplexer circuit DMPX.

以上の説明から明らかな如く、従来ある制御信号分配方
式においては、制御信号保持メモリSSMおよび信号分
配装置SDを介して総ての加入者回路LCに回線制御情
報dを時分割伝送Jる場合には伝送速度に限度が有り、
該限度を越える高速の回線制御情報dを伝送する為には
、専用の高速信号分配装置H3Dを所要数加入者回路1
.cの代りに収容する必要が有り、当該ディジタル交換
機の経済性を損なうと共に、収容加入者回路数を減少せ
しめる欠点が有った。
As is clear from the above explanation, in the conventional control signal distribution system, when the line control information d is time-divisionally transmitted to all subscriber circuits LC via the control signal holding memory SSM and the signal distribution device SD, has a limit on transmission speed,
In order to transmit high-speed line control information d that exceeds this limit, a dedicated high-speed signal distribution device H3D is connected to the required number of subscriber circuits 1.
.. It is necessary to accommodate the subscriber circuits in place of C, which has the disadvantage of impairing the economic efficiency of the digital exchange and reducing the number of accommodated subscriber circuits.

(C1発明の目的 本発明の目的は、前述の如き従来ある制御信号分配方式
の欠点を除去し、当該ディジタル交換機の経済性を損な
うこと無く、また収容回線数を減少せしめること無く、
高速の回線制御情+lを伝達可能な制御信号分配方式を
実現することに在る。
(C1 Purpose of the Invention The purpose of the present invention is to eliminate the drawbacks of the conventional control signal distribution system as described above, without impairing the economic efficiency of the digital exchange, and without reducing the number of accommodated lines.
The object of the present invention is to realize a control signal distribution system capable of transmitting high-speed line control information.

(d)  発明の構成 この目的は、通話路メモリと制御メモリとを有する1段
時分割スイッチから回線対応部に、ディジタル化された
音声情報と回線制御情報とを時分割多重通話路を介して
伝送するディジタル交換機において、前記通話路メモリ
の続出アドレスであることを示す識別符号を付加した前
記続出アドレスと、回線制御情報であることを示す識別
符号を付加した前記回線制御情報とを前記制御メモリの
所定領域に格納し、前記制御メモリから読出される前記
読出ア]・レスに基づき前記通話路メモリから読出され
る音声情報と、前記制御メモリから読出される回線制御
情報との何れかを、前記識別符号に基づき選択し、前記
時分割多重通話路に送出する選択回路を設けることによ
り達成される。
(d) Structure of the Invention This object is to transfer digitized voice information and line control information from a one-stage time division switch having a communication path memory and a control memory to a line corresponding section via a time division multiplex communication path. In the transmitting digital exchange, the following address to which an identification code indicating that the address is a subsequent address in the communication path memory is added, and the line control information to which an identification code indicating that it is line control information is added are stored in the control memory. either the voice information read from the call path memory based on the read response stored in a predetermined area of the control memory or the line control information read from the control memory; This is achieved by providing a selection circuit that selects based on the identification code and sends it to the time division multiplex channel.

(el  発明の実施例 以下、本発明の一実施例を図面により説明する。(el Embodiments of the invention An embodiment of the present invention will be described below with reference to the drawings.

第3図は本発明の一実施例による制御信号分配方式を示
す図である。なお、全図を通じて同一符号は同一対象物
を示す。第3図においては、中央制御装置CCから各加
入者回路LCに伝達される高速の回線制御情報dは、制
御メモリCMの所定アドレスLに格納される。該制御メ
モリCMの各アドレスには、通話路メモリSPMの続出
アドレスおよび前記高速の回線制御情報d自体を格納す
る領域以外に、1ビツトの識別符号iを格納する領域が
設けられている。中央制御装置CGは、前記続出アドレ
スを制御メモリCMに格納する場合には、続出アドレス
であることを示す識別符号i (例えば論理値0)を付
加し、また高速の回線制御情報dを制御メモリCMに格
納する場合には、高速の回線制御情報dであることを示
す識別符号i(例えば論理値l)を付加する。また通話
路メモIJSPMと選択回路5EL2との間には、選択
回路5EL3が設けられている。該選択回路5EL3は
、制御メモリCMから読出アドレスおよび高速の回線制
御情報dと共に読出される識別符号iにより制御され、
論理値0の識別符号iが読出された場合には、同時に読
出された読出アドレスに基づき、話路メモリSPMから
読出される音声情報を選択して選択回路5EL2に伝達
し、論理値lの識別符号iが読出された場合には、同時
に読出された高速の回線制御情報dを選択して選択回路
5EL2に伝達する。選択回路5EL2に伝達された高
速の回線制御情報dは、時分割多重通話路HWを介して
、多重分離回路DMPXの所定アドレスLに収容される
特殊加入者回路SLCに伝達される。
FIG. 3 is a diagram showing a control signal distribution system according to an embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures. In FIG. 3, high-speed line control information d transmitted from the central controller CC to each subscriber circuit LC is stored at a predetermined address L of the control memory CM. Each address of the control memory CM is provided with an area for storing a 1-bit identification code i, in addition to an area for storing the next address of the communication path memory SPM and the high-speed line control information d itself. When storing the successive address in the control memory CM, the central control unit CG adds an identification code i (for example, logical value 0) indicating that it is a successive address, and also stores the high-speed line control information d in the control memory CM. When storing it in the CM, an identification code i (for example, a logical value l) indicating that it is high-speed line control information d is added. Further, a selection circuit 5EL3 is provided between the call path memo IJSPM and the selection circuit 5EL2. The selection circuit 5EL3 is controlled by an identification code i read out from the control memory CM together with a read address and high-speed line control information d,
When the identification code i with the logical value 0 is read out, based on the read address read out at the same time, audio information read out from the speech path memory SPM is selected and transmitted to the selection circuit 5EL2, and the identification code with the logical value l is selected. When the code i is read out, the high speed line control information d read out at the same time is selected and transmitted to the selection circuit 5EL2. The high-speed line control information d transmitted to the selection circuit 5EL2 is transmitted to the special subscriber circuit SLC accommodated at a predetermined address L of the demultiplexing circuit DMPX via the time division multiplexing channel HW.

以上の説明から明Iらかな如く、本実施例によれば、高
速の回線制御情報dは中央制御装置CCにより識別符号
i’(論理値1)を付加された後、制御メモリCMの所
定アドレスLに格納され、選択回路5EL3を介して、
音声情報と同様に時分割多重通話路HWを介して、対応
する特殊加入者回路SLCに伝達される。従って音声情
報と同一の高速の回線制御情報dが伝送可能となり、然
も第2図におけるが、如く、所要数の高速信号分配装置
HS Dを多重化回路MPXに収容する必要が無くなる
As is clear from the above description, according to this embodiment, the high-speed line control information d is added with an identification code i' (logical value 1) by the central controller CC, and then addressed to a predetermined address in the control memory CM. stored in L and via the selection circuit 5EL3,
Like the voice information, it is transmitted to the corresponding special subscriber circuit SLC via the time-division multiplexing channel HW. Therefore, the same high-speed line control information d as the voice information can be transmitted, and there is no need to accommodate the required number of high-speed signal distribution devices HSD in the multiplexing circuit MPX, as shown in FIG.

なお、第3図はあく迄本発明の一実施例に過ぎず、例え
ば回線対応部は加入者回路LCに限定されることは無く
、トランク回路等信に幾多の変形が考慮されるが、何れ
の場合にも本発明の効果は変らない。また1段時分割ス
イッチT S Wおよび加入者回路LCの構成は図示さ
れるものに限定されることは無く、他に幾多の変形が考
慮されるが、何れの場合にも本発明の効果は変らない。
Note that FIG. 3 is only one embodiment of the present invention, and for example, the line corresponding section is not limited to the subscriber circuit LC, and many modifications to the trunk circuit etc. may be considered, but any Even in this case, the effects of the present invention remain the same. Furthermore, the configurations of the one-stage time division switch TSW and the subscriber circuit LC are not limited to those shown in the drawings, and many other modifications may be considered, but the effects of the present invention will not be affected in any case. It doesn't change.

(f)  発明の効果 以上、本発明によれば、前記ディジタル交換機において
、経済性を損なうこと無く、また収容回線数を減少せし
めること無く、高速の回線制御情報を伝達可能な制御信
号分配方式を実現゛→ることが出来る。
(f) Effects of the Invention According to the present invention, a control signal distribution method is provided in the digital exchange that can transmit high-speed line control information without impairing economic efficiency or reducing the number of accommodated lines. It can be realized.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来ある制御信号分配方式の一例を示す図、第
2図は従来ある制御信号分配方式の他の一例を示す図、
第3図は本発明の一実施例による制御信号分配方式を示
す図である。 図において、′r s wは1段時分割スイッチ、LC
は加入者回路、SLCは特殊加入者回路、MPXは多重
化回路、DMPXは多重分離回路、S ))Mは通話路
メモリ、CMは制御メモリ、SSMは制御信号保持メモ
リ、CNTは計数回路、5EL1.5EL2および5E
L3は選択回路、REGは回線制御情報レジスタ、SD
は信号分配装置、[I S Dは高速信号分配装置、C
Cは中央制御装置、dば回線制御情報、iは識別符号、
KおよびLはアドレス、を示す。 CC ヤ I 図 5W CC/ 第 2 図 SW 第 3 図
FIG. 1 is a diagram showing an example of a conventional control signal distribution method, FIG. 2 is a diagram showing another example of a conventional control signal distribution method,
FIG. 3 is a diagram showing a control signal distribution system according to an embodiment of the present invention. In the figure, 'r s w is a one-stage time division switch, LC
is a subscriber circuit, SLC is a special subscriber circuit, MPX is a multiplexing circuit, DMPX is a demultiplexing circuit, S)) M is a channel memory, CM is a control memory, SSM is a control signal holding memory, CNT is a counting circuit, 5EL1.5EL2 and 5E
L3 is a selection circuit, REG is a line control information register, SD
is a signal distribution device, [ISD is a high-speed signal distribution device, C
C is the central control unit, d is the line control information, i is the identification code,
K and L indicate addresses. CC Ya I Figure 5W CC/ Figure 2 SW Figure 3

Claims (1)

【特許請求の範囲】[Claims] 通話路メモリと制御メモリとを有する1段時分割スイッ
チから回線対応部に、ディジタル化された音声情報と回
線制御情報とを時分割多重通話路を介し゛ζ伝送するデ
ィジタル交換機において、前記通話路メモリの続出アド
レスであることを示す識別符号を付加した前記続出アド
レスと、回線制御情報であることを示す識別符号を付加
した前記回線制御情報とを前記制御メモリの所定領域に
格納し、前記制御メモリから読出される前記続出アドレ
スに基づき前記通話路メモリから読出される音声情報と
、前記制御メモリから読出される回線制御情報との何れ
かを、前記識別符号に基づき選択し、前記時分割多重通
話路に送出する選択回路を設けることを特徴とする信号
分配方式。
In a digital exchange that transmits digitized voice information and line control information from a one-stage time division switch having a communication path memory and a control memory to a line corresponding section via a time division multiplex communication path, the communication path The successive address to which an identification code indicating that it is a successive address of the memory is added, and the line control information to which an identification code indicating that it is line control information are added are stored in a predetermined area of the control memory, Based on the successive address read from memory, either the voice information read from the communication path memory or the line control information read from the control memory is selected based on the identification code, and the time division multiplexing is performed. A signal distribution system characterized by providing a selection circuit for sending out signals to a communication path.
JP14892182A 1982-08-27 1982-08-27 Control signal distributing system Pending JPS5939191A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14892182A JPS5939191A (en) 1982-08-27 1982-08-27 Control signal distributing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14892182A JPS5939191A (en) 1982-08-27 1982-08-27 Control signal distributing system

Publications (1)

Publication Number Publication Date
JPS5939191A true JPS5939191A (en) 1984-03-03

Family

ID=15463633

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14892182A Pending JPS5939191A (en) 1982-08-27 1982-08-27 Control signal distributing system

Country Status (1)

Country Link
JP (1) JPS5939191A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0483458A2 (en) * 1990-10-29 1992-05-06 Dsc Communications Corporation Power reduction technique for a time slot interchanger in the subscriber interface
JPH05168073A (en) * 1991-12-19 1993-07-02 Mitsubishi Electric Corp Device for inserting and extracting common line signal

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0483458A2 (en) * 1990-10-29 1992-05-06 Dsc Communications Corporation Power reduction technique for a time slot interchanger in the subscriber interface
JPH05168073A (en) * 1991-12-19 1993-07-02 Mitsubishi Electric Corp Device for inserting and extracting common line signal

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