JPS636184B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a time division multi-directional multiplex communication system configured by one master station and a plurality of slave stations. especially,
The present invention relates to a signal transmission/reception circuit of a master station that enables signal transmission between arbitrary master stations or slave stations.

FIG. 1 is a diagram showing a configuration and signal arrangement of an example of a time division multiplex communication system to which the present invention is applied. In this method, a time-division multiplexed signal S _C is sent out simultaneously in multiple directions from the master station to each slave station, and each slave station synchronizes with the signal _SC sent from the master station. , by reproducing the timing signal, the signals A, B, . . . assigned to the local station are obtained from the signal S _C.
...or take out N. In addition, each slave station has a time allocated to each slave station based on the above timing signal.
Send only SF _A , SF _B , ... or SF _N signals,
The master station controls the signals A, _B , . F in Figure 1 is 1 frame, SF _A ~
_N is a subframe and indicates the time allocated to each slave station within one frame. The above-mentioned subframes may be allocated to two or more locations within one frame.

FIG. 2 is a block diagram showing an example of a signal transmitting/receiving circuit used in a conventional master station. This is a diagram showing a circuit for converting a signal input to a master station into the frame structure of the system of FIG. 1 to be sent to each slave station using the method of FIG. 1. FIG. 3 is a diagram showing an example of input/output signals of the circuit shown in FIG. 2. The horizontal axis t is the time axis.

In FIG. 2, the input signal 1 of the memory circuit 101 is the first
To be sent to each slave station via the system shown in the figure,
This is a signal input to the master station, and an example of this signal is the third
As shown in Figure a. A, B,...N in the diagram
indicates the destination slave station of each channel's signal.

The storage circuit 101 temporarily stores the input signal 1 in units of one frame, and stores the input signal 1 in units of one frame, and stores the signal shown in FIG.
(equivalent to S _C )
This is a circuit that rearranges signals in channel units and outputs it as output signal 2. Memory circuit 103
is a circuit that rearranges signals in the opposite manner to that of the storage circuit 101. Input signal 4 is a signal sent from each slave station to the master station (Fig. 3b), which is temporarily stored in the storage circuit 103 in units of one frame, converted to the signal shown in Fig. 3a, and output signal. Output as 6. Control circuit 102 outputs control signals 3 and 5 that control write and read timing of signals in memory circuits 101 and 103.

In the conventional system configured as described above, the master station and the slave stations can communicate directly, but signals are transmitted between the slave stations by the following method. That is, the time-division signals sent from each slave station are sent to the PCM terminal device via the circuit shown in FIG. 2, where they are separated into PCM signals for each channel by a multiplexing/demultiplexing circuit. After this is converted into an analog signal by a DA conversion circuit, it is connected to an exchange. The output of the exchange is sent again to the PCM terminal equipment, where it is again converted into a digital signal by the AD conversion circuit, time-division multiplexed by the time-division multiplexing circuit, and then sent again to the master station shown in Figure 1. is input and sent to the target slave station.

In this way, in the conventional method, in order to transmit signals between slave stations, it is necessary to go through other equipment such as PCM terminal equipment, and in the process of signal transmission between slave stations, each DA and AD Because the conversion takes place,
There were drawbacks such as signal deterioration due to quantization noise and the like.

The present invention solves the above-mentioned drawbacks, and provides a time-division multidirectional multiplex communication system that enables signal transmission between arbitrary master stations or slave stations without going through other devices, and that causes less signal deterioration. With the goal.

The present invention includes a first storage circuit in a master station that temporarily stores signals to be transmitted from the master station to slave stations, and a first storage circuit that temporarily stores signals received from each slave station and transferred to other slave stations via the master station. a second memory circuit for storing, a third memory circuit for temporarily storing signals received from each slave station and output from the master station and outputting as a master station output signal, and a third memory circuit for temporarily storing signals received from each slave station and output from the master station; a control circuit to control;
a time division multiplexing circuit for time division multiplexing the readout output of the first storage circuit and the readout output of the second storage circuit; It is characterized by including means for controlling readout of the first and second storage circuits at the timing when a signal of the same destination as the destination enters from the second storage circuit into the same subframe destined for the same destination slave station. shall be.

Next, it will be explained in more detail using the drawings of the embodiment.

FIG. 4 is a block diagram showing an embodiment of the master station signal transmitting/receiving circuit according to the present invention. 10 in Figure 4
1, 103, and 104 are storage circuits that temporarily store the input signals 1 and 4 in units of one frame, and rearrange the signals on the time axis in units of channels. 102 is a control circuit, and a memory circuit 10
Control signals 3, 5 and 7 for controlling write and read timings of 1, 103 and 104 are output. Time division multiplexing circuit 105 time division multiplexes output signals 2 and 8 of storage circuits 101 and 104, and outputs signal 9 to be sent to each slave station. Here, blocks or signals with the same numbers as in FIG. 2 indicate circuits or signals having equivalent functions.

To explain the operation of the circuit configured in this way, in FIG.
3 rearranges signals in units of channels on the time axis based on the information of control signals 3 and 5 from the control circuit 102. The storage circuit 104 temporarily stores the signal 4 sent from each slave station to the master station in units of one frame. Furthermore, this storage circuit 104 stores channel information used for signal transmission between slave stations on the time axis based on the timing information of the control signal 7 from the control circuit 102. The signal is read out so that it falls within the subframe of the slave station, and is output as an output signal 8. The time division multiplexing circuit 105 outputs the output signal 2 of the storage circuit 101.
The output signal 8 (channel information used for signal transmission between slave stations) of the storage circuit 104 is time-division multiplexed and output as an output signal 9. This output signal 9 is sent from the master station to each slave station.

FIG. 5 is a block diagram showing a specific example of the structure of the memory circuit 104. In FIG. 5, 106 is a random access memory (RAM) in which input signal 4 is written into RAM 106 and output signal 8 is read out based on the information of address signal 10. Selection circuit 107
selects the write address signal 11 and the read address signal 12 of the RAM 106 alternately every frame and outputs them as the address signal 10 of the RAM 106. 108 and 109 are a write address signal generation circuit and a read address signal generation circuit, respectively. These generate a write address signal 11 and a read address signal 12 for the RAM 106 in synchronization with a control signal 7 that controls timing.

In the circuit shown in FIG. 5, when one frame is defined as n channels, for example, in the write address signal generation circuit 108, the input signal 4 is sequentially written from address 0 to address (n-1) of the RAM 106. The read address signal generation circuit 109 rearranges the signals by generating an address signal 12 in which addresses between addresses 0 and (n-1) are arranged in an arbitrary order. conduct.

Here, in the read address signal generation circuit 109,
The method for generating the address signal 12 in which arbitrary addresses of the RAM 106 are arranged in an arbitrary order is as follows. That is, if the address signal 12 does not vary over time, that is, if the channel used for signal transmission between slave stations in the method shown in FIG. The address signal 12 is obtained by sequentially reading the previously stored information from this ROM according to the timing information of the control signal 7.

In addition, if the channel used for signal transmission between slave stations is not fixed in time, that is, if the content of the address signal stored in the ROM is required to fluctuate in time, the above Use RAM instead of ROM. In this case, each time there is a request to change the contents of the address signal, the contents of the address signal written in the RAM are changed according to the contents of the change request, so that the contents can be changed arbitrarily on the time axis. Signals can be rearranged. In this way, signal transmission between arbitrary slave stations is possible using an arbitrary channel at an arbitrary time.

Note that the memory circuits 101 and 103 in FIG. 4 may also be the same circuits as in FIG. 5.

In this way, by adding the storage circuit 104 and the time division multiplexing circuit 105, signals addressed to each station are organized into the same subframe, and in addition to communication between the master station and each slave station, communication between any slave stations is possible. signal transmission becomes possible.

FIG. 6 is a diagram showing an example of the flow of signals in each part when transmitting signals between the master station and each slave station and between A and B of the slave stations using the circuit of FIG. 4. FIG. 6a shows the output signal 2 of the memory circuit 101. F
are frames, SF _A , SF _B . . . SF _N is a subframe, and indicates the time allocated to each slave station A, B, . T _A and T _B are a time slot into which a signal sent from slave station B to slave station A is inserted, and a time slot into which a signal sent from slave station A to slave station B is inserted, respectively. FIG. 6b shows a signal sent from each slave station to the master station, which is the input signal 4 of the memory circuits 103 and 104. SF _A ,
SF _B ...SF _N indicates the signals sent from slave station A, slave station B... slave station N, respectively, and A _B and B _A indicate the signals sent from slave station A to slave station B, respectively. A signal sent from slave station B to slave station A is shown.

FIG. 6c shows the output signal 8 of the memory circuit 104. In the memory circuit 104, the signal b (signal sent from each slave station) is temporarily stored in units of one frame. Signals A B and B _A for signal transmission between stations _A and B are shown in Figure 6a, respectively.
It shows the state read and output at times corresponding to the time slots _TB and _TA of . 6d is a signal obtained by time division multiplexing the signal a (output signal 2 of the memory circuit 101) with the signal c (output signal 8 of the memory circuit 104), which is the output signal 9 of the time division multiplexing circuit 105. . This signal d is sent from the master station to each slave station.

In this way, slave stations A and B extract the signals of their own station allocations SF _A and SF _B from the signals shown in FIG _. A _B can be received.

As described above, according to the present invention, external
A master station signal transmitting/receiving circuit that enables signal transmission between a master station and any slave stations and between any slave stations without requiring a PCM terminal device, etc., and with minimal signal deterioration due to signal transmission. can get.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a time division multiplex communication system to which the present invention is applied. FIG. 2 is a block diagram showing the configuration of a conventional signal transmitting/receiving circuit. Figure 3 is the second
FIG. 3 is a signal configuration diagram showing the input/output signals shown in the figure with the horizontal axis as the time axis. FIG. 4 is a block diagram showing one embodiment of a signal transmitting/receiving circuit according to the present invention. FIG. 5 shows the memory circuit 10
FIG. 4 is a block diagram showing details of 4. FIG. 6 is a signal configuration diagram showing an example of the signals of each part in FIG. 4 with the horizontal axis as the time axis. 101, 103, 104...memory circuit, 102...
Control circuit, 105... Time division multiplexing circuit, 106... Random access memory, 107... Selection circuit, 10
8...Writing address signal generation circuit, 109...
Read address signal generation circuit.

Claims (1)

[Claims] 1. Includes one master station and a plurality of slave stations, the master station sends out time-division signals to each slave station, and the slave stations receive the time-division signals sent from the master station. In the time-division multidirectional multiplex communication system, a timing signal is received and regenerated from this time-division signal, and a signal is sent to the master station at the time allocated to each slave station based on this timing signal. , a first memory circuit 101 that temporarily stores signals transmitted from the master station to the slave stations, and a second memory circuit that temporarily stores signals received from each slave station and transferred to other slave stations via the master station. circuit 104
a third memory circuit 103 that temporarily stores signals received from each slave station and output from the master station and outputs them as master station output signals; and a control circuit 102 that controls writing and reading of each of the memory circuits. , a time division multiplexing circuit 105 that time division multiplexes the readout output of the first storage circuit and the readout output of the second storage circuit, and the control circuit is configured to perform the following: further comprising means for controlling readout of the first and second storage circuits at a timing when a signal of the same destination as the destination of the signal enters from the second storage circuit within the same subframe destined for the same destination slave station. A time division multidirectional multiplex communication system characterized by: