JP2600494B2 - Split H-channel exchange transmission system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an ISDN (Integrated Services Digital Network) based on the CCITT Recommendation I series, which is used for an H channel based on a user / network interface structure.
The present invention relates to a divided H-channel switching transmission system in which a channel is divided into smaller bits, distributed in one frame, and exchanged and transmitted.

[0002]

BACKGROUND OF THE INVENTION Such a divided H-channel switching transmission system will be described with reference to FIGS.

[0003] Fig. 6 shows that the home equipment for ISDN is ISDN.
It is a system diagram which shows an example which connects to (network).

According to FIG. 6, a home device 1 includes a terminal 2B such as a telephone which occupies one of the B channels, which is a 64Kbps line only for voice transmission, and a large amount of data such as a data terminal, for example, a 384Kbps line. A terminal 2H occupying one of the H0 channels is accommodated and connected by a terminal accommodating line 3 to execute an extension exchange connection between the terminals.

On the other hand, the in-home device 1 connects to an ISDN (network) 5 via a subscriber line 4, and connects the ISDN (network) 5 to the extension of each of the terminals 2B and 2H.

In the CCITT recommendation, the side including the home device 1 is defined as a user (customer) with the branch point on the subscriber line 4 for the ISDN (network) 5.

FIG. 7 shows a primary group B channel interface structure "23B +" for an interface speed of 1.544 Kbps of a Japanese standard among user / network interface structures.
D "(A), a primary group H0 channel interface structure" 4H0 "(B), and a mixed channel interface structure (c) in which the 1H0 channel is divided into six and distributed and arranged in six B channels, respectively. FIG. 2 is a diagram illustrating a frame configuration.

FIG. 7A shows the first of 24 channels.
The “23B + D” structure is formed by the 23B channel from the 23rd channel to the 23rd channel and the 24th D channel.

In FIG. 7B, 24 channels are divided into four parts to form a "4H0" structure in which H0 channels are arranged every 384 Kbits starting from channel numbers 1, 7, 13, 19.

The bit code strings in one H0 channel are collectively arranged and switched so that the order is not changed.

Since one H0 channel continuously occupies six B channels, it is difficult to secure the H0 channels collectively at the peak time.

FIG. 7 (C) shows that one H0 channel has six channel numbers 1, 5, 6, 10, 12, and 20, and the B channel (64 Kbit) from the H0-1 channel to the H0-6 channel.
An example of dispersing and disposing them at positions is shown. In this way, the distributed arrangement is adopted in the case of the mixed channel. However, FIG.
As described with reference to, the information of the dispersed H0 channel causes the frame to be switched by the switch processing, and there is an opportunity to change the order.

FIG. 8 is a time chart showing an example of replacement in the switch memory.

As shown in FIG. 8, reception input channel numbers 3, 8, 9, and 13 are sequentially switched to transmission output channel numbers 4, 5, 11, and 12. As shown in the figure, when the transmission and reception frames are synchronized, each of the input channel numbers 3 and 9 can be transmitted in the same frame because the output channel numbers 4 and 11 are the oldest.

On the other hand, the input channel numbers 8 and 13 are transmitted and output after waiting for the next frame because the output channel numbers 5 and 12 are the youngest numbers.

That is, the information of the channel numbers 5 and 12 in one H0 channel is the information of the immediately preceding H0 channel, and the order of the output information is different from the order of the input information.

[0017] Therefore, it is necessary to take measures to prevent the dislocation of the H0 channel from disturbing the order of information in the input / output channel switch processing.

[0018]

2. Description of the Related Art Conventionally, this type of divided H-channel exchange transmission system has two switch memories, and on the one hand, when writing a reception input, on the other hand, means for reading stored information and transmitting and outputting it. Was.

FIG. 9 is a block diagram showing a conventional example.
FIG. 10 is a time chart showing an example of the exchange relationship of the input / output channel information in FIG.

As shown in FIG. 9, an input switching section 91 alternately switches and connects to a switch memory A 92 and a switch memory B 93. An output switching section 94 is controlled by a call control section 95, and the input switching section 91 is connected. Not switch memory A
Switch connection to one of the terminals 92 and B93.

The input switching unit 91 has a buffer memory,
The information to be received and input is alternately switched and connected for each frame and output to the switch memories A92 and B93 under the control of the call control unit 95.

The switch memories A92 and B93 receive instructions from the call control unit 95 alternately, and when one of them writes information,
The other side reads the written information by the output switching unit 94, forms a frame on the transmission line, and transmits and outputs it.

As shown in FIG. 10, in the case of a synchronized input / output frame, when each of the reception input channel numbers 3 and 8 outputs to each of the transmission output channel numbers 4.5, the switch memory A in the first frame is output. Written to
Next, in the second frame, the frames are output collectively.

The input in the second frame in which the stored information is output from the switch memory A is written to the switch memory B and output in the third frame.

Therefore, the information of the H0 channels received and distributed in the same frame can be switched under the control of the call control unit without changing the order in the same frame.

[0026]

The above-described conventional division H
Since the channel switching transmission system has two switch memories and is configured to perform writing and reading alternately, expensive parts of the switch memory and hardware and software for this control are duplicated. Must be operated, especially in the case where one H0 channel is mixed in the "23B + D" structure,
There was a problem that it was uneconomical.

An object of the present invention is to solve the above-mentioned problem by having an additional memory for storing information of at least one H channel, temporarily storing the information of the H channel once, and sequentially transmitting and outputting it in the next frame. Split H with configuration
A channel switching transmission device is provided.

[0028]

The basic structure of the divided H channel switching transmission apparatus of the present invention is to reduce the H channel by the user / network interface structure of ISDN (Integrated Services Digital Network) based on CCITT recommendation I series to a smaller size. Divided H-channel switching transmission device that divides into channels of the number of bits, disperses them in one frame, and performs switching transmission
In location, the division information of the H channel is distributed with additional memory for H channels sequentially extracts and stores the received frame, the non-split channel information and the additional memory in the received frame in one frame, Exchange channel information according to the transmission channel position
Read under the control of the exchange control unit, and
Switching to the channel by memorizing in the designated channel
It has a switch memory for performing switching and a transmission output unit for sequentially taking out and transmitting the stored channel information from the switch memory.

One embodiment of the additional memory and the exchange controller described in the above basic configuration is that the additional memory has a storage capacity for at least one H channel for one basic frame structure, and The exchange control unit makes the writing and reading of the additional memory and the switch memory continuous within one frame, and sets the execution timing to be equal to or higher than the code transmission rate obtained by adding the capacity of the additional memory to one basic frame. is there.

Further, another embodiment of the additional memory and the exchange control section is that the additional memory is composed of two sheets having a storage capacity of one H channel for one basic frame structure, When the exchange control unit writes and stores the received information in one of the additional memories, the stored information is read from the other additional memory to the switch memory.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A divided H-channel switching transmission system according to the present invention will be described with reference to the drawings.

FIG. 1 is a memory configuration diagram showing one embodiment of the present invention, and FIG. 2 is a block diagram showing an example of the memory configuration of FIG.

First, the configuration will be described with reference to FIG. 1 and FIG.

The input to be received has a one-frame / 24-channel configuration, and is temporarily stored in a buffer of the reception input unit 31.
In the example of FIG.
One H0 channel is dispersed among the channels.

Since the six channels distributedly used in the H0 channel are designated by the slot map included in the predetermined channel identifier information, the exchange control unit 30 identifies the reception input, and the reception input unit 31 The data is taken out from the buffer and sequentially written into the channel numbers H1 to H6 of the additional memory 33.

Next, the exchange control unit 30 designates a channel for transmitting the reception input, and also designates a slot map for the H0 channel. With these designations, the B channel is read from the buffer of the reception input unit 31 and the H0 channel is read from the additional memory 33 and written into the switch memory 32.

In the example of FIG. 1, the channel numbers 8.19.21 of the B channel are switched to the channel numbers 22.21.5 of the switch memory 32 from the buffer of the reception input unit 31.

The channel number H of the additional memory 33
Each of the numbers 1 to H6 is distributed and arranged in six channels of the switch memory 32 from channel numbers 6 to 20. The order of the dispersion information of the H0 channel is not changed from the reception input to the distribution information in the switch memory 32.

The transmission output section 34 sequentially extracts stored information from the switch memory 32 at a predetermined code transmission rate in the order of channel numbers, and transmits and outputs the information.

Next, a procedure from reception input to transmission output of channel information will be described with reference to FIG. 3 and FIG.

FIG. 3 is a time chart showing an example of writing (W) and reading (R) of the memory shown in FIGS.

In the example of FIG. 3, one frame / 24 channels of the reception input and the transmission output is 125 μS, and 1544 Kbps.
It has s code transmission rate of Japanese standard.

On the other hand, in the example shown in FIG. 3, the write timing from the buffer of the reception input section 31 to the switch memory 32 and the additional memory 33 is 30 channels obtained by adding the 6 channels of the additional memory 32 to the 24 channels of the reception input. Processing speed of 1920Kbps or more for processing channels. This speed adopts, for example, the European standard of 2048 Kbps.

First, under the control of the exchange control unit 30, the information of the channel numbers 8.19.21 for the B channels is written to the channel numbers 22.21.5 of the switch memory 32 from the buffer of the reception input unit 31, respectively. .

On the other hand, the information of the channel numbers 1.20 for the H0 channel is stored in the channel number H1 of the additional memory 33.
-Written to each of H6.

Next, the information of the channel numbers H1 to H6 of the additional memory 33 is read out from the additional memory 33 at the read timing following the write timing from the reception input section 31, and the switch memory according to the instruction of the exchange control section 30. The data is sequentially written to 6 channels distributed from 32 channel numbers 6 to 20.

The transmission output unit 34 sequentially transmits information stored in the switch memory 32 from a channel number 1 at a code transmission speed of 1544 Kbps.

Accordingly, the information of the H0 channel is output from the reception input unit 31 in the next frame written in the additional memory 33 without changing the order.

In this case, the additional memory is only the additional memory, that is, one H0 of the six B channels.
In addition to the channel memory capacity, there is an effect that the alternate switching means of the two-sheet configuration becomes unnecessary.

FIG. 4 is a memory configuration diagram showing an example in which two H0 channels are divided and transmitted in one "23B + D" interface structure.

In this case, position designations corresponding to the two H0 channels are newly added to the slot map included in the predetermined channel identifier information.

In FIG. 4, the first H0 channel dispersed in the reception input buffer into six channels from channel number 1 to number 11 is stored in the additional memory H01, and the first H0 channel from channel number 8 to number 23 is stored in the additional memory H01. Are collectively stored in the additional memory H02.

This information is stored in each of the additional memories H01 and H02 in the switch memory numbers 2,..., 1 without changing the order.
Output via 0,9, ..., 20.

In this case, only the additional memory of (2 × 6 =) 12 B channels is required for the memory capacity of 24 B channels per frame, and the timing circuit and the buffer memory for alternately switching the two 24 B channels are required. This has the effect of making it unnecessary.

Next, FIG. 5 shows that the interface structure H11 channel (1536 Kbps) corresponds to the H0 channel (384 Kbps).
It is a time chart which shows an example of division.

According to FIG. 5, one frame is composed of 26 channels (384 K × 26 = 9984 Kbp) of the H 0 channel (384 Kbps).
s), which is a 10 Mbps line.

The H11 channel is divided and dispersed into channel numbers 2, 9, 11, and 25 in the reception buffer, and the information is collectively stored in the additional memory. Next, under the control of the exchange control unit,
The H11 channel information on the additional memory is again divided into four,
They are distributed to channel numbers 1, 6, 8, and 20 of the switch memory.

The H0 channel is allocated to channels other than the H11 channel.

In this embodiment, the H0 channel (384 Kbps) is used as the basic channel. However, when the B channel (64 Kbps) is further finely divided, the H11 channel is divided into 24 parts.

The write / read timing speed of the additional memory and the switch memory of this embodiment is (384K × 26).
+ 1536K =) 11.52 Mbps or more.

In the above embodiment, the timing speed of writing / reading to / from the switch memory and the additional memory has been described as the speed obtained by adding the code transmission speed of the additional memory to the input / output code transmission speed. Instead, one switch memory and one or more additional memories are used, so that the capacity can be expected to be reduced by the capacity difference between the additional memory to be provided and the one switch memory.

The memory capacity can be reduced by using two additional memories, providing an alternate switching timing and a buffer memory, and using the additional memory in the same manner as the conventional switch memory shown in FIG.

For example, when two additional memories for one H0 channel are used for one “23B + D” structure,
The memory capacity for 12B channels can be reduced. In this case, a memory alternate switching timing circuit and a buffer are required for the additional memory.

[0064]

As described above, according to the divided H channel exchange transmission system of the present invention, an additional memory for the divided H channel information is provided for one switch memory.
Since the received distributed H-channel information is temporarily stored in the above-mentioned additional memory once and then written into the switch memory, the distributed information is added by adding a small amount of additional memory to one switch memory. And the exchange transmission processing can be performed while maintaining the above-mentioned order.

[Brief description of the drawings]

FIG. 1 is a configuration connection diagram showing one embodiment of a memory configuration and a switch path of a “23B + D” interface structure according to the present invention.

FIG. 2 is a configuration diagram showing an example for realizing FIG. 1;

FIG. 3 is a time chart showing an example of a switch processing procedure according to FIG. 1;

FIG. 4 is a configuration connection path showing an example in which an additional memory is doubled in FIG. 1;

FIG. 5 is a configuration connection diagram showing an example in which the B channel is changed to the H0 channel and the H0 channel is changed to the H11 channel in FIG. 1;

FIG. 6 is a system diagram showing an example of a connection relationship between an ISDN (network) and a user.

FIG. 7: B channel and H0 according to CCITT standard
FIG. 3 is a frame configuration diagram showing an example of each of a channel and a B / H0 mixed channel.

FIG. 8 is a time chart illustrating an example of a switch processing procedure in one switch memory;

FIG. 9 is a block diagram showing a conventional example.

FIG. 10 is a time chart illustrating an example of a switch process according to FIG. 9;

[Explanation of symbols]

 Reference Signs List 30 exchange control unit 31 reception input unit 32 switch memory 33 additional memory 34 transmission output unit

Claims (3)

(57) [Claims] 1. IS based on CCITT recommendation I series
A divided H channel switching transmission apparatus for dividing an H channel by a user network interface structure of a DN (Digital Integrated Services Network) into channels having a smaller number of bits, distributing and transmitting within one frame , and The H channel for sequentially extracting and storing the H channel division information distributed from
An additional memory for the channel, and a channel corresponding to the transmission channel position from the non-divided channel information in the received frame and the additional memory.
Read out the tunnel information under the control of the exchange control unit, and
By storing in the channel specified by the control unit,
A split H-channel exchange transmission device, comprising: a switch memory for switching channels; and a transmission output unit for sequentially extracting stored channel information from the switch memory and transmitting the information. 2. The additional memory has a storage capacity for at least one H channel for one basic frame structure, and the exchange control unit performs writing and reading of the additional memory and the switch memory in one frame. 2. The divided H-channel switching transmission device according to claim 1, wherein the execution timing is equal to or higher than a code transmission rate obtained by adding the capacity of the additional memory to one basic frame. Wherein two having a storage capacity of one H channels to the additional memory is one basic frame structure
2. The division according to claim 1, wherein the switching control unit comprises one memory , and when the exchange control unit writes and stores the received information in one of the additional memories, the stored information is read from the other additional memory to the switch memory. H-channel switching transmission equipment .