JPS6138912B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an apparatus for converting time slots of time division multiplexed data.

Conventionally, time slot conversion has a holding memory BFM for one frame as shown in Figure 1, and the holding memory BFM is converted according to instructions from the control memory CTL MEM.
This was achieved by reading out the data.
At this time, in one frame, there was no distinction between data bits (hereinafter abbreviated as D bits) and status bits (hereinafter abbreviated as S bits), and the frame configuration as shown in FIG. 2 was common. Therefore, each channel (hereinafter abbreviated as CH) in one frame has multiple D bits and one S bit, and in the case of a multiplexed frame configuration as shown in Figure 3, the D bit and S bit are Time slot conversion will be performed separately. Here, the frame structure shown in FIG. 3 will be briefly explained. ^Dm _o is the D bit of CHn, and m at the upper right means the m-th bit of CHn in this frame.
Sn is the S bit of CHn, and time slots are assigned at regular intervals within one frame. A multiplexing device having such a frame structure does not need to have a buffer memory corresponding to the circuit, so it can be easily realized with a small amount of hardware.

Now, if we pay attention to CH in Figure 3, we can see that
The S bit of CH has a meaning with respect to the D bit within the same frame, for example, the six bits D ⁰ ₁ to D ⁵ ₁ in CH1. When time slot conversion of D bits and S bits is performed using the conventional method as described above, the relationship between input and output is as shown in FIG. Fourth
The figure shows an example of converting CH5 to CH1. At this time D
⁰ ₅ to D ⁴ ₅ are output in the same frame as the input, and S ₅ and D
⁵ ₅ will be output in the next frame, so the D of S bit
The meaning of bits is lost.

The present invention temporarily holds the D bit and S bit,
The object of the present invention is to provide a time slot conversion device which solves the problem by delaying the output by one frame, maintains the relationship between the S bit and the D bit, and performs the time slot conversion within one frame.

In the time slot conversion device of the present invention, one frame consists of data bits and status bits of multiple channels that are time-division multiplexed, and the time intervals of the data bits and the time intervals of the status bits are different between any two channels. a multiplexing circuit that has a plurality of synchronous input/output lines according to a multiplexing method and multiplexes inputs from these multiple input/output lines; (number of channels) x (number of input lines) x (number of data bits in one frame assigned to one channel)] one side frame buffer memory having a capacity of 1 bit, and the output of the multiplexing circuit. It is connected to the two-sided status path memory that holds status bits as an input, and the output of the frame buffer memory, and receives data bits of [(number of channels of one input line) x (number of input lines)] bits. It is characterized in that it is equipped with a two-sided data path memory for holding and performing time slot conversion, and performs time slot conversion only within one frame.

Next, the present invention will be explained with reference to the drawings.

FIG. 5 is a block diagram showing an embodiment of the time slot conversion device of the present invention. LN1 to LN
Reference numeral 8 indicates input/output lines of the present apparatus, each of which carries frame data as shown in FIG. 3, which was illustrated earlier. LN1 to LN8 are connected to a multiplexing circuit MPX. The output of MPX is frame buffer memory FBM, status path memory SPM0,
Connected to SPM1. Furthermore, the output of the FBM is connected to data path memories DPM0 and DPM1. The outputs of DPM0 and SPM0 are connected to selector _S1 , and the outputs of DPM1 and SPM1 are connected to selector _S2 . Additionally, the outputs of S ₁ and S ₂ are connected to selector S ₃
The output of S ₃ is connected to the demultiplex circuit
Connected to DMPX. Each memory FBM, DPM0,
The addresses of DPM1, SPM0, SPM1, CHLMEM are data channel counters DCHCTR, S
It is given by the combination of the outputs of bit channel counter SCHCTR and LN counter LNCTR. A gate signal for each selector S ₁ to _{S 8} is given by a gate control circuit GCTL.

Next, in one embodiment of the present invention as described above,
Applying the frame in Figure 3, change CH5 of LN2.
The process of converting LN8 to CH1 will be explained. Here, in the frame of FIG. 3, D ^m ₁ to D ^m ₈ are 1
Name it channel interval. (hereinafter abbreviated as 1CI), one frame consists of 6 CIs and 8 S bits. The D and S bits of each CH of each LN are further multiplexed in MPX. In the embodiment shown in FIG. 5, the D bit and S bit are
It is multiplexed as shown in the figure. Therefore the actual
TS conversion is performed for (number of input lines) x (number of CHs per LN) TSs. Input from LN2
D bit ^D35 _of CH5 is sampled with the assigned sampling pulse _T52 , and CH5 of each LN
are sequentially written to the FBM in the order of T ₅₁ , T ₅₂ , T ₅₃ . Similarly, S bit S ₅ can be set to SPM 0 or 1.
will be written to. The data written to the FBM is read out in units of 1 CI in time to be output to the line one frame later, and written to DPM0 or 1. Here, data CH5, which is periodically read out at timing T18 assigned to CH1, _LN8 of the TS conversion control memory "CTLMEM",
Address CH5 of DPM indicated by LN2, contents ^D35 of _LN2 are read out at time _T18 . i.e. LN2
TS was converted from CH5 of LN8 to CH1 of LN8. S bit S ₅ is also SPM according to CTLMEM data.
The contents of S ₅ are read out and are transferred from CH5 of LN2 to LN8
TS is converted to CH1. DPM0 and DPM1 are in a relationship such that when one is writing data, the other is reading data according to CTLMEM, and SPM0 and SPM1 are in the same relationship.
Selectors S ₁ and S ₂ select the SPM output from the DPM output. Selector _S3 selects the SPM or DPM that is being read. In other words, the TS-converted LN2, CH5 data is _S1 or
It is sent to the desampling circuit through S ₂ and S ₃ ,
CH1 of LN8 by desampling pulse T ₁₈
separated into Data from LN1 to LN8 of CH1 is buffered once and output on all lines.

FIG. 7 shows the time relationship between input and output in the embodiment described above. That is, the _D bits ^{D05 to} _D55 and S bit _S5 input _{in frame #1 are all input to D01 to D51 and S1} ⁱⁿ _{the next} frame ^.
It is converted to TS and output. Therefore, TS conversion was performed while maintaining the relationship between the D bit and the S bit.

In the present invention, as explained above, by temporarily storing the D bit and S bit and delaying the output by one frame, it is possible to perform TS conversion of the D bit and S bit within the same frame.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional time slot conversion device, FIG. 2 is a diagram showing a conventional frame structure, FIG. 3 is a diagram showing an example of a frame structure, and FIG. 4 is an input diagram of the conventional device. FIG. 5 is a block diagram showing an embodiment of the present invention. FIG. 6 is a diagram showing an example of multiplexed data in the present invention. FIG. 7 is a diagram showing an example of multiplexed data in the present invention. FIG. 3 is a diagram showing the time relationship between MPX...Multiplexing circuit, FBM...Frame buffer memory, DPM...Data path memory, SPM
...Status path memory, S ₁ to S ₈ ... Selector, DMPX ... Demultiplex circuit, BF ...
Buffer memory, CTLMEM...Random access memory or read-only memory, G ₀ , G ₁
...gate circuit, DCHCTR, SCHCTR,
LNCTR...Counter circuit, GCTL...Gate control circuit.

Claims (1)

[Claims] 1. One frame consists of data bits and status bits of multiple channels time-division multiplexed,
It has multiple synchronous input/output lines that follow a multiplexing system in which the time interval of data bits and the time interval of status bits are different between any two channels, and the inputs from these multiple input/output lines are multiplexed. A multiplexing circuit, the output of this multiplexing circuit as input, and at least [(number of channels of one input line) x (number of input lines)
×(number of data bits in one frame allocated to one channel)] One side of frame buffer memory having a capacity of bits, and two sides of frame buffer memory which receives the output of the multiplexing circuit and holds status bits. A status path memory and a two-sided memory which are connected to the output of the frame buffer memory, hold data bits of [(number of channels of one input line) x (number of input lines)], and perform time slot conversion. A time slot conversion device comprising a data path memory and performing time slot conversion only within one frame.