JP2601219B2 - Multiplexer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplexer, and more particularly to a digital line terminator for multiplexing data input through a plurality of B channels in an ISDN (Digital Integrated Services Network) communication system. is there.

[0002]

2. Description of the Related Art Conventionally, in a multiplexing apparatus of this type for multiplexing input data using a plurality of transmission lines, a relative phase difference caused by a difference in transmission delay time between each line is determined. Need to absorb. To this end, a data memory having a capacity capable of absorbing the maximum phase difference and an address control unit for controlling each address for writing and reading of these data memories are provided for each transmission line. Using the memory as a buffer, the data of the corresponding transmission line is temporarily written in each buffer, read out after performing time compensation, and then multiplexed.

[0003] In such a multiplexing apparatus, 384 Kbps data communication is possible by using a so-called bulk transmission system that bundles 64 Kbps B channels of ISDN.

[0004]

As described above, in the conventional multiplexing apparatus, it is necessary to provide a data memory capable of absorbing the maximum phase difference for each transmission line with a guaranteed margin. There is a drawback that this data memory is required in a number, which increases the cost.

Therefore, the present invention has been made to solve such a drawback of the conventional device, and an object of the present invention is to store one data memory according to the delay state of each transmission line at that time. The present invention provides a multiplexing apparatus which can optimally divide and use a phase difference of each transmission line with a small amount of hardware.

[0006]

According to the present invention, there is provided a dividing means which is disposed opposite to each other via a data line of a plurality of channels, and divides transmission data from each terminal and sends the divided data to the plurality of channels; A multiplexing apparatus comprising: delay compensating means for compensating for each transmission delay; and means for multiplexing the delay-compensated divided data and restoring data transmitted from an opposite terminal. Means for performing multi-frame synchronization detection between the plurality of channels to obtain multi-frame synchronization between the channels; and multi-frame synchronization means for receiving data of each channel after the multi-frame synchronization as inputs. A data memory for compensating the transmission delay time, and a multi-channel of each channel at a predetermined time after synchronization by the multi-frame synchronization unit. Address determining means for calculating an address for each channel of the data memory based on the frame number and controlling the address to be divided and used for a memory map section corresponding to each channel; and an address for each channel determined by the address determining means. And an address control means for controlling the operation of each memory map unit as a buffer for one multi-frame synchronization while generating write / read addresses of the data memory in accordance with the above-mentioned method.

[0007]

The phases of the multi-frame data of each channel input via the data lines of a plurality of channels are aligned by multi-frame synchronization detection, and based on each multi-frame number at a certain point in time after the phases are aligned, An address for each channel of the data memory is calculated, and the data memory is controlled so as to be divided and used in a memory map section corresponding to each channel.

Then, a write / read address is generated such that each memory map section of the data memory is used as a buffer of one multiframe cycle to perform writing / reading, and multiframe data of each channel is synchronized with all memory map sections. It is derived in phase synchronization.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In FIG. 1, the ISDN multiplexers 8A and 8B
They are arranged to face each other via the SDN network 10. Each ISDN
The multiplexing devices 8A and 8B divide the data respectively transmitted from the subordinate terminals 9A and 9B and transmit the data to a plurality of B channels, and compensate for the transmission path delay of each B channel to absorb the relative phase difference. And has the function of restoring data transmitted from the terminal at the other end while multiplexing.

The ISDN multiplexers 8A and 8B have the same configuration, and a specific example of only the multiplexer 8A is shown.

The division transmission section 7 has a function of dividing data transmitted from the terminal 9A and transmitting the divided data to a plurality of B channels (n is assumed to be n). The transmission path delay compensator 6 includes a multi-frame synchronization accumulator 5, a data memory 3, and a data memory controller 4. Multi-frame synchronization storage unit 5
Is a memory for detecting multi-frame synchronization between n B channels and achieving multi-frame synchronization for each of these channels. Assuming that the multi-frame structure of each channel is a format composed of m multi-frames F1 to Fm shown in FIG. 1, the multi-frame synchronization storage unit 5 performs multi-frame synchronization detection in the multi-frame format and performs CCITT Recommendation H. The multi-frame synchronization is performed in accordance with the frame synchronization method defined in H.221.

For each channel data after the multi-frame synchronization, the data memory 3 is a buffer memory for absorbing a relative phase difference of delay of each channel. The control of the data memory 3 is performed by the data memory control unit 4. The data memory control unit 4 determines the memory for each channel from the multi-frame numbers (F1 to Fn) read from the multi-frame for each channel in a state where the multi-frame synchronization and accumulation unit 5 has synchronized the multi-frame. The address is calculated and determined, and the data memory 3 is divided and used as a memory map for each channel.

The memory map section divided corresponding to the channel operates as a buffer having one multi-frame cycle as one cycle. The write / read address (W / R address) corresponding to each memory map section from the data memory control section 4 is provided. ) Is controlled.

FIG. 2 shows an example of a multi-frame time chart of each channel of each section in the block of FIG. As shown in FIG. 2A, the data a divided from the multiplexing device 8B on the calling side and transmitted to each B channel is in phase in all the channels. It is assumed that this data a is received as shown in FIG. 2B as data b delayed in each of the transmission paths in the multiplexer 8A on the called side.

In the multi-frame synchronous accumulation section 5, data of each channel having such a phase shift is applied to the above-described H.264 data. Synchronization detection is performed by the multi-frame synchronization detection method according to the standard of H.221, and each data is stored in the memory. As a result, data c in which multi-frame synchronization has been obtained between the respective channels is output, and is input to the data memory 3 as data having a phase relationship as shown in FIG. 2C.

By the data memory 3 and the data memory control unit 4, the data d in which the phase difference between the transmission lines is absorbed is time-division multiplexed and output to the called terminal 9A as shown in FIG. 2d. Will be.

Hereinafter, the operation of the data memory 3 and the data memory control unit 4 will be described in detail with reference to FIGS. The data frame control unit 4 reads the frame number e of each channel at a certain time of the multiframe-synchronized data c in the multiframe synchronization storage unit 5. In the example of FIG. 2, the combination pattern “F2, F3, F1,.
.., F2 "are read.

Based on the read frame number combination pattern e of each channel, a memory capacity necessary to absorb the phase difference of each channel is calculated, and according to the memory capacity corresponding to each channel, Data memory 3
Is divided for each channel and used as a data buffer for absorbing the phase difference.

Then, first, the memory capacity is calculated based on each frame number of the combination pattern e of the frame numbers. The calculation rule is determined as follows. That is, the frame numbers "F2" and "F2" at the time point e when the multi-frame synchronization of each channel is established at the time of data transmission / reception.
, "F1",..., "F2", the memory capacity of the i-th channel (i = 1 to n) is (multi-frame number of i-th channel)-(minimum multi-frame number of all channels). ... (1)

Therefore, in the first channel CH1, (F2
−F1) = 1 The capacity for one multi-frame is required. In the second channel CH2, the capacity for (F3-F1) = 2 multi-frames is necessary. In the third channel CH3,
(F1−F1) = 0, and the data buffer is substantially unnecessary (because the third channel has the largest delay, so that the data buffer does not need to absorb the phase). F1) = 1 It is calculated that a capacity for one multi-frame is required. This is shown in the table “e” and “memory capacity” in the upper left of FIG. 3, respectively.

The capacity for one multi-frame is equal to the number of bits constituting one multi-frame in the multi-frame format. For example, if one multi-frame is 64 bits, the capacity is a capacity corresponding to 64 bits. is there.

A plurality of memory maps each corresponding to the obtained memory capacity for each channel are divided and used in the data memory 3, and the addresses (data) of the memory map corresponding to each channel are used. The address in the memory 3 needs to be determined.

Therefore, in the present embodiment, the address
Dress conversion table (ROM: read only memory)
I'm using In this case, the frame of each channel indicated by e
Pattern number combination pattern “F2, F3, F1,...,
F2 ", the input address of this ROM table is
From the first channel to the n-th channel,231 ………
20 ","231 ... 21 ","231 ... 2
2 ", ..."231 ... 2(N-1) "
Keep it. This corresponds to the “ROM input address” in the upper left table of FIG.
Dress ".

The ROM input address 2 underlined
31... 2 are frame numbers F2F3F1... F2 of each channel indicated by e, which are alphanumeric characters (positively the frame numbers themselves), and 01,1,2 at the end of 231. ,..., (N-1) are added to form ROM input addresses corresponding to the respective channels.

As for the combination pattern of the frame numbers of the respective channels indicated by e, if the number of multiframes m (F1 to Fm) is, for example, 64, 64 ⁿ combinations patterns can theoretically exist. The address is also a ROM input address as described above in order to be able to correspond to these 64 ⁿ combinations.

In the case of the combination pattern of frame numbers indicated by e in this case, the capacity of the memory map corresponding to the channel is known as described above.
Are calculated in advance according to the capacity of the memory map, and each ROM in the ROM table is calculated in advance.
Each of them can be stored in the entry corresponding to the input address.

In this example, the first address in the data memory 3 of the memory map required for the first channel is set to address 1 (where 1 of the address 1 is when a multi-frame is considered as one unit), The start address of the memory map required for the next second channel is address 2. Since this second channel needs a capacity of 2 multiframes,
The address 2 and the subsequent address 3 are assigned to the second channel.

For the next third channel, theoretically, no memory is required and data can be considered as a through state. In the following, the head address of the memory map of each channel is allocated in order, and the last n-th channel is set to the address x and one multi-frame is allocated.

As a result, as shown in FIG. 3, the data memory 3 is divided into a plurality of memory map sections each having a capacity sufficient to absorb the phase difference of the corresponding channel, corresponding to each of the channels CH1 to CHn. Will be used as a data buffer. The data buffer of each memory map unit is controlled by the data memory control unit 4 as a buffer of one multi-frame cycle. 1
Since the multi-frame is 64 bits in this example,
Each operates as a 64-bit data buffer.

An operation time chart is shown on the right side of the data memory 3 in FIG. 3, and the writing and reading control of each data buffer is performed in synchronization with the clock of the multi-frame configuration bit. As shown in the figure, reading (R) and writing (W) are performed in the first half and the second half of a one-bit clock cycle, and a bit (W) written in a certain multi-frame cycle is set after the next one multi-frame cycle. It is read (R).

FIG. 4 is a block diagram showing an example of the data memory control unit 4 for controlling the writing and reading of the data memory 3. The write address counters (WAC) 44 to 44 (corresponding to channels) correspond to each memory map unit. 46 and read address counters (RAC) 47 to 49 are provided, respectively.
RAC is controlled.

That is, each of the WACs and RACs is a counter which can select and control each cycle such as 64 × 1 cycle, 64 × 2 cycle, 64 × 3 cycle,... The bit clock described above is counted.

Here, if the combination pattern of the frame numbers of the respective channels e at the time when the multi-frame synchronization is established as shown in FIG. 3 is determined, the memory capacity required to absorb the phase difference of each channel becomes ( Since it can be calculated by the equation (1), the memory capacity calculation unit 42 calculates this and sends it to the address control unit 41. Further, the ROM 43 generates the head address of the memory map of each channel and sends it to the address control unit 41.

The address control unit 41 determines the W for each channel from the memory capacity of each channel and the start address.
The counter cycle and the initial value are loaded into AC and RAC, respectively.

As a result, data in which the phase difference between the transmission lines is absorbed is obtained from the data memory 3 as shown in FIG. 2D, multiplexed in a time-division manner and transmitted to the called terminal 9. Will be.

Note that the memory capacity calculation unit 42
It can be composed of OM. That is, if the combination pattern of the frame numbers indicated by e of each channel is determined, the capacity of each channel is uniquely determined by the equation (1). Therefore, each entry of the ROM input address of the address conversion ROM table at the upper left of FIG. It is sufficient that the above-mentioned respective capacities are calculated in advance and stored.

[0038]

As described above, according to the present invention, a plurality of IS
In order to absorb the relative phase difference due to the transmission delay of the DN-B channel, a common data memory is used as a plurality of memory maps that are optimally divided for each channel, so that the data memory can be used effectively and cost is reduced. This also has the effect of being advantageous. Further, the transmission path delay to be compensated can be made variable by the number of channels to be bundled, and therefore, when the number of channels to be bundled is small, a larger delay can be compensated.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a time chart of a multi-frame of each part of the block of FIG. 1;

FIG. 3 is a schematic diagram for explaining the operation of the block in FIG. 1;

FIG. 4 is a block diagram illustrating an example of a data memory control unit 4 of the block in FIG. 1;

[Explanation of symbols]

 Reference Signs List 3 data memory 4 data memory control unit 5 multi-frame synchronization storage unit 6 transmission line delay compensation unit 7 division transmission unit 8A, 8B ISDN multiplexer 9A, 9B terminal 10 ISDN network 41 address control unit 42 memory capacity calculation unit 43 ROM 44 ~ 46 Write address counter 47 ~ 49 Read address counter

Claims (4)

(57) [Claims] A dividing means for dividing transmission data from each terminal and transmitting the divided data to the plurality of channels, and a delay compensator for compensating a transmission delay of each of the channels; And a means for multiplexing the delay-compensated divided data and restoring data transmitted from the terminal at the other end, wherein the delay compensation means comprises: Multi-frame synchronization means for performing frame synchronization detection and performing multi-frame synchronization between these channels; and a data memory for compensating for transmission delay time of each channel by using data of each channel after the multi-frame synchronization as an input. Based on the multi-frame number of each channel at a predetermined time after synchronization by the multi-frame synchronization means. Address determining means for calculating an address for each channel of the memory and controlling to use the memory map portion corresponding to each channel in a divided manner; writing and reading of the data memory according to the address for each channel determined by the address determining means Address control means for controlling the operation of each memory map section as a buffer of one multi-frame period while generating addresses, respectively. 2. The read-only memory according to claim 1, wherein said address determining means stores in advance each address of a memory map section of said data memory corresponding to all possible combinations of multi-frame numbers of each channel at said predetermined time. The multiplexing device according to claim 1, further comprising: 3. An address control unit comprising: a memory capacity calculating unit for calculating each capacity of the memory map corresponding to a channel based on a multi-frame number of each channel at the predetermined time; an output of the read-only memory; 3. The multiplexing apparatus according to claim 2, further comprising address generation means for generating a write / read address of each memory map unit in accordance with a calculation capacity of said calculation means. 4. The data line is an ISDN line,
4. The multiplexing apparatus according to claim 1, wherein said channel is a B channel of said ISDN line.