JP3198675B2 - Data rate converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data rate converter for reproducing a signal by demultiplexing a signal in which a plurality of asynchronous frames are multiplexed.

[0002]

2. Description of the Related Art SDH (SYNCHRONOUSDIGITAL HIERARCH) is a new synchronous network standardized by CCITT.
When implementing the data transmission according to Y), there are a plurality of rates in the overhead multiplexing process and the demultiplexing process. As basic multiplexing units, there are a container (hereinafter C), a virtual container (hereinafter VC), and an STM (see CCITT recommendation: G.707 to 709).

FIG. 5 shows an STM-1 frame configuration. 5, 501 is a C-4 frame, 502 is a POH
(Path overhead), 503 is a VC-4 frame,
504 is an SOH (section overhead), 505
Is an AU pointer, and 506 is an STM-1 frame.

[0004] As shown in FIG.
The multiplexed OH (path overhead) 502 is V
C-4 frame 503, VC-4 frame 503
A multiplexed OH (section overhead) 504 and AU pointer 505 is the STM-1 frame 50.
6. The VC-4 frame 503 is STM-1
Since it is asynchronous with the frame 506, the AU pointer 5
05 indicates the leading phase of the VC-4 frame 503 when multiplexing the VC-4 frame 503 into the STM-1 frame 506.

Here, the signal rates are different from each other,
In an 8-bit parallel state, the C-4 frame is 18.7.
2 Mbps, VC-frame is 18.792 Mbps
Since the s, STM-1 frame is at 19.44 Mbps, a method of performing data rate conversion using a buffer memory is usually used during multiplexing and demultiplexing.

FIG. 3 is an example of the configuration of a data rate conversion device showing a first conventional example. In FIG. 3, 301 is F
IFO (1), 302 are STM timing generation circuits,
03 is a pointer processing / stuff decision circuit, 304 is AN
D gate, 305 is STM deframer, 306 is FIF
O (2), 307 is a VC timing generation circuit, 308 is an AND gate, 309 is a VC deframer, 310 is ST
M-1 data input terminal, 311 is an STM-1 clock input terminal, 312 is an STM-1 frame pulse input terminal,
313 is a VC-4 clock input terminal, 315 is a C-4 data output terminal, 316 is a C-4 clock input terminal, 31
7 is a data rate conversion device.

In FIG. 3, first, the STM deframer 3
05 from the STM-1 data input terminal 310
Data is input, and the STM timing generation circuit 302 generates a VC-4 based on the STM-1 frame pulse input from the STM-1 frame pulse input terminal 312.
Is generated, and this signal and the STM-1 clock input from the STM-1 clock input terminal 311 are used to write the write clock (W
CK1) is generated and the FIFO (1) 30
Write data to 1. Then, the read clock (RCK) input from the VC-4 clock input terminal 313
In step 1), VC-4 data and VC-4 frame pulse are read from FIFO (1) 301.

However, the STM-1 frame and the VC-4 frame are asynchronous.
-4 frame pulse and FIFO at the same time as data
(1) Write to 301. Furthermore, STM-
One frame has a stuff byte. If stuff processing has been performed, stuff determination is performed in the pointer processing / stuff determination circuit 303, and the information is transferred to the STM timing generation circuit 302 to be decoded. It is assumed that stuff processing is performed to control the write clock (WCK1).

Next, the VC-4 data is input to the VC deframer 309, and the VC timing generator 307 generates the VC-4 data from the VC-4 data based on the VC-4 frame pulse output from the FIFO (1) 301. A signal corresponding to C-4 data is generated, and this signal and VC-4
A write clock (WCK2) is generated by the AND gate 308 with the VC-4 clock input from the clock input terminal 313, and the FIFO (2)
Write data to 306. Then, the read clock (RCK) input from the C-4 clock input terminal 316 is input.
In 2), C-4 data is read from FIFO (2) 306. As described above, the data rate converter 315 can perform the data rate conversion of STM-1 and C-4.

FIG. 4 shows an example of the configuration of a data rate converter according to a second conventional example. In FIG. 4, 401 is F
IFO (1), 402 is a VC timing generation circuit, 40
3 is an AND gate, 404 is a POH generation circuit, 405 is a selector, 406 is a VC framer, and 407 is a FIFO.
(2), 408 is an STM timing generation circuit, 409 is an AND gate, 410 is a stuff determination circuit, and 411 is S
OH generation circuit, 412 is a selector, 413 is an STM framer, 414 is a C-4 data input terminal, 415 is a C-4 data input terminal.
Clock input terminal, 416 is C-4 frame pulse input terminal, 417 is VC-4 clock input terminal, 418 is S
TM-1 frame pulse input terminal, 419 is STM-1
A data output terminal, 420 is an STM-1 clock input terminal, and 421 is a data rate converter.

In FIG. 4, first, the VC framer 406
C-4 data is input from a C-4 data input terminal 414, and C is input from a C-4 clock input terminal 415.
-4 clocks are used as the write clock (WCK1) of the FIFO (1) 401, and data is written to the FIFO (1) 401. Further, in the VC timing generation circuit 402, based on the C-4 frame pulse input from the C-4 frame pulse input terminal 416 and indicating the head position of the C-4 frame, a pulse indicating the position where the POH is multiplexed is generated. The VC-4 clock input from the VC-4 clock input terminal 417 and the AND gate 403
D is read and data is read by using this as a read clock (RCK1) for the FIFO (1) 401.
Then, the POH generated in the POH generation circuit 404
By switching and multiplexing the data in the selector 405 with the select signal supplied from the VC timing generation circuit 402, VC-4 data can be obtained.

Next, the VC-4 data input to the STM framer 413 is FIFO-converted by the VC-4 clock (WCK1) input from the VC-4 clock input terminal 417.
(2) Write to 407. Further, in the STM timing generation circuit 408, based on the STM-1 frame pulse input from the STM-1 frame pulse input terminal 418 and indicating the head position of the STM-1 frame, a pulse indicating the position for multiplexing the SOH is generated. Generate and AND gate 4
09, AND with the STM-1 clock input from the STM-1 clock input terminal 420, and
Data is read by using the read clock (RCK2) of the IFO (2) 407. Then, the SOH data generated in the SOH generation circuit 411 is switched and multiplexed in the selector 412 by the select signal supplied from the STM timing generation circuit 408, so that STM-1 data can be obtained.

However, since the VC-4 frame (C-4 frame) and the STM-1 frame are asynchronous, the FIF
When the stuff byte is required by monitoring the FIFO accumulation amount in O (2) 407 by the stuff determination circuit 410, a stuff is requested from the STM timing generation circuit 408, and the FIFO (2) 407 read clock (RCK2 ) Shall be controlled. As described above, the data rate conversion device 421 allows C-4 and ST
M-1 data rate conversion can be performed.

[0014]

However, in the above conventional configuration, since two buffer memories are used, LS
When the device is configured by I, the number of gates of the LSI increases, which hinders the realization of the LSI, causes an increase in cost, and further increases transmission delay.

In view of the above, the present invention reduces the number of gates of an LSI while reducing the number of gates of an LSI with a small buffer capacity when performing rate conversion of a signal in which signals of N types are multiplexed. It is an object to realize a data rate conversion device with a simple configuration.

[0016]

Means for Solving the Problems The present invention for forming the object reaches an asynchronous multiple frame by using the buffer memory
The multiplexed STM data is demultiplexed into C (con
Tena) A data rate converter that reproduces data
Te, VC (virtual container with stuff bytes
Indicating Na) data and staff judging means for detecting the presence of stuff bytes in the STM data multiplexed, the multiplexed the portion corresponding to VC data into the STM data by the determination result of the stuff determination means VC De
A first timing generating means for generating a chromatography data effective area signal, detects the pointer indicating the frame start position of the VC data, a pointer processor for generating a VC frame pulse indicating the VC frame start position, the VC data and VC clock generating means for generating a VC clock a chromatic <br/> effective area signal and the STM clock, using the VC clock,
And second timing generating means for generating a C data chromatic <br/> effective area signal of a portion corresponding to the C data multiplexed to the STM data by the VC frame pulse, before <br/> Symbol VC it is configured to and a writing clock generating means for the data valid region signal by synthesizing the C data valid region signal to generate a write clock of the buffer memory.

Alternatively, C (container) data is multiplexed with VC (virtual container) data by using a buffer memory, and the VC data is multiplexed with a stuff byte by S.
Data rate converter for multiplexing with TM data
Te, a judging means for performing insertion request stuff byte monitors the storage amount of pre-Symbol buffer memory, multiplexing the time of multiplexing the VC data to generate a stuff bytes according determination result of said determination means to the STM data A fourth timing generating means for generating a VC data valid area signal indicating a conversion position, a VC clock generating means for generating a VC clock using the VC data valid area signal and the STM clock ,
VC clock and C frame indicating the start position of the C data
The C data to the VC data using
The C data effective area signal indicating the multiplexing position when multiplexing
A third clock generating means for generating the read data and a read clock generating means for generating a read clock for the buffer memory by combining the VC data valid area signal and the C data valid area signal. It is a thing.

[0018]

According to the present invention, the data rate conversion (STM-1 → C-
4 or C-4 → STM-1) and the circuit scale of the data rate conversion device can be reduced, so that the data rate conversion can be performed with one chip or a small LSI, and the total buffer memory capacity is reduced. Therefore, the transmission delay is also reduced.

[0019]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows a main configuration of a data rate conversion device according to a first embodiment of the present invention.

In FIG. 1, reference numeral 101 denotes a FIFO;
Is an STM timing generation circuit, 103 is a VC timing generation circuit, 104 is a synthesis circuit, and 105 is pointer processing.
Stuff determination circuits, 106 and 107 are AND gates, 1
08 is an STM-1 data input terminal, 109 is an STM-1
Clock input terminal, 110 is an STM-1 frame pulse input terminal, 112 is a C-4 data output terminal, 113 is a C
-4 clock input terminal, 114 is a data rate converter. AND gate 106 provides a means for generating a VC clock.
Make up.

As shown in FIG. 1, the STM-1 data input terminal 108 of the data rate converter 114
One data is input. Then, in the STM timing generation circuit 102, a pulse corresponding to data other than the SOH and AU pointer is generated based on the STM-1 frame pulse input from the STM-1 frame pulse input terminal 110. VC indicating the head position of the VC-4 frame in the stuff determination circuit 105
A −4 frame pulse is generated, and the position of the POH is detected by the VC timing generation circuit 103 using the pulse, and a pulse corresponding to data other than the POH is generated.

Here, the two types of pulses are combined by the synthesizing circuit 10.
4 and the STM-1 clock input from the STM-1 clock input terminal 109 and the AND gate 107
To generate an appropriate write clock (WCK) other than the SOH, AU pointer, and POH,
This is used as a write clock of the FIFO 101 as C-4.
Only the portion corresponding to the data is written to the FIFO 101. Then, C-4 data can be read from the FIFO 101 by the read clock (RCK) input from the C-4 clock input terminal 113.

However, since the STM-1 frame and the VC-4 frame are asynchronous, a stuff byte is provided in the STM-1 frame. However, when stuff processing is performed, pointer processing / stuffing is performed. Judgment circuit 1
At 05, the stuff is determined, the information is transferred to the STM timing generation circuit 102 to perform the destuffing process, and the write clock (WCK) is controlled.

As described above, according to this embodiment, the buffer memories are integrated into one, and the data rate conversion is performed collectively by one buffer memory. Since the scale can be reduced, the total buffer memory capacity can be reduced, and the transmission delay can be reduced.

Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 2 shows a main configuration of a data rate conversion device according to a second embodiment of the present invention.

In FIG. 2, reference numeral 201 denotes a FIFO;
Is a VC timing generation circuit, 203 is an STM timing generation circuit, 204 is a synthesis circuit, 205 is a stuff determination circuit, 206 and 207 are AND gates, 208 is an overhead generation circuit, 209 is a selector, 210 is a C-4 data input terminal, 211 is a C-4 clock input terminal;
2 is a C-4 frame pulse input terminal, 213 is an STM-
1 frame pulse input terminal, 214 is an STM-1 data output terminal, 215 is an STM-1 clock input terminal, 21
6 is a data rate converter. AND gate 206
Constitutes a VC clock generating means.

As shown in FIG. 2, C-4 data is input from the C-4 data input terminal 210 of the data rate converter 216. And a C-4 clock input terminal 211
The C-4 data is written to the FIFO 201 by using the input C-4 clock as the write clock (WCK) of the FIFO 201. Further, in the VC timing generation circuit 202, a pulse indicating a position for multiplexing the POH ( based on a C-4 frame pulse input from the C-4 frame pulse input terminal 212 and indicating a head position of the C-4 frame ). C data valid area signal (data
Valid)) is generated.

At the same time, the STM timing generation circuit 203
In ST, ST indicating the head position of the STM-1 frame input from the STM-1 frame pulse input terminal 213
On the basis of the M-1 frame pulse, a pulse (VC data valid area signal (data containing
)) Is generated. The generated pulses are combined by the combining circuit 204, and the AND gate 207 ANDs the STM-1 clock input from the STM-1 clock input terminal 215. Read the ANDed clock of FIFO 201 (RCK)
To read the data.

Next, the POH and SOH data generated in the overhead generation circuit 208 are
In the above, STM-1 data can be obtained by switching and multiplexing by the select signal supplied from the synthesis circuit 204. However, since the VC-4 frame (C-4 frame) and the STM-1 frame are asynchronous, the stuff determination circuit 205 monitors the FIFO accumulation amount in the FIFO 201, and if the stuff byte is required, the STM timing generation is performed. It is assumed that a stuff is requested from the circuit 203 to control the FIFO 201 read clock (RCK).

As described above, the data rate converter 21
6, the data rate conversion between C-4 and STM-1 can be performed.

The present invention is not limited to the above embodiment, but various modifications are possible based on the gist of the present invention, and these are not excluded from the scope of the present invention.

[0032]

As described above, according to the present invention, a plurality of rate conversion processes are collectively performed by one buffer memory, and a plurality of multiplexed low-order group signals are demultiplexed in the demultiplexing rate conversion. A plurality of timing generating circuits for generating respective effective area signals, and a means for synthesizing the respective effective area signals to generate a write clock for the buffer memory, or a plurality of A plurality of timing generating circuits for generating effective area signals indicating positions where each of the low-order group signals is to be multiplexed; and means for synthesizing the respective effective area signals and generating a read clock for the buffer memory. Therefore, when this rate conversion device is configured by an LSI,
The number of gates of the LSI can be significantly reduced, the cost and size of the device can be reduced, and the transmission delay of the signal buffer memory can be reduced.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram of a data rate conversion device according to a first embodiment of the present invention.

FIG. 2 is a schematic configuration diagram of a data rate conversion device according to a second embodiment of the present invention.

FIG. 3 is a schematic configuration diagram of a data rate conversion device in a first conventional example.

FIG. 4 is a schematic configuration diagram of a data rate conversion device in a second conventional example.

FIG. 5 is an STM-1 frame configuration diagram

[Explanation of symbols]

 Reference Signs List 101 FIFO 102 STM timing generation circuit 103 VC timing generation circuit 104 synthesis circuit 105 pointer processing / stuff judgment circuit 106 AND gate 107 AND gate 114 data rate conversion device 201 FIFO 202 VC timing generation circuit 203 STM timing generation circuit 204 synthesis circuit 205 stuff Judgment circuit 206 AND gate 207 AND gate 208 Overhead generation circuit 209 Selector 216 Data rate converter

────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Kiyoshi Uchimura 1006 Kazuma Kadoma, Kadoma City, Osaka Inside Matsushita Electric Industrial Co., Ltd. (56) References JP-A-6-141014 (JP, A) JP-A-6-141 244827 (JP, A) JP-A-4-287589 (JP, A) Table 7-503818 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04J 3/00 H04L 7 / 00

Claims (2)

(57) [Claims] 1. A demultiplexes the STM data multiple frames of asynchronous is multiplexed using a buffer memory C
(Container) A data rate converter that reproduces data, and includes a VC (virtual controller) together with stuff bytes.
Shows the staff judging means Tena) data to detect the presence or absence of stuff bytes in the STM data multiplexed, the multiplexed the portion corresponding to VC data into the STM data by the determination result of the stuff determination means VC
A first timing generating means for generating a data valid area signal, detects the pointer indicating the frame start position of the VC data, a pointer processor for generating a VC frame pulse indicating the VC frame start position, the VC data
C data indicating a VC clock generating means for generating a VC clock valid area signal and the STM clock, a portion in which the use of a VC clock, corresponding to the C data multiplexed to the STM data by the VC frame pulse
Comprising a second timing generating means for generating a data effective area signal, and a write clock generating means for the VC data valid region signal and said by synthesizing the C data valid region signal to generate a write clock of the buffer memory A data rate conversion device characterized by the above-mentioned. 2. C (container) using a buffer memory
Multiplexes data in VC (virtual container) data, comprising the VC data at the data rate converter for multiplexing the STM data together with stuff bytes, the insertion request before Symbol stuff bytes monitors the storage amount of the buffer memory Determining means for performing, and fourth timing generating means for generating a stuff byte in accordance with the determination result of the determining means and generating a VC data valid area signal indicating a multiplexing position when multiplexing the VC data with the STM data; , and VC clock generating means for generating a VC clock and the VC data valid area signal and the STM clock, the VC black
And a C frame pulse indicating the start position of the C data
Multiplexes the C data with the VC data using
C data valid area signal indicating the multiplexing position at the time of
A third timing generating means; and a read clock generating means for combining the VC data valid area signal and the C data valid area signal to generate a read clock for the buffer memory. Data rate converter.