JP4021566B2 - Data memory device and data memory control method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data memory device and a data memory control method, and more particularly, to a data memory device and a data memory control method configured at low cost using a single port memory.
[0002]
[Prior art]
In general, an exchange and a transmission apparatus have a function unit that requires a large-capacity main signal buffer, and it is required to configure such a function unit at low cost. For example, in the non-instantaneous switching function, when absorbing a transmission path length difference of 600 km, for example, a main signal buffer for at least 26 frames is required. Here, in the case of a virtual container-3 (VC-3) signal, one frame is composed of 783 bytes (87 bytes × 9 rows). Conventionally, such a large-capacity buffer is generally constituted by a dual port random access memory (DPRAM).
[0003]
FIG. 19 shows a configuration diagram of a main signal buffer using a conventional DPRAM.
[0004]
The conventional main signal buffer includes a DPRAM 101, a write side frame counter 102, a write side address control unit 103, a read side frame counter 104, and a read side address control unit 105. The data input to the main signal buffer is written into the DPRAM 101 at the address specified by the write side address control unit 103 based on the counter value by the write side frame counter 102. On the other hand, the data stored in the DPRAM 101 is read from the DPRAM 101 at an address specified by the read side address control unit 104 based on the counter value by the read side frame counter 105.
[0005]
As described above, conventionally, a large-capacity main signal buffer is configured using a DPRAM, and this is mainly due to the following reasons. That is,
The write address control unit 103 and the read address control unit 105 can independently control the write address and the read address to the DPRAM 101, so that the circuit configuration for address control is easy.
If the data throughput is the same, there is no problem even if the clock frequency on the writing side and the clock frequency on the reading side are different.
It is.
[0006]
[Problems to be solved by the invention]
As described above, conventionally, a large-capacity main signal buffer is generally composed of a DPRAM, and thus is very expensive. In view of the above, an object of the present invention is to construct a large-capacity main signal data buffer at low cost by using an inexpensive single port RAM (SPRAM).
[0007]
Another object of the present invention is to output the separated data so that the phase difference between them does not become excessive before and after the input data group is separated in parallel.
[0008]
[Means for Solving the Problems]
In the present invention, an inexpensive large-capacity main signal buffer unit is configured by using SPRAM. Since the SPRAM performs data writing and reading at the same port, it cannot perform writing and reading simultaneously. Therefore, in the present invention, a main signal buffer using SPRAM is realized by alternately performing writing and reading.
[0009]
According to the first solution of the present invention,
A parallel separation circuit that separates the input data group into parallel data;
A pointer detection circuit for detecting a pointer indicating a head position of the data group;
A single port memory for storing the parallel data in parallel at equal addresses,
A write side gate for inputting the parallel data to the single port memory;
A read side gate for reading the parallel data stored in the single port memory;
A multiplexing circuit that multiplexes the parallel data output from the read side gate into serial data;
An address control unit for controlling the parallel separation circuit, the single port memory, the write side gate, the read side gate, and the multiplexing circuit;
The address control unit
A control for adding at least one empty bit or other data to an odd number of data included in the data group by the parallel separation circuit and separating the parallel data as an even number of data;
The write side gate is turned on, and the parallel data is written in parallel to the single port memory from the start position of the data group according to the pointer detected by the pointer detection circuit;
The read side gate is turned on, and the parallel data is read from the single port memory; and
Control to multiplex and output the parallel data read from the single port memory by the multiplexing circuit
A data memory device is provided.
[0010]
According to the second solution of the present invention,
A data memory control method for inputting / outputting an input data group by a single port memory,
A function of adding at least one vacant bit or other data to an odd number of data included in the data group and separating it into parallel data;
A function of detecting a pointer indicating the head position of the data group;
The write side gate is turned on, and the parallel data is stored in parallel in the single port memory at the same address from the start position of the data group according to the pointer detected by the pointer detection circuit. The ability to write,
A function of turning on the read side gate and reading the parallel data from the single port memory;
A function of multiplexing and outputting the parallel data read from the single port to serial data
A data memory control method is provided.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 shows a schematic configuration diagram of a data memory device according to the present invention. FIG. 2 shows a time chart of the data memory device according to the present invention. The illustrated data memory device shows a main signal buffer as an example.
[0012]
The main signal buffer according to the present invention includes an SPRAM 1, an address control unit 2, a write side gate 3, and a read side gate 4. At the time of data input, the address control unit 2 turns on the write side gate 3 by a data input enable (/ DiEN) (here, “/” represents inversion. The same applies hereinafter), and the SPRAM 1 is also turned on. Writing is enabled by write enable (/ WE), and an address is designated by address designation (A). The data input to the main signal buffer is input to the data input / output (D) of the SPRAM 1 through the write side gate 3. On the other hand, when reading data, the address control unit 2 turns on the read side gate 4 with the data output enable (/ DoEN) and enables the SPRAM 1 to be read with the output enable (/ OE). Specify the address. The data stored in the SPRAM 1 is output from the D terminal via the reading side gate 4. Note that an output circuit 5 can be appropriately provided at the output terminal to adjust the output timing.
[0013]
In FIG. 2, as an example, when input data (DATA in) is input as Di (1) to Di (4), output data (DATA out) is expressed as Do (1) to Do (4). A timing chart when output is shown. Control of the SPRAM 1, that is, control by each terminal such as / DiEN, / DoEN, A, / WE, / OE, and D, is executed at a speed twice as high as the input / output data writing / reading speed.
[0014]
In the present invention, since data writing and reading are alternately performed, an access speed that is twice as high as that of the DPRAM system is required. Therefore, for example, the following method can be used for realizing the present invention. That is,
(A) A method of accessing the SPRAM at twice the speed of the DPRAM method, or
(B) A method of making the access speed to the SPRAM equal to that of the DPRAM method by developing two parallel write data to the SPRAM.
It is.
[0015]
If the speed of the device for realizing the memory control circuit is sufficient, the method (a) can be adopted. In general, however, the SPRAM control signal needs to have a resolution of about 1/4 of the access period. Therefore, the method (a) requires a device that operates at a clock speed four times the access speed.
[0016]
However, when the (a) method is difficult in terms of device capability, the (b) method can be used. FIG. 3 shows a configuration diagram of a data memory device according to the present invention. FIG. 3 shows, as an example, a main signal buffer configuration of (b) system, that is, a configuration diagram of a main signal buffer in which two write data to SPRAM are developed in parallel.
[0017]
The main signal buffer according to the present invention includes an SPRAM 11, an address control unit 12, a write side gate 13, a read side gate 14, a write side frame counter 15, a read side frame counter 16, a pointer detection circuit 17, and two parallel separation circuits 18 and 2. A multiplexing circuit 19 is provided.
[0018]
At the time of data input, the address control unit 12 turns on the write side gate 3 by the data input enable (/ DiEN) based on the count value of the write side frame counter 15 and writes the SPRAM 11 to the write enable (/ WE). ) Can be written, and the address is designated by address designation (A). The data input to the main signal buffer is input to the data input / output (D) of the SPRAM 11 through the write side gate 13. On the other hand, when reading data, the address control unit 12 turns on the read-side gate 14 by data output enable (/ DoEN) based on the count value of the read-side frame counter 16 and also enables the SPRAM 11 to output enable. Reading is possible by (/ OE), and an address is designated by address designation (A). The data stored in the SPRAM 11 is output from the data input / output (D) through the read side gate 4.
[0019]
The pointer detection circuit 17 detects a pointer indicating the head position of the input data group from the value of the write side frame counter 15 and notifies the address control unit 12 of it. Under the control of the address control unit 12, the 2-parallel separation circuit 18 converts, for example, 8 parallel inputs into 16 parallel outputs, and separates input data into 2 parallel data. Further, the 2-parallel separation circuit 18 can also include a parity line arithmetic circuit, and in that case, parity can be inserted into an empty bit position of the SPRAM 11. The 2-multiplex circuit 19 multiplexes the parallel data output from the read-side gate 14 into serial data and adjusts the output timing under the control of the address control unit 12. The 2-multiplex circuit 19 includes a buffer memory, and has, for example, a function as a buffer that aligns phases corresponding to phase fluctuations, and a function that skips and outputs empty bits or parity under the control of the address control unit 12.
[0020]
Further, the address control unit 12 controls the two parallel separation circuit 18 to add at least one empty bit or other data to the odd number of data included in the data group to separate the data into two parallel data. Further, the write side gate 13 is turned on, and parallel data is controlled to be written to the single port memory 11 from the head position of the data group detected by the pointer detection circuit 17. On the other hand, the read side gate 14 is turned on, and parallel data is controlled to be read from the single port memory 11.
[0021]
Next, an example will be described in which such a method (b) is applied to a VC-3 / 4 signal buffer in the Synchronous Digital Hierarchy (SDH) format. First, FIG. 4 shows an explanatory diagram of the SDH format. This figure shows, as an example, a frame structure in which three VC-3s are multiplexed on a synchronous transport module level-1 (STM-1) of a 155.52 Mbit / sec interface. ing.
[0022]
In STM-1, the section overhead including the pointer (Section Over Head, SOH) has a configuration of 9 bytes × 9 rows, and the payload has a configuration of 261 bytes × 9 rows. In VC-3, the path overhead (Path Over Head, POH) is 1 byte × 9 lines, and the payload is 86 bytes × 9 lines. Accordingly, one frame of VC-3 includes data # J1, # 2 to # 783.
[0023]
In this embodiment, as an example, the main signal buffer allows only the VC-3 signal to pass through, so that the range to be written into the SPRAM is only VC-3. However, since VC-3 is an odd number of 783 bytes, a timing shift occurs for each frame in the 2-parallel expansion, and thus it is difficult to adapt to the 2-parallel expansion system as described above (b). Therefore, in the present invention, an even number of data is obtained by inserting empty bits or other data (parity or the like).
[0024]
Hereinafter, the embodiment will be described focusing on one VC-3 in the STM-1 frame.
[0025]
FIG. 5 is an explanatory diagram of the storage area of the SPRAM.
[0026]
The SPRAM 11 stores parallel data in parallel at equal addresses. As illustrated, in this example, 8-bit input data # J1 and # 2 are stored at a 16-bit address 0 position. Similarly, at the address where the data is sequentially stored and the final data # 783 of one frame is stored, the previous 8 bits are data of # 783, and the subsequent 8 bits are vacant bits or parity bits are inserted. . Examples of the parity bit include BIP-8 (Bit Interleaved Parity 8).
[0027]
In addition, since the SOH input / output timing (SOH timing) is not written to and read from the memory, the present invention makes it possible to absorb the timing difference of the payload by using this SOH timing. Further, in the SDH frame, the number of data in the STM-0 payload may be 782 or 784 bytes due to justification. Therefore, in the present invention, the absorption of this number of data can be performed using the SOH timing.
[0028]
FIG. 6 is an explanatory diagram of the write and read ranges during justification. FIG. 6A shows a writing range in the case of positive justification (PJ). In this case, the pointer interrupts the payload as shown. On the other hand, FIG. 6B shows a writing range in the case of negative justification (NJ). In this case, the pointer is interrupted from the payload.
[0029]
Next, a time chart of the two parallel development units in the present invention will be described. In the present invention, the address controller 12 mainly monitors the data phase before two parallel expansion and the data phase after expansion at the boundary between a certain frame and the next frame, that is, when straddling the SOH timing, The control is performed so that the phase is approached when the phase is approached and is approached when the phase is separated, so that the data phase before and after the two parallel developments is kept within a certain range.
[0030]
First, FIGS. 7 to 9 show time charts of the two parallel development units at the boundary of VC-3.
[0031]
FIG. 7 shows a case where the phase difference before and after the two parallel developments is 3 bytes. In the figure, “input data before two parallel development” indicates data input to the main signal buffer. Here, with respect to the frame boundary of VC-3, it is indicated that the data up to the input data # 783 of the previous frame and the input data # J1 of the next frame have been input. “2 parallel data” in the figure indicates data separated in two parallels by the two parallel separation circuit 18 in accordance with the address control unit 12 in FIG. 3, and simultaneously indicates write and read data of the SPRAM 11. Here, input data # 779 and # 780 are in parallel, and similarly, # 781 and # 782, # 783 and BIP-8 are in parallel. BIP-8 may be an empty byte. The head data # J1 and # 2 of the next frame are aligned in parallel by BIP-8 or empty bytes. At this time, the input data # 779 is written into the SPRAM 11 with a phase difference of 3 bytes, and the input data # 780 is also written at that position. Also, the input data # J1 of the next frame is written into the SPRAM 11 with a phase difference of 6 bytes, delayed by the amount of insertion of BIP-8 or an empty byte, and the input data # 2 is also written at that position. Is included. According to the address control unit 12, reading is also performed at the same timing and phase difference as shown in “2 parallel data” in the figure. At this time, the write and read timings can be executed as shown in the time chart of FIG.
[0032]
Next, “output data after two separations” in the figure indicates data after the data output from the SPRAM 11 is multiplexed by the two multiplexing circuit 19 in accordance with the address control unit 12. In this example, data # 779 read from the SPRAM 11 is output by the 2 multiplexing circuit 19 with a phase difference of 12 bytes. Also, the BIP-8 or empty byte inserted earlier is removed by the 2 multiplex circuit 19. Data # J1 is output with a phase difference of 9 bytes.
[0033]
FIG. 8 shows a case where the phase difference before and after the two parallel developments is 6 bytes. At this time, as “2 parallel data”, the input data # 781 is written in the SPRAM 11 with a phase difference of 6 bytes, and the input data # 782 is also written at that position. The input data # J1 of the next frame is written into the SPRAM 11 with a phase difference of 9 bytes with a delay of 3 bytes, and the input data # 2 is also written at that position. Reading is also performed at the same timing and phase difference. Next, as “output data after 2 separation”, the data # 781 read from the SPRAM 11 is output by the 2-multiplex circuit 19 with a phase difference of 9 bytes. Data # J1 is output with a phase difference of 6 bytes.
[0034]
FIG. 9 shows a case where the phase difference before and after the two parallel developments is 9 bytes. At this time, as “2 parallel data”, the input data # 779 is written into the SPRAM 11 with a phase difference of 9 bytes, and the input data # 782 is also written at that position. The input data # J1 of the next frame is written into the SPRAM 11 with a 12-byte phase difference, and the input data # 2 is written at that position. Reading is also performed at the same timing and phase difference. Next, as “output data after 2 separation”, data # 779 read from the SPRAM 11 is output by the 2 multiplexing circuit 19 with a phase difference of 6 bytes. Data # J1 is output with a 3-byte phase difference.
[0035]
In such a system, the phase difference before and after the two parallel separations may increase due to BIP-8 or empty bytes. That is, in the above example, the phase difference of 3, 6, 9 bytes in the previous frame was added to 3 bytes in the next frame, resulting in a phase difference of 6, 9, 12 bytes. . In this example, this delay amount may be accumulated in subsequent frames. Therefore, another embodiment in which the delay amount is not added and accumulated by using SOH timing will be described below.
[0036]
10 to 12 show time charts of 2-parallel development at the SOH timing.
[0037]
FIG. 10 shows a case where the phase difference before and after the two parallel developments is 6 bytes. In the figure, “input data before two parallel development” indicates data input to the main signal buffer. Here, a case where SOH is input between frames # 6 and # 7 is shown (see the shaded area). As for SOH, as an example, the input main signal data is processed after the pointer conversion into the in-device phase in its own device, and the timing position of the input / output data is fixed before and after the two parallel separation circuit 18. Shall be.
[0038]
As for “2 parallel data”, here, the input data # J1 and # 3 are written into the SPRAM 11 with a phase difference of 3 bytes, and the input data # 2 and # 4 are also written at the respective positions. When the SOH is input, the address control unit 12 recognizes it using the write frame counter 15. The address controller 12 monitors the phase difference before and after the 2 parallel separation circuit 18 and outputs 3 bytes of SOH as it is because it is less than 9 bytes. Here, since SOH is 3 bytes, 4 bytes are written into the SPRAM 11 by resting 1 byte of writing or inserting other data of 1 byte. In addition, when this difference is 9 bytes or more, the address control unit 12 performs a process of deleting the SOH as will be described later. Also, since the SOH timing is fixed here, SOH is written after input data # 3 and # 4, and thereafter input data # 5 and # 6 and thereafter are sequentially written. The input data # 7 after the SOH is input is written into the SPRAM 11 with a phase difference of 9 bytes, and the input data # 8 is also written at that position. According to the address control unit 12, reading is also performed at the same timing and phase difference.
[0039]
Next, as “output data after 2 separation”, the data # J1 read from the SPRAM 11 is output from the 2-multiplex circuit 19 with a phase difference of 9 bytes. Next, as for the SOH, the inserted empty byte or BIP-8 is discarded, and the original 3 bytes are output at a fixed SOH timing. Since the position of SOH is fixed after data # 2, it is sequentially output thereafter. Input data # 5 written / read after SOH is output with a phase difference of 6 bytes.
[0040]
Next, FIG. 11 shows a case where the phase difference before and after the two parallel developments is 9 bytes.
[0041]
At this time, as “2 parallel data”, the input data # 3 is written into the SPRAM 11 with a phase difference of 9 bytes. The SOH is written at a fixed position, but the address controller 12 recognizes that the 2 parallel data has been written to the SPRAM 11 with a phase difference of 9 bytes by the 2 parallel separation circuit 18, and the phase difference is In order to prevent it from becoming excessive, a process of reading and discarding one byte of SOH is performed. Here, an empty byte or BIP-8 or the like for making an even number at the frame boundary of VC-3 is added, and if the phase difference is already 9 bytes, there is a possibility of further delay by 3 bytes. Therefore, as an example, in order to make the phase difference equal to or less than 12 bytes, when the phase difference before and after the two parallel separations is already 9 bytes, such SOH discard processing is performed. Next, input data # 5 and subsequent data are sequentially written. The input data # 9 is not so delayed because of the SOH read-out process, and writing is performed with a phase difference of 6 bytes. Reading is also performed at the same timing and phase difference.
[0042]
Next, as “output data after 2 separation”, the data # J1 read from the SPRAM 11 is output by the 2-multiplex circuit 19 with a phase difference of 6 bytes. In addition, appropriate data (such as empty bits) for 1 byte is inserted into the SOH, and 3 bytes are output at a fixed SOH timing. Input data # 7 written / read after SOH is output with a phase difference of 9 bytes.
[0043]
Next, FIG. 12 shows a case where the phase difference before and after the two parallel developments is 12 bytes.
[0044]
At this time, as “2 parallel data”, the input data # J1 is written into the SPRAM 11 with a phase difference of 12 bytes, and the input data # 2 is also written at that position. Further, SOH is written next, but since the phase difference is large, the SOH is discarded as described above. Thereafter, input data # 3 and subsequent data are written. Input data # 7 input after SOH is written into the SPRAM 11 with a phase difference of 9 bytes. Reading is also performed at the same timing and phase difference.
[0045]
Next, as “output data after 2 separation”, the data # J1 read from the SPRAM 11 is output by the 2-multiplex circuit 19 with a phase difference of 3 bytes. In addition, as described above, SOH is output. Data # 7 after the SOH timing is output with a phase difference of 6 bytes.
[0046]
As described above, the SOH timing can be used to control the phase difference before and after the two parallel developments from becoming excessive.
[0047]
Next, two parallel developments when there is a pointer justification instruction as shown in FIG. 6 will be described. 13 to 15 show time charts of 2-parallel development at NJ.
[0048]
FIG. 13 shows a case where the phase difference before and after the two parallel developments is 6 bytes. “Input data before 2-parallel expansion” indicates data input to the main signal buffer. Here, a case where SOH is input between frames # 6 and # 7 is shown.
[0049]
As for “2 parallel data”, here, the input data # J1 and # 3 are written into the SPRAM 11 with a phase difference of 3 bytes, and the input data # 2 and # 4 are also written at the respective positions. When the SOH is input, the address control unit 12 recognizes it by the write frame counter 15 and also recognizes the NJ time by the pointer detection circuit 17. At the time of NJ, since SOH is an even number of 2 bytes, it is separated into 2 parallels and written to SPRAM 11 as it is. As for SOH, here, as an example, the case where the timing positions of input / output data are fixed before and after the two parallel separation circuit 18 is shown as described above. Therefore, SOH data is written after input data # 3 and # 4, and thereafter, input data # 5 and # 6 and thereafter are sequentially written. The input data # 7 after the SOH is input is written into the SPRAM 11 with a phase difference of 6 bytes, and the input data # 8 is also written at that position. Further, according to the address control unit 12, reading is performed at the same timing and phase difference.
[0050]
Next, “output data after two separations” outputs the SOH output from the SPRAM 11 as it is for two bytes. In this example, data # J1 read from the SPRAM 11 is output by the 2-multiplex circuit 19 with a phase difference of 9 bytes. Also, SOH is output at SOH timing for 2 bytes. Since the position of SOH is fixed after data # 5, it is sequentially output thereafter. Input data # 5 written / read after the SOH data is output with a phase difference of 9 bytes.
[0051]
Next, FIG. 14 shows a case where the phase difference before and after the two parallel developments is 9 bytes.
[0052]
At this time, as “2 parallel data”, the input data # J1 is written in the SPRAM 11 with a phase difference of 9 bytes. Similarly, the SOH is written at a fixed position, but the address control unit 12 recognizes that the SOH is 2 bytes at the time of NJ. Next, input data # 5 and subsequent data are sequentially written. Input data # 9 is written with a phase difference of 9 bytes. Reading is also performed at the same timing and phase difference.
[0053]
Next, as “output data after 2 separation”, data # J1 read from the SPRAM 11 is output with a phase difference of 6 bytes. After the SOH is output at the fixed position, the input data # 3 and # 4 input before the SOH are output. Input data # 7 written / read after SOH is output with a phase difference of 6 bytes.
[0054]
Next, FIG. 15 shows a case where the phase difference before and after the two parallel developments is 12 bytes.
[0055]
At this time, similarly, as “2 parallel data”, the input data # J1 is written into the SPRAM 11 with a phase difference of 12 bytes, and the input data # 2 is also written at that position. Next, SOH is written in a fixed position, and thereafter input data # 3 and subsequent data are written. Input data # 7 input after SOH is written into the SPRAM 11 with a phase difference of 12 bytes. Reading is also performed at the same timing and phase difference.
[0056]
Next, as “output data after 2 separation”, data # J1 read from the SPRAM 11 is output with a phase difference of 3 bytes. Data # 5 is output with a phase difference of 3 bytes.
[0057]
Next, FIGS. 16 to 18 show time charts of 2-parallel development at the time of PJ.
[0058]
FIG. 16 shows a case where the phase difference before and after the two parallel developments is 6 bytes. “Input data before 2-parallel expansion” indicates data input to the main signal buffer. Here, a case where SOH is input between frames # 6 and # 7 is shown.
[0059]
As for “2 parallel data”, here, the input data # J1 and # 3 are written into the SPRAM 11 with a phase difference of 6 bytes, and the input data # 2 and # 4 are also written at the respective positions. When SOH is input, the address control unit 12 recognizes it by the write frame counter 15 and recognizes that it is PJ time by the pointer detection circuit 17. At the time of PJ, since SOH is an even number of 4 bytes, it is separated into two parallels and written to SPRAM 11 as it is. Regarding SOH, as an example, the timing position of input / output data is fixed before and after the two parallel separation circuit 18. Therefore, SOH data is written after input data # 3 and # 4, and thereafter, input data # 5 and # 6 and thereafter are sequentially written. The input data # 7 after the SOH is input is written into the SPRAM 11 with a phase difference of 6 bytes, and the input data # 8 is also written at that position. Further, according to the address control unit 12, reading is performed at the same timing and phase difference.
[0060]
Next, for “output data after 2 separation”, the SOH output from the SPRAM 11 is output as it is for 4 bytes. In this example, data # J1 read from the SPRAM 11 is output by the 2-multiplex circuit 19 with a phase difference of 9 bytes. Also, SOH is output at SOH timing for 4 bytes. Since the position of SOH is fixed after data # 5, it is sequentially output thereafter. Here, the input data # 5 written / read after the SOH data is output with a phase difference of 9 bytes.
[0061]
Next, FIG. 17 shows a case where the phase difference before and after the two parallel developments is 9 bytes.
[0062]
At this time, as “2 parallel data”, the input data # J1 is written in the SPRAM 11 with a phase difference of 9 bytes. Similarly, the SOH is written at a fixed position, but the address control unit 12 recognizes that the SOH is 4 bytes at the time of PJ. Next, input data # 5 and subsequent data are sequentially written. Input data # 9 is written with a phase difference of 9 bytes. Reading is also performed at the same timing and phase difference.
[0063]
Next, as “output data after 2 separation”, data # J1 read from the SPRAM 11 is output with a phase difference of 6 bytes. After the SOH is output at the fixed position, the input data # 3 and # 4 input before the SOH are output. Input data # 5 written / read after SOH is output with a phase difference of 6 bytes.
[0064]
Next, FIG. 18 shows a case where the phase difference before and after the two parallel developments is 12 bytes.
[0065]
At this time, similarly, as “2 parallel data”, the input data # J1 is written into the SPRAM 11 with a phase difference of 12 bytes, and the input data # 2 is also written at that position. Next, 4 bytes of SOH are written in a fixed position, and thereafter input data # 3 and subsequent data are written. Input data # 7 input after SOH is written into the SPRAM 11 with a phase difference of 12 bytes. Reading is also performed at the same timing and phase difference.
[0066]
Next, as “output data after 2 separation”, data # J1 read from the SPRAM 11 is output with a phase difference of 3 bytes. Further, data # 5 after SOH is output with a phase difference of 3 bytes.
[0067]
Although the embodiment has been described above, the present invention is not limited to this, and includes various improvements and changes. For example, the present invention can be applied not only to the main signal buffer but also to any data memory device. The storage area of the input data and SPRAM is not limited to 8 bits or 16 bits, respectively, and an appropriate number of bits can be used. The parallel separation is not limited to two parallel expansions, and can be expanded to a plurality of even-numbered parallel data. In addition to the frame formats such as VC-3 and STM-0, the present invention can be applied to various data groups. Furthermore, as a reference for discarding / deleting SOH, etc., a phase difference of 9 bytes or more is obtained before and after 2-parallel development.
[0068]
【The invention's effect】
As described above, according to the present invention, a large-capacity main signal data buffer can be configured at low cost by using inexpensive SPRAM.
[0069]
Also, according to the present invention, before and after the input data group is separated in parallel, the separated data can be output so that the phase difference between them does not become excessive.
[0070]
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram of a data memory device according to the present invention.
FIG. 2 is a time chart of the data memory device according to the present invention.
FIG. 3 is a configuration diagram of a data memory device according to the present invention.
FIG. 4 is an explanatory diagram of an SDH format.
FIG. 5 is an explanatory diagram of a storage area of an SPRAM.
FIG. 6 is an explanatory diagram of a write and read range during justification.
FIG. 7 is a time chart (phase difference: 3 bytes) of two parallel expansion units at the boundary of VC-3.
FIG. 8 is a time chart (phase difference: 6 bytes) of two parallel development units at the boundary of VC-3.
FIG. 9 is a time chart of the two parallel development units at the boundary of VC-3 (phase difference: 9 bytes).
FIG. 10 is a time chart of two parallel developments at SOH timing (phase difference of 6 bytes).
FIG. 11 is a time chart of two parallel developments at SOH timing (phase difference 9 bytes).
FIG. 12 is a time chart of two parallel developments at SOH timing (phase difference 12 bytes).
FIG. 13 is a time chart of 2-parallel development at NJ (phase difference 6 bytes).
FIG. 14 is a time chart of two parallel developments at NJ (phase difference 9 bytes).
FIG. 15 is a time chart of two parallel developments during NJ (phase difference 12 bytes).
FIG. 16 is a time chart of 2-parallel development at PJ (phase difference 6 bytes).
FIG. 17 is a time chart of two parallel developments during PJ (phase difference 9 bytes).
FIG. 18 is a time chart of two parallel developments during PJ (phase difference 12 bytes).
FIG. 19 is a configuration diagram of a main signal buffer using a conventional DPRAM.
[Explanation of symbols]
11 SPRAM
12 Address control unit
13 Write side gate
14 Reading side gate
15 Write side frame counter
16 Reading side frame counter
17 Pointer detection circuit
18 2 parallel separation circuit
19 2 Multiplex circuit 19

Claims (11)

A parallel separation circuit that separates the input data group into parallel data;
A pointer detection circuit for detecting a pointer indicating a head position of the data group;
A single-port memory for storing the parallel data input from the data input / output terminals in parallel at equal addresses,
A write side gate for inputting the parallel data to the data input / output terminal of the single port memory;
A read side gate for reading the parallel data stored in the single port memory from the data input / output terminal of the single port memory ;
A multiplexing circuit that multiplexes the parallel data output from the read side gate into serial data;
An address control unit for controlling the parallel separation circuit, the single port memory, the write side gate, the read side gate, and the multiplexing circuit;
The address control unit
A control for adding at least one empty bit or other data to an odd number of data included in the data group by the parallel separation circuit and separating the parallel data as an even number of data;
The write side gate is turned on and the single port memory can be written , the parallel data is input to the data input / output terminal of the single port memory, and the data is detected according to the pointer detected by the pointer detection circuit. A control for writing the parallel data in parallel to each of the same addresses from the head position of the group to the single port memory;
A control for turning on the read-side gate and enabling the single-port memory to be read, and reading the parallel data at the address from the single-port memory through the data input / output terminal in accordance with an indicated address ;
A data memory device that performs control such that the parallel data read from the single port memory via the data input / output terminal is multiplexed and output by the multiplexing circuit to serial data . The parallel separation circuit includes a parity operation circuit,
The data memory device according to claim 1, wherein a parity calculated by the parity calculation circuit is inserted as the other data. The multiplexing circuit is:
A function that aligns phases in response to phase fluctuations,
3. The data memory device according to claim 1, further comprising a function of skipping and outputting the empty bits or other data added by the parallel separation circuit under the control of the address control unit. . The address control unit
Based on the count value of the writing side frame counter, it is recognized that the input data is overhead,
The overhead including an odd number of data is written to the single port memory in parallel as an even number of data by resting the writing for one data or inserting other data by the parallel separation circuit. The data memory device according to claim 1, wherein the data memory device is a data memory device. The overhead input and output timings are fixed,
The data included in the data group is written and read by the single-port memory and output from the multiplexing circuit at a timing other than the overhead timing. A data memory device as described. The address control unit
Based on the count value of the writing side frame counter, it is recognized that the input data is overhead,
By monitoring the phase difference before and after the parallel separation circuit, if the phase difference is less than a predetermined byte, the overhead is separated as parallel data, and writing of one data is suspended or other data is inserted The parallel separation circuit outputs parallel data from the parallel separation circuit as an even number of data. On the other hand, if the phase difference is equal to or larger than a predetermined byte, at least one of the data included in the overhead is deleted and the parallel separation circuit is obtained as an even number of data. 6. The data memory device according to claim 1, wherein parallel data is output from the data storage device. The address control unit
Based on the count value of the writing side frame counter, it is recognized that the input data is overhead,
When the pointer detected by the pointer detection circuit recognizes that the data group is negative justification or positive justification, the parallel separation circuit converts the data into parallel data as an even number of data. 7. The data memory device according to claim 1, wherein the data memory device is separated and written to the single port memory. A data memory control method for inputting / outputting an input data group by a single port memory,
A function of adding at least one vacant bit or other data to an odd number of data included in the data group and separating it into parallel data as an even number of data ;
A function of detecting a pointer indicating the head position of the data group;
The write side gate is turned on and the single port memory can be written , the parallel data is input to the data input / output terminal of the single port memory, and the parallel data is started from the head position of the data group according to the detected pointer. A parallel write to the single port memory at the same address,
A function of turning on a read-side gate and enabling reading of the single-port memory, and reading the parallel data of the address from the single-port memory through the data input / output terminal according to an instructed address ;
A data memory control method comprising a function of multiplexing the parallel data read from the single port memory through the data input / output terminal and outputting the serial data. Based on the count value of the writing side frame counter, it is recognized that the input data is overhead,
The overhead is included in an odd number of data, and the overhead is written in parallel into the single port memory as an even number of data by resting one data write or inserting other data. 9. The data memory control method according to 8 . Based on the count value of the writing side frame counter, it is recognized that the input data is overhead,
The phase difference before and after the parallel separation is monitored, and if the phase difference is less than a predetermined byte, the overhead is separated as parallel data, and the writing of one data is interrupted or another data is inserted to Parallel data is output as a plurality of pieces of data, and on the other hand, when the phase difference is equal to or greater than a predetermined byte, at least one of the data included in the overhead is deleted and the parallel data is output as an even number of pieces of data. Item 10. The data memory control method according to Item 8 or 9 . Based on the count value of the writing side frame counter, it is recognized that the input data is overhead,
When the detected pointer recognizes that the data group is negative justification or positive justification, the overhead is separated into parallel data as an even number of data and written to the single port memory. 11. The data memory control method according to claim 8, wherein the data memory control method is performed.

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