JPH05292556A - Switch system and switching method - Google Patents

Abstract

PURPOSE:To realize a large-scale switch device without extending the circuit scale by shifting the frame phase of an input highway to divide the frame and adjusting the phase of a virtual container in the frame to prevent the extension of the delay time and the increase of the number of gates and performing the switching in every divided unit. CONSTITUTION:The frame subjected to parallel expansion from a reception part 11 is supplied to a phase control part 12 and is outputted to a space switch 13 based on the signal from a timing generating part 20. At this time, the phase difference between input and output is adjusted by a phase pointer in the frame of the virtual container to minimize the delay. Next, the space switch 13 is operated to perform parallel expansion and byte multiplexing, and the frame has bytes sliced by one byte and is transferred to a highway 4 in this state, and it is written in a DM 14 of a time switch and is read out as the address of an ACM 17 correspondingly to an output highway 7. A space switch 18 transforms the frame and sends it onto a prescribed highway.

Description

Detailed Description of the Invention

[0001]

The present invention relates to STM (Synchronous
Transfer Mode) The present invention relates to a switch system and a switch system used for a transmission device and an STM switch.

[0002]

2. Description of the Related Art A conventional time division type switch is disclosed in "Digital Communication Technology (p.247-251)" (Kimio Tanaka: ISBN4-486-00898-7 C3355, published by Tokai University Press). In the above-mentioned conventional technology, switching processing is realized by multiplexing all signals on the input highway, writing them to the data memory, controlling the reading order on the reading side of the data memory, and then separating them into output highway units. To do.

A method according to the above-mentioned known example is shown in FIG. In the conventional method shown in FIG. 11, the multiplexing unit 40 multiplexes frames on all input highways. Therefore,
When the number of input highways increases, the operating speed of the switch circuit increases. The upper limit of the operating speed is set depending on the device used for the switch circuit. In order to prevent the operation speed from increasing above the upper limit, a method of performing serial-parallel conversion on an input frame and then performing multiplex processing is generally used.

Here, the number of input highways is N (N is 2).
In the case of the above natural number), in order to keep the signal transmission speed on the input highway and the operation speed of the switch circuit at the same speed, the number of parallel expansions of the input frame on the input highway may be increased by N times. For example, if the number of parallel signals expanded on the input highway is 8 bits in parallel,
When the number of all input highways is N, if the parallel expansion number of each input frame is expanded to (8 × N) bits in parallel and then multiplexed, the signal transmission speed on the input highway and the operation speed of the switch circuit become the same. You can In FIG. 11, N =
6, the frame format on the highways 3-1 to 3-6 before multiplexing when the frame length = 12 bytes is shown in FIG. Name A on each frame on highways 3-1 to 3-6
Gave ~ F. In FIG. 12, A-1 indicates that it is the first time slot of frame A. Since the frame is expanded into 8 bits in parallel, one time slot corresponds to 1 byte.

FIG. 13 shows the frame format on the highways 4-1 to 4-6 after multiplexing. In FIG. 11, each reception unit receives a frame from each highway, detects the beginning of the frame, parallel-decomposes it into 8 bits, and outputs the parallel-decomposed frame to each frame phase control unit. Each frame phase control unit matches the phase at the beginning of the frame based on the reference signal from the timing generation unit 20 and outputs the combined phase to the multiplexing unit 40. In the multiplexing unit 40,
A frame having a format as shown in FIG. 12 is input from each frame phase control unit, temporarily stored in a storage unit such as a flip-flop for latching, and multiplexed into a frame having a format as shown in FIG. Is output. In this case, for example, the time when the time slot A-6 shown in FIG. 13 is output is later than the input time of the time slot A-6 shown in FIG. Since each frame is input to the data memory (DM) for storing the data of the frame and the switching is performed at the same time, FIG.
The frame shown in is input in synchronization with each DM. Therefore, at least after the input time of the time slot of A-6, the output of the time slots of A-1 to A-6 is performed, so that the time is delayed. The data of the input frame is sequentially written in each DM, and the data is read out in accordance with the address of the data memory indicated by the contents previously written in the address control memory. At this time, as the contents of the address control memory, the address of the data memory corresponding to the output highway is written. It is switched by being read out according to the contents of the address control memory, and is input to the separation unit 41. The demultiplexing unit 41 temporarily stores the data output from each DM in a storage unit such as a flip-flop for latching, and, contrary to the operation of the multiplexing unit, demultiplexes it into frames of the format shown in FIG. Then, each frame is output to each transmitting unit. Each transmission unit converts the data serially and outputs the data of each frame to each output highway.

[0006]

When the above processing is performed,
The multiplexer 40 shown in FIG. 11 requires (number of input highways × number of parallel expansions) latch flip-flops for parallel expansion processing. That is, as the number of input highways increases, the delay due to the latch of the multiplexing unit increases, and the number of gates required for the latch also increases. Further, this phenomenon also occurs in the separating unit 41. That is, in order to separate and output the output frames read from the memory in the multiplexed state into the output highways (the number of input highways ×
The number of parallel development) latch flip-flops is required.

An object of the present invention is to provide a large-scale switching device and a switching method without increasing the delay time and the circuit scale in the multiplexing unit and the demultiplexing unit necessary for the switching process.

[0008]

SUMMARY OF THE INVENTION The present invention, in a switch system for connecting a plurality of input highways and a plurality of output highways for switching, is provided corresponding to each input highway and sets the frame phase of the input highway. It has a phase control unit that shifts and outputs the phase instructed in advance, and a switch unit that switches a frame from each phase control unit to an output highway that is instructed in advance, and the switch unit has each phase. Using the phase difference of each frame from the control unit, a spatial switch that spatially switches for each time slot, a time switch that performs time slot replacement processing for the corresponding output highway, and a time slot after the replacement Space switch to switch to convert to input highway frame data Equipped with a. The input frame is
The phase control unit has a pointer generation unit for rewriting the information indicating the start position of the data portion of the input highway, and the pointer control unit is pre-specified. Phase,
By calculating the information indicating the start position of the data portion of the frame from the phase difference between the designated reference point and the frame of the input highway and rewriting the information indicating the start position of the data portion of the frame, the phase of the frame Shift.

Each of the pointer generators shifts the frame phase between input frames by M (M is a natural number) time slots.

The switching method of the above switch system is as follows.

The frame phase on the input highway is relatively shifted by M (M is a natural number and a divisor of P) time slots for each input highway, and the first N-input N-output spatial switches are used to shift the number of the N frames. The i-th (i is a natural number not less than 1 and not more than N) time slot block from the reference point of each input highway is the [[((i -1)
/ M}% N + 1] th (where {(i-1) / M}%
N + 1 controls to output the quotient obtained by subtracting 1 from i divided by M on the highway of (dividing by 1 and adding 1 too much), and then replaces the time slot for each highway unit. Perform processing.

After completion of the time slot exchange processing, the second
No. N input N output space switch, the j-th (j is a natural number not less than 1 and not more than N) time slot block from the reference point on each of the N input highways of the second N input N output space switch. Of the N output highways of the second N-input N-output space switch.
1) / M}% N + 1] th output is controlled to be output on the highway.

When the frame is composed of an overhead part and a data part, the means for relatively shifting the phases of the frames input from the input highway by M time slots respectively is provided for each of the frames on the N input highways. Write only the data part in the memory to the memory that uniquely corresponds to each highway, and then when reading the data part from the memory, the phase of the read frame on the N highways is relative by M bytes each. Read in the shifted state.

If the start position of the data portion in the frame can be set to an arbitrary position in the frame and the position can be indicated numerically by an indicator provided in the overhead, in order to shift the phases of the frames from each other. The means used is to first write only the data portion in each of the frames on the N input highways to the memory that uniquely corresponds to each highway, and then when reading the data portion from the memory, The read frame on the highway is read in a state in which the phase of each frame is relatively shifted by M time slots, and at that time, the value of the indicator indicating the start position of the data portion in the frame is recalculated and added to the read frame. To do.

The value of M may be 1. Further, when the frame length is P (P is a natural number) time slot, N may be a divisor of P.

The frame is CCITT Recommendation G.
It may be a frame defined in 709.

[0017]

Each phase control unit provided corresponding to each input highway shifts the frame phase of the input highway by the phase instructed in advance and outputs it. For example, the frame phases of the input frames are shifted by M time slots. At this time, the pointer generation unit of each phase control unit calculates information indicating the start position of the data portion of the frame from the phase amount previously designated and the phase difference between the designated reference point and the frame of the input highway. Then, the phase of the virtual container in the frame is adjusted by rewriting the information indicating the start position of the data portion of the frame (pointer attached to the input frame), and the increase in delay time is prevented.

Next, in the switch section, the first N input-
The N-output space switch outputs the i-th (i is a natural number of 1 or more and N or less) time slot block from the reference point of each of the N input highways to the N-th of the first N-input N-output space switches. Of the output highways of the book, the [{(i−1) / M}% N + 1] th (where {(i
(-1) / M}% N + 1 indicates that the quotient of i minus 1 divided by M is divided by N and 1 is added too.)
Control to output on the highway.

Next, the time switch performs a time slot interchange to a desired state on each highway by performing a time slot interchange process for the corresponding output highway.

Next, the second N-input N-output space switch is connected to the j-th (j is 1 or more and N or less) reference points on each of the N input highways of the second N-input N-output space switch. The (N natural number) timeslot block of the second N-input N-output spatial switch is output to the [{(j−1) / M}% N + 1] -th highway of the N output highways. To control.

By the above operation, the switching delay time and the circuit scale are suppressed.

[0022]

EXAMPLE A first example of the present invention will be described with reference to FIG. FIG. 1 is a switch system that connects six input highways to six output highways. Frames on each input highway have A, B, C, D, and
The names E and F will be given. In FIG. 1, each frame phase control unit is provided corresponding to each input highway, and outputs the frame phase of the input highway by shifting by a phase instructed in advance. In addition, the space switch 13
Is a first spatial switch, which spatially switches for each time slot by utilizing the phase difference of each frame from each phase control unit. The subsequent stage of the space switch 13 constitutes a time switch, and performs time slot interchange processing for the corresponding output highway. The time switch is a data memory 14-1 that stores the input data.
14-6, an address control memory for performing a switching process, a writing control unit for controlling writing of the data memory, and a reading control unit for controlling reading of the data memory. The space switch 18 is a second space switch, and switches to convert the exchanged time slot into the input highway frame data.

The structure of the frame used in this embodiment is shown in FIG. The frame shown in FIG. 2 includes an overhead part and a data part (hereinafter, referred to as a virtual container). The frame length is 12 bytes. The overhead is 3 bytes and the virtual container part is 9 bytes. Further, in this embodiment, since the frame from the input highway is expanded in 8 bits in parallel, one time slot corresponds to 1 byte. Since the frame configuration shown in FIG. 2 is an example, the frame length is P time slots (where P is a natural number), and the areas of the overhead portion and the virtual container portion can be arbitrarily determined.

The phase of the virtual container can be arbitrarily determined with respect to the overhead. That is, FIG.
By the pointer (1 byte) included in the overhead shown in, the number of bytes apart from the pointer at the beginning of the virtual container is displayed in binary. The pointer is information indicating the head position of the data portion of the frame of the input highway. For example, when the pointer and the head of the virtual container are separated by 10 bytes, 1 is set in the pointer.
A value of 0 (1010 in binary notation) is displayed. In addition, as shown in FIG. 3, a portion which does not fit in one frame is accommodated in the next frame. From the value indicated by this pointer, it is possible to know where the head of the virtual container of the frame, that is, the head of the actual data section, starts.

The frame shown in FIG. 2 is SDH (Synchronous) defined in CCITT Recommendation G.709 shown in FIG.
Digital Hierarchy) and ANSI SONE
This is a simplified T (Synchronous Optical Network) frame, and the present invention is considered to be applied to both.

In FIG. 1, the receiving units 11-1 to 11-6 first perform overhead termination processing such as frame synchronization and byte synchronization of received frames. By byte synchronization,
The head of the frame is detected, serial-parallel conversion is performed in the state where byte synchronization is established, the data is expanded in 8 bits in parallel, and the parallel expanded frame is output to each frame phase control unit.

Next, the operation of the frame phase control units 12-1 to 12-6 will be described with reference to FIG. FIG. 5 shows an internal circuit of each frame phase control unit shown in FIG. In FIG. 5, the frame phase control unit has a memory 30, a write control unit 31, a read control unit 32, a pointer generation unit 33, and a selector 34. The memory 30 stores the input frame data, the writing control unit 31 controls writing, and the reading control unit 32 controls reading. The write control unit 31 gives a write instruction based on the frame head signal and the clock from each receiving unit. The read control unit 32 performs read control based on the frame start signal and the clock reference signal from the read timing generation unit 20. The pointer generation unit 33 calculates information indicating the start position of the data portion of the frame from the phase amount previously designated and the phase difference between the designated reference point and the frame of the input highway,
The phase of the frame is shifted by rewriting the information indicating the start position of the data portion of the frame. Selector 34
Is a pointer generation unit 3 in the overhead area.
3 is selected, and when it is the area of the data section, the output from the memory is selected.

In the frame phase controller, only the virtual container portion in the frame on the input highway is required data, and the information of the overhead portion is not used. Therefore, in the memory 30, the write control unit 31
However, the information of the overhead portion is not written based on the frame head signal and clock from each receiving unit. Here, since the frame phase on the writing side of the memory 30 differs depending on the transmission path of the received frame, it becomes an arbitrary frame phase.

When reading from the memory 30, the phase of the head of the frame is matched and output to the spatial switch 13 based on the frame head signal from the timing generator 20 on the read side and the reference signal of the clock. The output is read from the memory 30 and output in accordance with the frame phase, and the output from the pointer generation unit 33 is selected by the selector 34 and output in the overhead portion. At this time, the phase of the output frame of each memory 30 inside each frame phase control unit is 1 time slot (or M time slot, where M is a natural number).
The timing generation unit 20 controls so as to shift each. Here, since the frame phase is different between the writing side and the reading side of each memory, the phase in the frame of each virtual container is adjusted using a pointer. The pointer generator 33 makes this adjustment. The pointer generator 33
The value of the received frame pointer is detected from the received frame data and the frame start signal. The value of the pointer is
Since there is almost no change other than fluctuations in the daily range or the year range, if a pointer of a predetermined number of frames is detected and if they are the same, the value is stored as a pointer value, and thereafter, the pointer is stored. The value can be used to rewrite the pointer. In addition, the pointer generator 33
The phase difference between the time of writing data to the memory and the time of reading data from the memory is detected, and the pointer value is newly written to the data output at the timing instructed by the timing generation unit 20. For example, in order to detect this phase difference, a pointer value is set in a down counter provided inside the pointer generation unit 33, and down counting is performed according to a clock until there is an indication of the head position of the frame from the reference point. Can be detected. Further, the pointer generation unit 33 is instructed by the timing generation unit 20 to shift the M time slot, and calculates the value of the pointer. That is, the pointer generation unit 33 determines the value of the pointer of the received frame data, the phase difference between the reference point and the received frame, and the number of time slots to shift from the reference point by M.
The position of the virtual container of the frame at the time of output is calculated from the time slot and written as a pointer value, and the overhead portion is added.

This state is shown in FIG. As shown in FIG.
Shows the input frame format to the frame phase control unit, and (b) shows the input frame format from the frame phase control unit. In FIG. 8, the head position of the frame of the highway 2-1 is used as a reference point, and the frames of the other highways have different transmission paths, and thus the phases thereof are deviated. In this case, the highway 2-2 is slid one time slot from the reference point, and the highway 2-2 is sequentially set to 1 for each highway.
Slide the time slot, highway 2-6 is 5
Time slot slides. By rewriting the value of the pointer in the frame phase control unit, the position of the virtual container on the highway 2-2 and the position of the virtual container on the highway 3-2 are deviated by a delay of the processing time required for rewriting the pointer. Just little delay. Although not shown in FIG. 8, since the frames are consecutive, for example, when the pointer value is smaller than M to shift the M time slots, the virtual container is stored in the previous frame and output. It Here, the value of the number of time slots to be slid from the reference point of the input highway should be a divisor of the frame length.

As described above, by writing the pointer value using the pointer generation unit 33, the virtual container can be accommodated at an arbitrary position within the frame, and as a result, the delay can be minimized and the frame phase can be controlled.

Next, the processing in the space switch 13 will be described.
Frame space switch on each input highway 3-1 to 3-6
The input format to 13 is shown in FIG. Space switch 13
Is a space switch with 6 inputs and 6 outputs. By operating this space switch, the frame on the output side is converted as shown in FIG. That is, the heads of the frames on the six input highways are used as reference points, and
The (i is a natural number of 1 or more and 12 or less) time slot is output to the [(i-1)% 6 + 1] th highway of the 6 output highways of the 6-input 6-output spatial switch. To control. For example, as shown in FIG.
Of the frames on the six input highways, the third time slot (A-
3) is the third highway of the 6 output highways of the 6-input 6-output space switch shown in FIG.
(4-3) Control to output to the first time slot from the reference point above (subtracting 1 from 3 and dividing by 6 and adding 1 to the remainder gives 3 so on the 3rd output highway Output). In addition, the first time slot (C-1) on the third highway shown in FIG. 6 is the first of the six output highways of the six-input, six-output spatial switch shown in FIG. Third from the reference point on the highway
Control to output to the th time slot. For example, the A-3 time slot shown in FIG. 6 is the third time slot from the reference point of the first highway, so the third time slot is the third time slot.
Output to the highway. Since C-1 is the first time slot of the third highway, it is output to the first highway.

By the above operation, the input frame is (8 ×
6) This means parallel development into bits and byte multiplexing. Moreover, in the above method, since the space switch is used for the multiplex operation instead of the shift register, the delay time is small and the number of gates is remarkably small.

Next, as shown in FIG. 7, the output of the space switch 13 is transferred to the highways 4-1 to 4-6 in a state where it is byte-sliced byte by byte, and the data is stored in the data memory of the time switch (hereinafter, DM). 14-1 to 14-6, respectively.

An address control memory (hereinafter referred to as an ACM) is attached to each DM, and the contents are all the same. Data of input frames is sequentially written in each DM. Since the input frame shifts by one clock for each highway, each DM also shifts by one clock and performs the same operation. That is, as shown in FIG. 6, when A-2 is written in DM14-2, DM14-
B-1 will be written in 1.

On the read side, data is read from DM according to the address value read from ACM. Data is read out in accordance with the address of the data memory indicated by the contents written in advance in the address control memory. At this time, as the contents of the address control memory, the address of the data memory corresponding to the output highway is written. It is switched by being read according to the contents of the address control memory. The state of the frame in this case is shown in FIG. Here, the reading order is F, E, D, C, B, and A.

In the above explanation of the principle, the data is sequentially written to the data memory, and the read control section reads the data from the data memory at random using the contents of the address control memory ( Although the sequential writing / random reading method) has been taken as an example, it can be applied to other methods. For example, by using the contents of the address control memory in the data memory by using the write counter value, the data is randomly written, and the data is sequentially read from the data memory (random write / serial It is also applicable to the sequential read method).
The operation is the same as the sequential writing / random reading method.

Then, in the space switch 18, the frame is deformed as shown in FIG. That is, the j-th (j is a natural number of 1 or more and N or less) time slot from the reference point on the input highway of the space switch 18 is the [(j-1)% of the 6 output highways of the space switch 18. 6 + 1]
Control to output on the second highway. For example, since A-3 is the first time slot of the third highway, it is output to the first highway. As a result,
Highways 6-1 to 6-6 have F, E, D, C, and
It can be seen that the frames B and A have appeared, and the switching operation has been completed.

By the above operation, switching is executed, overhead is inserted in the transmitting unit, and each frame is sent to the output highways 7-1 to 7-6.

Next, the second embodiment will be described with reference to FIGS.
This will be described with reference to FIGS. 16 and 17. In the second embodiment, the switch configuration is the same as the above-described embodiment, and N
The number of sliding time slots M (M is a natural number and N is a natural number greater than or equal to 2) is connected in a switch system in which N input highways are connected to N output highways and the frame length is P time slots (P is a natural number). The case where the divisor of P) is larger than 1 is shown. When the number of timeslots to be slid is larger than 1, for example, when the time slots are shifted by 2 timeslots, the input frame format from each frame phase control unit is, as shown in FIG. A-1, in order
A-2, ..., Is output, and B- is displayed on the highway 3-2.
, B-2, ..., Similarly, each frame is output with two time slots.

The output frame format from the space switch 13 is, as shown in FIG.
-1, A-1, A-2, B-1, B from the reference point in order
-2 ... is output every two time slots. Highway 4-2, two time slots later,
.. are output in order from the reference point, such as A-3, A-4, B-3, B-4 ..., and 2 time slots are output to the same highway.

In this case, the frame phase on the input highway is relatively shifted by M (M is a natural number and a divisor of P) time slots for each input highway, and the first N-input N-output spatial switch switches The i-th (i is a natural number not less than 1 and not more than N) time slot block from the reference point of each of the N input highways is designated as the [third] of the N output highways of the first N-input N-output spatial switch. {(I-1) / M}% N + 1] th (where {(i
-1) / M}% N + 1 controls to output the quotient obtained by dividing the value obtained by subtracting 1 from i by M and adding 1 to the remainder divided by N), and then outputs , Time slot replacement processing is performed for each highway.

For example, of the frames on the three input highways shown in FIG. 13, the first highway (3
-1) The third time slot (A-3) above is located on the second highway (4-2) of the three output highways of the three-input three-output spatial switch shown in FIG. The output is controlled to output from the reference point to the first time slot (the quotient obtained by subtracting 1 from 3 and dividing by 2 is divided by 3 and adding 1 to the remainder gives 2 so the second output highway Output above). In addition, the first time slot (C-1) on the third highway shown in FIG.
Among the three output highways of the three-input, three-output space switch shown in (3), control is performed so as to output from the reference point on the first highway to the fifth time slot.

The output of the space switch 13 is shown in FIG.
As shown in, the data is transferred to the highways 4-1 to 4-3 in a byte sliced state and written to the data memories 14-1 to 14-3 of the time switch, and each time slot is Replacement processing is performed on the corresponding output highway. As shown in FIG. 16 which shows an output frame format from the data memory, it operates similarly to the time switch of the above-mentioned embodiment.

Then, in the space switch 18, the frame is deformed as shown in FIG. That is, after the time slot replacement process is completed, the second N-input N-output space switch 18 causes the j-th (j is j) from the reference point on each of the N input highways of the second N-input N-output space switch. A natural number from 1 to N inclusive) th time slot block,
The output is controlled to be output on the [{(j-1) / M}% N + 1] th highway of the N output highways of the second N-input N-output spatial switch.

As described above, the space switch 13 and
Switching processing can be performed by the time switch and the space switch 18.

Here, the value of the number N of input highways should be a divisor of the frame length. Also, when the number of input highways is not a divisor of the frame length, it can be dealt with by inserting a dummy slot.

In the above two embodiments, since the space switch is used instead of the shift register for the separation operation,
The delay time is also small and the number of gates is much smaller.

As described above, the use of the space switch in the multiplexing unit and the demultiplexing unit prevents the delay and the increase in the number of gates.

In this description, the number of input highways and the number of output highways are set to 6 or 3 for the sake of simplicity, but in practice, any natural number of 2 or more is also possible.

Further, in this description, the frame length is set to 12 bytes for the sake of simplicity, but this can be any natural number.

Further, it is desirable that the number of input highways is a divisor of the frame length.

[0053]

According to the switching method of the present invention, it is possible to perform a switch process in which the signal delay time inside the switch is minimized, and a large capacity time switch with a small signal delay time can be constructed.

[Brief description of drawings]

FIG. 1 is a block diagram of a switch according to the present invention.

FIG. 2 is a frame format.

FIG. 3 is an explanatory diagram showing functions of pointers and mapping of virtual containers to frames.

FIG. 4 is a frame configuration diagram defined in CCITT recommendation G.709.

FIG. 5 is a configuration diagram of a frame phase control unit.

FIG. 6 shows an input frame format to the space switch 13.

FIG. 7 is an output frame format from the space switch 13.

FIG. 8 is a diagram showing the operation of a frame phase control unit.

FIG. 9 is an output frame format from the data memory.

FIG. 10 is an output frame format from the space switch 18.

FIG. 11 is a switch configuration diagram according to a conventional method.

FIG. 12 is an input frame format for a multiplexing unit.

FIG. 13 is an output frame format from the multiplexing unit.

FIG. 14 shows an input frame format to the space switch 13 in the second embodiment.

FIG. 15 is an output frame format from the space switch 13 in the second embodiment.

FIG. 16 is an output frame format from the data memory in the second embodiment.

FIG. 17 is an output frame format from the space switch 18 in the second embodiment.

[Explanation of symbols]

1-1 ・ 1-2 ・ ・ ・ 1-6 ・ ・ ・ Input highway 、 2-1 ・ 2-2 ・ ・ ・ 2
-6 ... Highway, 3-1, 3-2 ... 3-6 ... Highway, 4-1
・ 4-2 ・ ・ ・ 4-6 ... Highway 、 5-1 ・ 5-2 ・ ・ ・ 5-6 ... Highway 、 6-1 ・ 6-2 ・ ・ ・ 6-6 ・ ・ ・ Highway 、 7-1 ・ 7 -2
・ ・ ・ 7-6… Output highway, 11-1, 11-2 ・ ・ ・ 11-6…
Receiving unit, 12-1, 12-2 ... 12-6 ... Frame phase control unit,
13 ... Space switch, 14-1, 14-2 ... 14-6 ... Data memory, 15-1, 15-2 ... 15-6 ... Write controller, 16-1, 16-2.
..16-6 ... Read control unit, 17-1, 17-2 ... 17-6 ... Address control memory, 18 ... Space switch, 19-1, 19-2
・ ・ ・ 19-6 ... Transmitter, 20 ... Timing generator, 21-1, 21
-2 ... 21-6 ... Receive clock, 22-1, 22-2 ... 22-6 ...
Reception frame start signal, 23 ... Timing signal in the case of the conventional method, 23-1, 23-2 ... 23-6 ... Timing signal according to this patent, 30 ... Memory, 31 ... Write control unit, 32 ... Read control Part, 33 ... pointer generating part, 34 ... selector, 40 ... multiplexing part, 41
… Separation part.

Claims (10)

[Claims] 1. In a switch system for connecting a plurality of input highways and a plurality of output highways for switching, the frame phases of the input highways provided corresponding to the respective input highways are shifted by a predetermined phase. And a switch unit for switching a frame from each phase control unit to an output highway designated in advance, and the switch unit has a phase difference of each frame from each phase control unit. Using, the spatial switch that spatially switches for each time slot, the time switch that performs time slot replacement processing for the corresponding output highway, and the time slot after the conversion is converted to input highway frame data And a space switch for switching to Switch system. 2. The pointer according to claim 1, wherein the input frame includes information indicating a start position of a data portion of the frame, and each phase control unit rewrites information indicating a start position of a data portion of the input highway frame. The pointer generation unit calculates information indicating the start position of the data portion of the frame from the phase amount designated in advance and the phase difference between the designated reference point and the frame of the input highway. Then, the switch system is characterized in that the phase of the frame is shifted by rewriting the information indicating the start position of the data portion of the frame. 3. The pointer generation unit according to claim 2, wherein the respective pointer generators calculate a mutual frame phase between input frames by M.
(M is a natural number) A switch system characterized by shifting by time slots. 4. N (N is a natural number of 2 or more) input highways and N output highways are connected, and the frame length is P.
In a switching method of a switch system of time slots (P is a natural number), a frame phase on an input highway is relatively shifted by M (M is a natural number and a divisor of P) time slots for each input highway, and a first N An input N output space switch allows the i-th distance from the reference point of each of the N input highways.
The (i is a natural number greater than or equal to 1 and less than or equal to N) time slot block is the Nth space switch of the first N input N output.
[{(I-1) / M}% of the output highways of the book
N + 1] th (where {(i-1) / M}% N + 1
Controls the output of the quotient of i minus 1 divided by M on the highway (indicating that 1 is added too much divided by N). A switching method characterized by performing processing. 5. A reference on each of the N input highways of the second N-input N-output space switch by the second N-input N-output space switch after completion of the time slot interchange processing according to claim 4. The j-th time slot block (j is a natural number of 1 or more and N or less) from the point
Of the N input N output space switches of the above, the control method is such that the output is performed on the [{(j-1) / M}% N + 1] th highway of the N output highways. 6. The method according to claim 4 or 5, wherein when the frame is composed of an overhead portion and a data portion, the means for relatively shifting the phase of the frame input from the input highway by M time slots is used. Only the data portion in each of the frames on the input highway of the book is written to the memory that uniquely corresponds to each highway, and then when reading the data portion from the memory, the frame of the read frame on the N highways. The switching method is characterized in that the phase is read by shifting the phase of each by M bytes relatively. 7. The frame according to claim 6, wherein the start position of the data portion in the frame can be set to an arbitrary position in the frame, and the position can be indicated numerically by an indicator provided in the overhead. The means used to shift the mutual phase first writes only the data portion in each of the frames on the N input highways to a memory that uniquely corresponds to each highway, and then writes the data portion from the memory. When reading, the phases of the frames of the read frames on the N highways are shifted relative to each other by M time slots, and at this time, the value of the indicator indicating the start position of the data portion in the frame is reset. A switching method characterized by calculating and adding to a read frame. 8. The switching method according to claim 4, 5, 6 or 7, wherein the value of M is 1. 9. The method according to claim 3, 4, 5, 6 or 7.
A switching method, wherein N is a divisor of P when the frame length is P (P is a natural number) time slot. 10. A switching method according to claim 3, 4, 5, 6, 7 or 8, wherein said frame is a frame defined in CCITT Recommendation G.709.