JPH07162905A - Time division multiplex switch - Google Patents

Abstract

PURPOSE:To provide the time division multiplex time switch composed of T1 steps by constituting the hardware which does not accelerate memory speed and further is not proportional to the square of the multiplicity. CONSTITUTION:A multiframe editing part (CNV) 20 forms multiframes shifted for each frame from input highways (IHW) 11-11 corresponding to input highway banks (IBANK) 31-3j and inputs them to time switches (TSW) 41-4j. The time switches 41-4j change time slot positions for the unit of the multiframe and output them as output highway banks (OBANK) 51-5j, and a multiframe inverse editing part (DCNV) 60 resolves the multiframe into frames corresponding to output highways (OHW) 71-7k.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time division multiplex switch, and more particularly to a T1 stage time division multiplex switch.

[0002]

2. Description of the Related Art A T1 stage time division multiplex switch is a so-called complete group switch, and is characterized by easy software control. As a basic configuration, all time slots in the input highway with a frame structure are multiplexed and written to memory, and the time slot switching function (time switch function) is realized by controlling the read order of the output highway. There is. That is, one frame period (125 μse in the case of 64 Kbps exchange operation)
It is necessary to write and read time slots for the switch multiplicity in the memory in c), and it is necessary to increase the memory operation speed as the multiplicity is increased. 125 μs even when the memory has a double buffer configuration
A memory operation speed (cycle time) of 15 nsec if the multiplicity N = 8192 and 7.5 nsec if the multiplicity N = 16384 is required in the ec cycle, and the limit of the multiplicity is determined by the speed of the memory device. Will end up.

As a conventional example for solving this problem, as shown in FIG. 3, a plurality of (k) time switches (TSW) 80 are provided for each of the input highway groups (IHW) 11 to 1i.
Are connected in multiple and each TSW8 is selected by the selector (SEL) 90.
There is a configuration in which an output highway group of 0 is selected by time division and each of the output highway groups (OHW) 71 to 7k is output. Here, the multiplicity of the input highway and the output highway is the same (that is, i = k), and assuming that multiplicity is N, the multiplicity of each TSW 80 is N / i. Therefore, the operation speed of the memory is relaxed to 1 / i.

[0004]

The problem with this conventional time division multiplex switch is that the number of input highways × the number of output highways, ie, i × i, are required for the time switch (TSW) in order to relax the memory speed. It is in. That is, when trying to increase the multiplicity N at a constant memory operation speed,
There is a problem that the number of TSWs increases in proportion to the square of the multiplicity.

[0005]

According to the present invention, in a time division multiplex switch for exchanging frame-by-frame time slot positions of a plurality of input highways and outputting to a plurality of output highways, a predetermined number of each of the plurality of input highways are output. Means for multiplexing a plurality of frames at a predetermined cycle to form a multi-frame and editing the input highway bank with a plurality of input highway banks, and the time slot positions of each of the plurality of highway banks are exchanged at the multi-frame cycle. A plurality of time switches as banks, and a reverse editing means for editing the plurality of output highway banks into the plurality of output highways of one frame period,
Is equipped with.

Further, in the above structure, the editing means includes first selecting means for selectively connecting the plurality of input highways to the plurality of input highway banks, respectively, and each of the plurality of input highways is provided. From the above, the frames are sequentially selected by shifting the phase by one frame for each frame cycle, and multi-frames having the plurality of frames of the input highways as a cycle are formed by the number of the plurality of input highways. A plurality of output highway banks, the reverse editing means having second selection means for selectively connecting the plurality of output highway banks to the plurality of output highways respectively, and the multiframe of each of the plurality of output highway banks. Therefore, the phases are shifted one frame at a time for each frame cycle and sequentially selected. It can be respectively decomposing configuration to said plurality of output highways corresponding frame.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. Each of the input highways (IHW) 11 to 1i is a selector (SEL) of the multi-frame editing unit (CNV) 20.
21 to 2j, the input highway bank (IBANK) 31 to 3j for each multi-frame is edited.
Here, j represents the number of multi-frames. IBANK3
1 to 3j are time switches (TSW) 41 to 4 respectively.
The output highway bank (OBANK) 51 to 5j after receiving time slot replacement (time switch operation) at j
Is output from the TSWs 41 to 4j. Each TSW41
4j is a speech path memory (SPM) 4 as shown in FIG.
10, a read control memory (SCM) 420, and an address counter (CNT) 430. OBA
The NKs 51 to 5j are edited to output highways (OHW) 71 to 7k by selectors (SEL) 61 to 6k of a multi-frame reverse editing unit (DCNV) 60 that restores the original highway from one multi-frame period.

Next, the operation will be described. FIG. 4 is a highway time slot timing diagram for explaining the operation of the embodiment of FIG. 1 in a simplified manner with i = j = k = 4. Further, here, one frame is composed of 8 time slots. Since j = 4, the TSWs 41 to 4j operate in four multiframes. IHW11 ~
As shown in FIG. 4A, 14 configures one frame with 8 time slots, and the CNV 20 operates by regarding this as a highway of 4 multiframe configuration. Also,
It is considered that the phases of the multiframes are shifted one by one between the IHWs 11 to 14. Then, as shown in FIG.
Each SEL 21 to 24 of V20 selects a time slot belonging to the same multiframe of each IHW 11 to 14,
Highway bank for each multiframe (IBANK)
31 to 34 are output. As is clear from FIGS. 4A and 4B, the operation of the SELs 21 to 24 is only to sequentially select the IHWs 11 to 14 in one frame cycle. TSW
41 to 44 perform time slot replacement in four multi-frame cycles for the input IBANKs 31 to 34. In FIG. 4B, time slot # 1 (data A1, A2, A3, A4, ...) Of IHW11 and IHW4 is shown.
Time slot # 7 (data D1, D2, D3, D4
...) is replaced, and the replacement result is shown in FIG. The time slot switching operation in TSWs 41 to 44 is the same except that the start position of the multiframe is deviated. That is, TSW 41-44
The read control memory (SCM) has the same contents. As shown in FIGS. 4C and 4D, DCNV60
Similarly to the CNV 20, the SELs 61 to 64 select the OBANKs 51 to 54 after time slot replacement for each frame in order and output them as OHWs 71 to 74. By the above, time slot # 1 of IHW11 and time slot # 7 of IHW14 are exchanged (exchanged)
The operation is realized.

In this embodiment, IBANK11 to 1 are used.
Although each of j and OBANK71 to 7j has been described as having one highway structure, it goes without saying that it is also possible to configure a plurality of highways.

[0011]

According to the present invention, each time switch (TS
The multiplicity N of W) is equal to the multiplicity N of the entire time division multiplex switch. However, since the switch operation cycle of each TSW is made into a multi-frame of a plurality of (j) frame cycles, the operation speed of the memory operation is proportional to N / j. In other words, by multi-frame,
It is possible to reduce the operating speed of each TSW. In this case, the number of TSWs also increases, but it is only proportional to j, and does not increase by the square as seen in the conventional example. Therefore, according to the present invention, it is possible to realize a highly multiplexed time division multiplex switch more compactly than the conventional one by using a relatively low speed TSW.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a detailed configuration diagram of a time switch (TSW) of the embodiment of FIG.

FIG. 3 is a block diagram showing a conventional time division multiplex switch.

4A and 4B are timing charts of highway time slots for explaining the operation of the present invention, where FIG. 4A is an input highway format, FIG. 4B is a highway format after multiframe conversion, and FIG. ) Shows the highway format after the time slots are exchanged, and the diagram (d) shows the output highway format.

[Explanation of symbols]

 11, ..., 1j Input highway (IHW) 20 Multi-frame editing section (CNV) 41, ..., 4j Time switch (TSW) 60 Multi-frame reverse editing section (DCNV)

Claims (2)

[Claims] 1. A time-division multiplexing switch for switching time slot positions of a plurality of input highways in units of frames and outputting to a plurality of output highways, wherein a predetermined number of frames of each of the plurality of input highways are multiplexed at a predetermined cycle. Editing means for forming a multiframe to edit into a plurality of input highway banks, and a plurality of time switches for replacing each time slot position of each of the plurality of highway banks at the multiframe period to form a plurality of output highway banks. , A demultiplexing means for editing the plurality of output highway banks into the plurality of output highways of one frame period, the time division multiplex switch. 2. The editing means comprises first selecting means for selectively connecting the plurality of input highways to the plurality of input highway banks, respectively, and for each frame cycle from each of the plurality of input highways. , The phases are sequentially selected by shifting the phase by one frame from each other, and multi-frames having a plurality of frames corresponding to the plurality of input highways are formed as the plurality of input highways to form the plurality of input highway banks. The reverse editing means has second selecting means for selectively connecting the plurality of output highway banks to the plurality of output highways, respectively, and for each frame period from the multi-frame of each of the plurality of output highway banks. , One frame at a time, the phase is shifted by one frame from each other, and the phases are sequentially selected. The time division multiplex switch according to claim 1, wherein the time division multiplex switch is decomposed into frames corresponding to ways.