JPH03253199A - Time slot conversion circuit - Google Patents

Abstract

PURPOSE:To make the size of actual constitution small and to simplify the constitution even when lots of number of highways are employed by using a multi-port memory so as to set a line. CONSTITUTION:Multiplexer circuits 30, 32 apply time division multiplex to an input digital signal of plural highways and converts the signals into plural 1st multiplex signals, and a storage means 33 is provided with write address generating means 34 generating plural write addresses each of which is specific to each of plural sets of channel information subject to time division multiplex and plural read address generating means generating a readout address for each of plural sets of channel information. Then a storage means stores tentatively plural sets of channel information subject to in time division onto the plural 1st multiplex signals in write addresses via plural write ports and reads the information from the plural read pots according to the read address and gives the read information to demultiplex circuits, The demultiplex circuits 38, 39 demultiplex plural 2nd multiplex signals into an output digital signal on plural highways. Thus, even when lots of highways are employed, the constitution is not especially made large nor complicated.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is used for setting a transit route from a highway to another highway, from an exchange to a highway, or from a highway to an exchange. This relates to a time slot conversion circuit.

[Prior Art] The basic configuration of a conventional time slot conversion circuit is shown in FIG.

In FIG. 2, digital signals passing through a plurality of highways IN1 to Nm are time-division multiplexed in a multiplex circuit (MUX) 1 and then provided to a time switch unit 2. The time switch unit 2 includes a RAM (random ac
cess memory) configuration memory 3 and memory 3
It consists of a write address generation circuit 4 that generates a write address for the memory 3 and a read address generation circuit 5 that generates a read address for the memory 3. A multiplexed signal in which the position of the time slot on the time axis in the multiplexed signal is changed is output. The multiplexed signal with swapped time slots is sent to separation port B.
(DMUX>6, demultiplexed by this demultiplexing circuit 6, and output to a plurality of highways 0UT1 to OUTm.

In this way, the lines between highways INI-INm and highways 0UT1-OUTm are established.

By the way, when the number m of highways used for line setting is large, the degree of multiplexing by the multiplex circuit 1 becomes large, the time slot time becomes short, and the access time of the memory 3 is required to be short. However, there may be cases where the number of highways is so large that the access time of the easily available memory 3 cannot be met. In this case, a time slot conversion circuit shown in FIG. 3 has conventionally been used.

In FIG. 3, digital signals passing through a plurality of highways IN1 to INm are time-division multiplexed in a multiplexing circuit 289, and then given to a time switch unit IO, and then sent to a plurality of other highways IN(x+1) to INm. The digital signals passing through are time-division multiplexed in the multiplexing circuit 1i1811 and then provided to the time switch unit 10.

This time switch unit 10 includes four RAM memory units 12 to 15, a write address generation circuit 16 common to the memories 12 and 13, a write address generation circuit 17 common to the memories 14 and 15, and a memory A read address generation circuit 18 common to 12 and 13 and memories 14 and 15
and a common read address generation port B19.

The multiplexed signal from the multiplex circuit 9 is applied to memories 12 and 14, and for the memory 12, the write address generation port 1
16 is written according to the generated write address, and the write address generation circuit (7) is written to memory 4 according to the generated write address. The multiplexed signal from the other multiplex circuit 1 is sent to memory 3 and 15. write address generation circuit 16 for the memory 13.
is written in accordance with the write address generated by the write address generation circuit 17, and written into the memory 15 in accordance with the write address generated by the write address generation circuit 17.

The multiplexed signals stored in the memories 12 and 13 are read out according to the read address given from the read address generation circuit 18, and the time slots are exchanged.
Each is given to the selector circuit 20 as a selection input. The multiplexed signals stored in the memories 14 and 15 are read out according to the read address given from the read address generation circuit 19, the time slots are replaced, and each is given as a selection input to the selector circuit 21.

The selector circuit 20 is given a selection control signal that changes the selection input for each time slot from the read address generation circuit 18, and the selector circuit 20 sends the selection output to the separation circuit 2.
Give to 2. Similarly, the selector circuit 21 is supplied with a selection control signal from the read address generation circuit 19 that changes the selection input for each time slot, and the selector circuit 21 provides a selection output to the separation circuit 23. Each separation port ¥822
．． 23 separates the multiplexed signal whose time slots have been replaced and which has been selectively mixed and outputs it to the corresponding highway groups 0UTl to 0UTx and OUT (x+1) to OUTm.

For example, a signal from one of the highways in highway groups INI to INx is sent to highway groups 0UTl to 0UTx.
When feeding to either highway, the multiplex circuit 9
, the memory 12, the selector circuit 20, and the separation circuit 22.
+1) to OIJTm, multiplex circuit 9, memory 4, selector circuit 2■,
This is done via the route of the separation circuit 23.

In this way, lines can be set up even when there are many highways.

[Problems to be Solved by the Invention] However, according to the conventional device, as is clear from the comparison between FIG. 2 and FIG. This poses a problem in that the actual configuration becomes large and complicated. In other words, the one-chip memory area is divided into memories 12 to 15.
Therefore, if the number of highways were about twice as large as the number that could be accommodated by the basic configuration, it would not be twice as complicated and large, but four times as complicated and large. Although not shown in the drawings, if the number of highways becomes about n times (n is 3 or more) the number that can be accommodated by the basic configuration, it becomes about n22 times more complex and larger.

The present invention has been made in consideration of the above points, and it is an object of the present invention to provide a time slot conversion circuit that does not have a particularly large or complicated configuration even when a large number of highways are used for line setup. It is something.

[Means for Solving the Problem] In order to solve the problem, the present invention provides a method for changing the temporal or spatial order of a plurality of channel information time-division multiplexed on input digital signals of a plurality of highways. The time slot conversion circuit that exchanges the signals and converts them into output digital signals for multiple highways is composed of the following elements.

That is, it is provided with a multiplex circuit that time-division multiplexes the input digital signals of a plurality of highways and converts them into a plurality of multiplexed signals. Further, a plurality of write address generation means generate a unique write address for each of the plurality of channel information time-division multiplexed on the plurality of first multiplexed signals, and a plurality of write address generation means generate a read address for each of the plurality of channel information. read address generation means, and temporarily store a plurality of channel information time-division multiplexed on a plurality of multiplexed signals at a write address via a plurality of write ports, and temporarily store a plurality of temporarily stored channel information. and storage means for reading out a plurality of second multiplexed signals from a plurality of readout ports according to a readout address and outputting a plurality of second multiplexed signals. Furthermore, a plurality of second
and a separation circuit that separates the multiplexed signal into output digital signals of multiple highways.

[Operation] In the present invention, the multiplex circuit time-division multiplexes the input digital signals of a plurality of highways, converts them into a plurality of first multiplexed signals, and provides the first multiplexed signals to the storage means. In relation to this storage means,
A plurality of write address generation means for generating a unique write address for each of the plurality of channel information time-division multiplexed on the plurality of first multiplexed signals, and a plurality of read addresses for generating a read address for each of the plurality of channel information. Address generation means is provided. Therefore, the storage means temporarily stores the plurality of channel information time-division multiplexed on the plurality of first multiplexed signals at the write address via the plurality of write ports, and stores the temporarily stored plurality of channel information. The data is read from a plurality of read ports according to the read address and provided to the separation circuit.

The separation circuit then separates the plurality of second multiplexed signals into output digital signals of the plurality of highways.

In this way, an output digital signal is obtained in which the time slots of the input digital signal are converted.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

Also in this embodiment, a plurality of highways IN1 to IN
The digital signal passing through
The digital signals passing through the other plurality of highways IN(x+1) to INm are time-division multiplexed in the multiplexing circuit 32 and then provided to the time switch unit 31.

This time switch unit 31 includes one multi-port memory 33, a write address generation circuit 34 that generates a write address for this memory 33, and t readout circuits that generate first and second read addresses for the memory 33. The address generation circuit 35 is also provided.

The multi-port memory 33 of this embodiment includes two input ports 33i1 and 3312, two sets of two output ports 33011 and 33012, 33o21 and 33o22, and four output ports 33011 and 33012. There are two areas specified by addresses. That is, it includes two memory area groups ARI and AR2.

The multiplexed signal from the multiplexing circuit 30 is applied to the second input port 33i1 of the memory 33, and the multiplexed signal from the multiplexing circuit 32 is applied to the second input port 33i2 of the memory 33. The multiplexed signal input to the first input port 33iL is written to any area of the first memory area group ARI specified according to the write address generated by the write address generation port i\834, and The multiplexed signal input to the input port 3312 of is written to any area of the second memory area group AR2 specified according to the write address generated by the write address generation circuit 34.

In this embodiment as well, the switching of time slot positions, which is a function of the time switch section 31, is performed based on the difference in the change order of the write address and the read address.

A first memory area group AR specified according to the first read address generated by the read address generation circuit 35
The multiplexed signal written in any area of I is output from the first output port 33011 and given to the selector circuit 36 as a first selection input. The multiplexed signal written in any area of the second memory area group AR2, which is specified according to the first read address, is output from the second output port 33o12 and sent to the selector circuit 36 as a second selection input. given as.

Similarly, the multiplexed signal written in any area of the first memory area group ARI, which is specified according to the second read address generated by the read address generation circuit 35, is output from the third output port 33o21. The multiplexed signal written in any area of the second memory area group AR2 specified according to the second read address is given as the first selection input to the selector circuit f137. It is output from the output port 33o22 and given to the selector circuit 37 as a second selection input.

The read address generation circuit 35 also outputs selection control signals for these selector circuits 36 and 37.

The read address generation circuit 35 selects highways in the first input highway group INI to INx and the first output highway group 0UT1 to 0UT1 to be described later to the selector circuit 36.
When setting up a line with the highway in 0UTx, select the multiplexed signal from the first output port 33o11 of the memory 33, and select the multiplexed signal from the second input highway group IN(
x+1) to INm and the highways in the first output highway group 0UT1 to 0UTx, the second output port 3 of the memory 33
The multiplexed signal from 3012 is controlled to be selected.

Further, the read address generation circuit 35 includes the selector circuit 3
7, the first input highway group INI~INx
highways within and the second output highway group OU, which will be described later.
When setting a line with the highway in T(x+1)~OUTm, select the multiplexed signal from the third output port 33o21 of the memory 33 and connect the second input highway group IN(x+1)~INm. inner highway and second output highway group OUT (x+1) ~OUT
When setting up a line with a highway within m,
Control is performed to select the multiplexed signal from the fourth output port 33o22 of the memory 33.

The multiplexed signals output from each selector circuit 36, 37, in which the time slots have been replaced and which have been selectively mixed, are applied to the corresponding separation circuits 38, 39. Each separation port 138.3 separates the input multiplexed signal and outputs the corresponding highway group 0UT1 to 0UTx, OUT (x+
1) Output to ~OUTm.

FIG. 4 is an explanatory diagram showing an example of line setting operation in the first embodiment. Note that, to simplify the explanation, the number of highways (m) is assumed to be eight.

This figure 4 shows each highway INI to INS on the input side and the highway 0UT2.0UT3.0 on the output side.
UT8.0UT7.0UT6.0UT1.0UT4.0
This shows the case where a line is set up in UT5.

Information a to d on highways INI to INJ is multiplexed by the multiplexing circuit 30 and applied to the first input port 3311 of the memory 33 in the order of a to d and stored therein. The information eh on the highways IN5-INS is multiplexed by the multiplexing circuit 32, and is applied to the second input port 33i2 of the memory 33 in the order of eh to be stored.

The write address generation circuit 34 and the read address generation circuit 35 generate a write address and a read address according to the state to be set, and replace the time slots. Thus, in this example, the first output port 3
Information is output in the order of babC from 3o11, information is output in the order of fefg from the second output port 33o12, information is output in the order of dadc from the third output port 33o21, and information is output in the order of dadc from the fourth output port 33022.
Information is output in this order.

The selector circuit 36 has a second input, a first input,
The selection operation is performed in the order of the second human power, and information is output around fabg 1. The selector circuit 37 performs a selection operation in the order of second manual power, second manual power, first input, and first input, and outputs information in the order of hedc.

Thus, for example, the line is set up in a predetermined manner so that information a of the input highway INI is supplied to the output highway 0UT2.

Therefore, according to this embodiment, since line setting is performed using a multiport memory, the actual configuration can be made small and simple even when the number of highways is large. Compared to the conventional system, if the number of meters of highway is the same, the configuration can be reduced to about 1/2.

Note that in the above embodiment, a multiport memory with two input ports and four output ports is used, but a multiport memory with one input port and two output ports is used. The structure shown in FIG. 1 may be realized by using the same.

Further, in the above-described embodiment, the ratio of the input port to the output port of the memory is shown as 2:2, but the same configuration can be made even if the ratio is 2:3 or more. In this case, it is necessary to group the highways into three or more groups. Note that in practice, the number of input/output ports in one multiport memory is limited to a certain extent, so 1
Although it is difficult to realize such a modified example with one multi-port memory, it is possible to realize it by using a plurality of multi-port memories.

[Effects of the Invention] As described above, according to the present invention, for each of y (y is 2 or more) multiplexed signals, y multiplexed signals are obtained by replacing the time slots, that is, Since a total of y2 multiplexed signals are obtained and line settings are made by appropriately selecting these multiplexed signals, the time slot conversion circuit can be relatively small and have a simple configuration even when the number of highways increases. can be realized.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a time slot conversion circuit according to the present invention, FIG. 2 is a block diagram showing the basic configuration of a conventional circuit, FIG. 3 is a block diagram showing an expanded configuration thereof, and FIG. 4 FIG. 2 is an explanatory diagram showing an example of line settings in the above embodiment. 30.32...Multiple circuit (MUX>, 31...Time switch unit, 33...Multi-port memory, 34...
...Write address generation circuit, 35...Read address generation circuit, 36.37...Selector circuit, 38.3
... Separation port i ¥8 (DMUX>.

Claims (1)

[Claims] Time slot conversion for converting a plurality of channel information time-division multiplexed onto input digital signals of a plurality of highways into output digital signals of a plurality of highways by changing the temporal or spatial order of the information. The circuit includes: a multiplexing circuit that time-division multiplexes input digital signals of the plurality of highways and converts them into a plurality of first multiplexed signals; and a plurality of channel information time-division multiplexed on the plurality of first multiplexed signals. a plurality of write address generation means for generating a unique write address for each channel information; a plurality of read address generation means for generating a read address for each of a plurality of channel information; A plurality of channel information is temporarily stored at the write address via a plurality of write ports, a plurality of temporarily stored channel information is read from a plurality of read ports according to the read address, and a plurality of second multiplexed signals are generated. and a separation circuit that separates the plurality of second multiplexed signals into output digital signals of a plurality of highways.