JPS6174496A - Circuit editing system - Google Patents

Abstract

PURPOSE:To set up data speeds of input signals to plural channels optionally and to send the signals to respective pathes with the minimum number of circuits required by editing and outputting the multiplex signal of many having different speeds respectively in each data. CONSTITUTION:Input signals A1-An are stored in memories T1(1)-T1(n) successively and read out signals B1-Bn are inputted to a switch circuit SW to replace spatial positions, stored in memories T2(1)-T2(n) as signals C1-Cn and then outputted as signals E1-En. When the addresses of a control memory ACM are specified by a control information input, the addresses of respective memories and switches are specified in respective channels. Consequently, the multiplex signal of many kinds of data having different speeds is replaced as the time slots and output lines of these data to edit each data.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a data line having a plurality of incoming lines and outgoing lines. This relates to a line editing method for editing.

Prior Art and Problems In a data line with multiple incoming lines and outgoing lines,
For a signal that is multiplexed with many types of data at different speeds, it may be necessary to rearrange the order of the data and edit each data item. Conventionally, as an editing method for editing data on a data-by-data basis, fixed or semi-fixed connection circuits using switch circuits or cord circuits have generally been used.

FIG. 1 shows a conventional line editing system. In the same figure, a1 to an, bl to bn are incoming lines, 1-1
, ~1-λ is a switch circuit or code circuit, 01~c
m and dl-dm are outgoing lines.

In FIG. 1, incoming lines a1 to an and bl to bn are one line per data channel, and outgoing line cl=ci
The data rate is fixed for each line ~(m, di~di=dm. For example, if the data rate of the outgoing lines C1~ci''cm is 3.2 kb/s, the data rate of the outgoing lines C1~c
All editing within i"cm is fixed at a data rate of 3.2 kb/s. In addition, the editing in this case is a spatial editing method, and the switching circuit or code circuit 1-1 to 1-a, the combination is changed and edited.

In this case, for example, incoming lines a1 to an, outgoing lines C1 to c
i=cm 3.2kb/s data, input line b1~b
n, outgoing line d1~d i” dm 12.8kb/
In the case of s data, incoming lines a1~an and outgoing lines d1~
between di=dm or incoming lines b1 to bn and outgoing line c1
Since it is impossible to cross between ~ci=cm, a large number of outgoing lines are required.

OBJECT OF THE INVENTION The present invention attempts to solve the problems of the prior art, and its purpose is to When editing a signal in which speed data is multiplexed for each data, it is possible to freely set the data speed of each channel of input signals of multiple channels, and also to freely transfer between each line. The object of the present invention is to provide a system that can transmit signals to each direction using the minimum necessary number of lines.

Embodiment of the Invention FIG. 2 shows the configuration of an embodiment of the line editing system of the invention. In the figure, Tl(11, Tl(2), -
....

T I (nl is input memory, SW is switch circuit, T
2(1), T2(21, . . . , T2(n) is an output memory, and ACM is a control memory.

In FIG. 2, memories TI(11, Tl(2), -
, Tl(nl stores input signals At, A2+-, An in input order. Memories Tl(11, Tl(21,-, Tl
(Signals 81, B2, ..., Bn read from nl
are input to the switch circuit SW, their spatial positions are swapped and output as signals C1, C2, . . . , Cn,
Memory T2(1), T2f21, -, T2fn
) are stored in the order of input. Memory T2(11, T2(2
The signals read from 1, -, T2 (nl are output as output signals El, E2...En. The control memory ACM controls the memory T2 at this time based on the control information.
l(11, T2(2), -.

Read address in T2(n), input/output address in switch SH, memory T2(11, T2(2)
1.~.

Controls the read address in T2Tnl. Such writing and reading of data is performed, for example, in units of octets.

FIG. 3 shows an example of the configuration of the control memory in FIG. 2. In the figure, 11 is a control information storage unit;
12 is a channel information storage unit, 13 is a counter (CTR)
It is.

The control information storage section 11 consists of a read-only memory, and when an address in the control information storage section 11 is specified by the control information input, the memo 'J Tl1)
, Tlf2) , -, the read address for Tl(n), that is, the ACM(1) address, the input/output address in the switch circuit SW, that is, the SW address, and the memory T2(L) , T2(21, -, T2(nl)
A read address, that is, ACM (21 address) is output, and this information is stored in the channel information storage section 12 for each channel.The counter 13 sequentially counts up every channel repetition period, and stores the information in the channel information storage section. 12, thereby indicating the address of each channel in memory Tl(1),
T1121.

-, Tl(nl, switch S-, memory T2(11, T
2 (21, -.

T2(nl is addressed).

FIG. 4 is a time chart showing an example of data editing in the line editing method of the present invention. In the figure, a case where the channel repetition is divided into 20 is illustrated. Now, with A1+A21-1 An as the input signal string,
Data D1 to D24 as shown in FIG. 4 are input, among which data Di, 012.013. D23 and data D2.014.021. D22 and data D3.
It is assumed that Dll and D24 have the same data rate in their respective groups. However, the speed of the second group is twice that of the first group, and the speed of the third group is twice that of the first group.
This is twice as many as the group. These input signals are converted to ACM (1) address and SW address for each channel.

ACM (Controls the 21 address and edits it so that it is output to the specified output section.

In FIG. 4, for example, focusing on data D1, input signal A
Consider a case where data DI input to the 0th channel of I is edited so as to be output to the 1st channel of the output signal En. To do this, first, the address ACM (11) switches the time slots of the data D1 to the second channel of the signal B1 corresponding to the signal A1.Next, the address SW changes the data D1 in the signal B1 to the signal C.
Push into the same channel in n. Next address A
CM (21) performs time slot swapping of the data D1 to the 1st channel of the output signal En corresponding to the signal Cn.In this way, the data D1 inputted to the 0th channel of 1 to the input signal is changed to the output signal En. Data can be edited so that it is output to the first channel of .Other data can be edited in the same way.

FIG. 5 shows editing of the data illustrated in FIG. 4 for each data item. In the same figure, A, B
, C, E are the signals A1+A2 . in FIG. 4, respectively. −
．． An, Bl, B2+-+Bn 5CLC2+'-
+CnXE1+ε2. ~． For example, data D1 in signal A is given by line name (A1-0).
1) and the channel name (0).

As described in detail, according to the line editing system of the present invention, each incoming line is a plurality of input memories provided for each input line for storing data in input order; and a switch circuit; and an output memory provided for each output line for storing data for each output line of the switch circuit in input order. , control means for controlling the data reading in the input memory and the output memory and the connections on the input side and the output side of the switch circuit. On the other hand, it is extremely effective because editing can be performed for each data item by replacing the data time slots and output lines.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a conventional line editing method, FIG. 2 is a diagram showing a configuration of an embodiment of the line editing method of the present invention, and FIG. 3 is a diagram showing an example of the configuration of a control memory in the method of the present invention. 4 is a diagram showing an example of data editing in the method of the present invention, and FIG. 5 is a diagram showing editing of the data illustrated in FIG. 4 for each data. 71(IJ, Tl(21, -, TI(nl: input, %'%U, store: switch circuit, T2(11, T2(2
1, -, T2 (nl: output memory, ACM: control memory, 11: control information storage section, 12: channel information storage section, 13: counter (CTR) Patent applicant
Fujitsu Limited (1 other person) Agent Patent attorney Gobe Tamamushi (1 other person) Figure 1 Figure 2 Control practice information

Claims (1)

[Claims] In a data line that has multiple incoming lines and outgoing lines and multiplexes and transmits many types of data, a plurality of input memories provided for each incoming line that stores the data of each incoming line in the order of input; A switch circuit that switches the data read from the input memory to a designated output line for each data and outputs the data, and a switch circuit that is provided for each output line that stores the data of each output line of the switch circuit in the order of input. an output memory; and control means for controlling data reading in the input memory and output memory and connections between the input side and the output side of the switch circuit,
A line editing method characterized by editing and outputting a signal made up of multiplexed data of many different speeds.