JP2990793B2 - Satellite exchange - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exchange suitable for mounting on a satellite, and in particular, requires a memory to perform exchanges such as data rate conversion and channel conversion, and requires a switch circuit part. The present invention relates to a satellite exchange using a space switch with a memory.

[Conventional technology]

Next, a conventional satellite exchange will be described with reference to the drawings.

FIG. 3 is a functional block diagram of an example of a conventional satellite exchange.

To the satellite exchange, input data Di of a continuous signal that is time-division multiplexed to an integral multiple of a constant transmission rate is input from n (n is a positive number of 2 or more) input data lines 101 from D1 to Dn, It is assumed that output data Do of continuous signals which are also time-division multiplexed are output to m (m is a positive number of 2 or more) output data lines 102 from d1 to dm. When the input data Di is input from each of the input data lines 101 to the information data memory circuit 1, each of the input data Di is written to a plurality of memories 6 arranged in parallel (two columns in the drawing) in the order of input. .
The number of parallel memories 6 is determined from the number of output data lines 102 and the processing speed of the satellite exchange. The input data Di written to the memory 6 is output from the address data editing circuits 3a and 3b prepared in the same number as the parallel number of the memory 6, and designates the multiplex address data input through the multiplex address data lines 104a and 104b. And is generated in time-division multiplexed data. This data is output to output data buses 103a and 103b, and is also input to signal division circuits 4a and 4b prepared in the same number as the parallel number of memories 6. The signal dividing circuits 4a and 4b divide the input data together into m output data lines d1 to dm, and
It outputs to each of the output data lines 102 as Do.

The multiplex address data is generated by the pattern generation circuit 2 and the address data editing circuits 3a and 3b. The pattern generation circuit 2 generates mk (2 ≦ k ≦ m) high-speed address pattern generation circuits 7 for generating high-speed output address patterns and k low-speed address pattern generations for generating low-speed output address patterns. It has a circuit 8. The address data generated by the m address pattern generation circuits 7 and 8 in total correspond to each of the m output data numbers 102, and define each output pattern of the m output data Do. The address data output from the high-speed and low-speed address pattern generation circuits 7 and 8 are input to the corresponding address data editing circuit 3a or 3b through the high-speed address data line 105 and the low-speed address data line 106, respectively. The distribution of the address data to the address editing circuit 3a or 3b is arbitrary. The address data editing circuits 3a and 3b time multiplex the input address data. Each of the address data editing circuits 3a and 3b has multiple address data lines.
The multiplexed address data is transmitted to n memories 6 corresponding to the number of input data lines 101 through 104a and 104b.

FIG. 4 is a diagram for explaining the operation of the satellite exchange shown in FIG. 3, and shows an example of a data time slot allocation situation on the output data bus 103a of the information data memory circuit 1.

Time slot repetition period T (for example, T1 to T8
8 time slot) indicates a cycle of data having the highest data rate in the output data read from the information data memory circuit 1 of the satellite exchange. Also, one cycle T is divided into two equal parts, a read cycle and a write cycle, and the read cycle is further divided into four time slots. The data of each time slot of the repetition period T, that is, data A, B, C, and D, are
The output data line is divided by a, and output is performed by four different data lines among the output data lines 102. The output data A is data having the highest data rate, and therefore, the entire time slot T1 is filled in the period from t1 to t5 indicating the lapse of time t. Time slot T2 is assigned data B of data rate 1/2 of A, time slot T3 is assigned data C of data rate 1/3, and time slot T4 is assigned data D of data rate 1/4. Have been. On the other hand, in the conventional example shown in FIG. 3, the address data editing circuit 3a multiplexes four address data, outputs multiplexed address data to one address data line 104a, and outputs the multiplexed address data to the memory shown in the left side of FIG. 6 is a read address.

Thus, in the conventional example, the repetition period T of 1
The data of one time slot was transmitted on one of the m output data lines 102. Therefore, as shown in FIG. 4, when the data rate of the data on each output data bus 103a or 103b is lower than the highest speed data, the time slot assigned to this data bus 103a or 103b (eg, In this case, T2 to T4) were not effectively used.

[Problems to be solved by the invention]

In the above-mentioned conventional satellite exchange, when the number of output data increases, it is necessary to increase the number of time slots of the repetition period T on the output bus line of the memory. Since the processing speed of the memory is limited, the number of output bus lines must be increased by assuming that the number of time divisions of one output bus line is constant. Then, the number of information data memory circuits increases in proportion to the number of output bus lines, and there is a disadvantage that the circuit scale as a whole increases.

[Means for solving the problem]

In the satellite exchange of the present invention, input data of a continuous signal time-divided to an integral multiple of a constant transmission rate is input from n (n is an integer of 2 or more) input data lines, and output data of the continuous signal is m ( m is a positive number of 2 or more). In a satellite exchange which outputs from two output data lines, the input data is written to the memory in the order of input, and the written input data is written from the memory in the order specified by the address data. An information data memory circuit for reading and generating time-division multiplexed data, and dividing the time-division multiplexed data to m
A signal dividing circuit that outputs the output data of the continuous signal to the output data lines; and read address data having output pattern information of each of the output data output to the m output data lines. A pattern generation circuit, a low-speed address multiplexing circuit that time-division multiplexes low-speed address data among the read address data to generate high-speed address data, and a high-speed address data generated by the pattern generation circuit and the low-speed address multiplexing circuit. And an address data editing circuit for converting the generated high-speed address data into the address data by time-division multiplexing and outputting the address data to the information data memory circuit.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a functional block diagram of one embodiment of a satellite exchange according to the present invention, and FIG. 2 is an explanatory diagram of the operation of the present embodiment. An example of a time slot allocation situation of data on an output data bus of an information data memory circuit. Is shown.

The satellite exchange of this embodiment has an information data memory circuit 1, signal division circuits 4a and 4b, and a pattern generation circuit 2 for generating m read address data, which are included in the satellite exchange shown in FIG. , The address editing circuit 3a and
3b, a low-speed address data multiplexing circuit 5 is provided between the pattern generating circuit 2 and the address data editing circuit 3a. This low-speed address multiplexing circuit 5 has k (2 ≦ k ≦ m,
Integer number of low-speed address pattern generation circuits 8
The k low-speed address data input via the low-speed address data lines 106 are multiplexed into one high-speed address data. Then, the multiplexed high-speed address data is input to the address data editing circuit 3a via the high-speed address data line 105a. The address data editing circuit 3a compares the high-speed address data generated by the high-speed address pattern generation circuit 7 and input through the high-speed address data line 105 with the high-speed address data input through the high-speed address data line 105a. Edit and output the multiple address data to the multiple address data line 104a. As a result, the data read out to the output data bus 103a of the information data memory circuit 1 is only high-speed data, and time slots on this bus can be eliminated. The same operation is performed when the low-speed address data multiplexing circuit 5 is connected to the address data editing circuit 3b.

Therefore, in the operation of the conventional example shown in FIG. 4, the output data bus of the information data memory circuit 1, for example, 103a contains only four data A, B, C, and D. In the embodiment shown in FIG. 2 and FIG.
The time slot is read by multiplexing the low-speed data written in the memory 6 with the address data on the multiplexed address data line 104a multiplexed at the same speed as the high-speed address data of the highest-speed data and reading out the data to the data bus 103a. It can be used without waste. That is, in FIG. 2, the time slot T1 has data A, which is the fastest data, and T2 has data having a data rate 1/2 that of data A.
B, E, and T2 output a total of ten pieces of data C, F, G, and T4, and data D, H, I, and J at a data rate of 1/4. As described above, in the same cycle T and time slot division (T1 to T8) and time t1 to t5 as in the conventional example, A, B,
.., J can be included in four time slots.

〔The invention's effect〕

As described above, according to the present invention, when address data for reading output data having a high transmission speed and low-speed address data are mixed, the low-speed address data is time-division-multiplexed and converted into high-speed address data. Empty time slots on the output data bus of the data memory circuit can be eliminated. Thus, when the satellite exchange outputs a large number of low-speed data, the number of output data included in one output data bus of the information data memory circuit can be increased and the number of output data buses can be reduced. At the same time, the number of memories in the information data memory circuit can be reduced, and the circuit scale of the satellite exchange itself can be reduced.

As an example, four output data buses are conventionally provided to output 16 low-speed data, and one output data bus has
When 10 memories are connected, by using the present invention, if the 16 low-speed data can be combined into 1 high-speed data, all data can be output only by one output data bus, and As a result, the circuit scale can be reduced by 30 memories.

[Brief description of the drawings]

FIG. 1 is a functional block diagram of a satellite exchange according to one embodiment of the present invention, FIG. 2 is an explanatory diagram of its operation, FIG. 3 is a functional block diagram of a conventional embodiment, and FIG. . 1 ... information data memory circuit, 2 ... pattern generation circuit, 3a, 3b ... address data editing circuit, 4a, 4b ... signal division circuit, 5 ... low speed address multiplexing circuit, 6 ... memory, 7 ... High-speed address pattern generation circuit, 8: Low-speed address pattern generation circuit, 101: Input data line, 102
…… Output data line, 103a, 103b …… Output data bus, 104
a, 104b: Multiple address data lines, 105, 105a: High speed address data lines, 106: Low speed address data lines.

Claims (2)

(57) [Claims] An input data of a continuous signal time-divided to an integral multiple of a constant transmission rate is input from n (n is an integer of 2 or more) input data lines, and output data of the continuous signal is m (m is an integer). 2
In the satellite exchange outputting from the above (positive number) output data lines, the input data is written into the memory in the order of input,
An information data memory circuit for reading the written input data from the memory in the order specified by the address data to generate time-division multiplexed data; and dividing the time-division multiplexed data into m outputs A signal dividing circuit for outputting the output data of a continuous signal to a data line;
A pattern generation circuit for generating read address data having output pattern information of each of the output data output to the output data lines; and a time division multiplexing of low speed address data among the read address data to obtain a high speed address. A low-speed address multiplexing circuit for generating data; and high-speed address data generated by the pattern generation circuit and high-speed address data generated by the low-speed address multiplexing circuit are time-division multiplexed and converted to the address data. An address data editing circuit for outputting data to the information data memory circuit. 2. A predetermined data line out of the output data lines for outputting data according to a time throttle adjusted to output data having the highest data rate includes:
2. The satellite exchange according to claim 1, wherein a plurality of data having a data rate which is a fraction of the highest data rate is output.