JPS6348993A - Digital signal generator - Google Patents

Abstract

PURPOSE:To generate a digital signal with a simplified circuit and to improve a noise resistance and processing speed by dividing recording circuit into plural memory areas, reading PB and PCM data written in the respective areas in the same format and reading by the use of a reading counter. CONSTITUTION:The selection signal of the PB signal transferred from the central control unit of a digital signal generator is recorded on recording elements 2, 3. The transmission cycle of a tone signal is decided in a transmission cycle forming circuit 4 and one memory area in the memory circuit 6 is selected by a data selector 5. Further, the PCM data in the area of the circuit 6 is read with a sampling frequency by the reading counter 7, applied to a shift register 8 to convert parallel data into serial data and outputted to a speech path 10. The respective timings of the recording elements 2, 3, the circuit 4, the selector 5 and the register 8 are controlled by a selection circuit and a timing circuit 9 and the digital signal is outputted by the simplified circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an improvement in a digital signal generator that is attached to a digital exchange and generates digital signals such as PB signals and tone signals.

Due to the disadvantages of conventional digital exchanges, PB signal and tone signal generators that are compatible with these are also required. That is, such a generator stores PB signals and tone signals in PCM codes, and the readout order and readout timing are controlled in order to supply a predetermined signal among them on a predetermined time slot. There must be.

Conventionally, as such a generator, Japanese Patent Application Laid-Open No. 59-4909
As disclosed in Publication No. 3, the configuration is such that the PCM codes of the PB signal and tone signal are stored in a ROM, and read out by a microprocessor using software.

However, since the above conventional means uses a microprocessor, noise resistance is insufficient, and the influence of noise can cause the program to run out of control, making normal operation impossible. There's a problem.

Furthermore, since the processing is performed by software using a microprocessor, the processing speed is inevitably slow, and there is a problem that it is disadvantageous for systems that require high-speed processing such as digital exchanges.

Therefore, an object of the present invention is to provide a digital signal generator that can solve these problems.

To achieve the above object, the present invention provides a storage element for storing a PB signal selection signal from a central control unit, a selection circuit for selecting one of a plurality of tone signals, A circuit that generates a tone signal sending cycle and a PB signal and tone signal P in each memory area divided into a plurality of areas.
a memory circuit in which CM data is written in the same format; a data selector that selects one of the memory areas of the memory circuit based on signals from the PB signal selection signal and the tone signal selection circuit; and the selected memory area. a read counter that reads out the PCM data in the memory circuit at a predetermined timing; a shift register that converts the PCM data output from the storage circuit from parallel to serial and sends it out to the communication path at a predetermined timing; and a shift register that reads the PCM data from the shift register. It is characterized by comprising a timing circuit that generates the timing for sending out to the communication path.

According to the present invention, a circuit for reading out PCM data of a PB signal and tone signal from a storage circuit and sending it out to a communication path can be configured in hardware.

Therefore, the problems of the conventional example configured with a microprocessor can be solved.

JLJf FIG. 1 is a block diagram showing an embodiment of the digital signal generator of the present invention, in which 1 is a central control unit of a digital exchange, and 2 and 3 store a PB signal selection signal sent from the central control unit 1. 4 is a transmission cycle generating circuit that determines the transmission cycle of tone signals; 5 is a data selector that selects one memory area in the memory circuit 6; 7 is a PCM in the memory area; A read counter reads data at a sampling frequency (8KH2); 8 is a shift register that converts the 8-bit parallel data sent from the storage circuit 6 into serial data and sends it out at a predetermined timing; 9 is a various tone signal A selection/timing circuit is a combination of a selection circuit for selecting PCM data and a timing circuit for generating timing for sending PCM data to the shift register 8. 10 is a communication path.

For example, a ROM is used as the storage circuit 6, and the memory area thereof is divided into a plurality of areas, and each area stores the PB signal and tone signal in the same format. In this embodiment, the memory area is divided into 24 areas, and as shown in Table 1, 8 areas are allocated to tone signals and 16 areas are allocated to PB signals. One area consists of 512 words, of which 400 words have PCM data written. When selecting one of 8 types of tone signals, 16 types of PB signals, and a total of 24 types of digital signals, selection is possible using a 5-bit signal line. In this case, the most significant 1 bit is used to select the tone signal or PB signal, and the following 4 bits are used for the PB signal and tone signal, in which case 3 bits are sufficient.)
You can make a selection.

(Hereinafter, blank space) Sampling frequency: 8KllzTable 2 shows the relationship between the tone signal and PB signal, frequency, and number of data. The values of the PB signal and frequency are changed within an allowable range in order to keep the number of data within 400 words. Read counter 14 that reads data in one area
counts 8KHz pulses and advances the count value, so for example, a signal with 400 data in one cycle will have 2
It becomes 0Hz. And the number of words in one area is 400
Therefore, the number of repetitions in the area is one. Similarly, the frequency, the number of data required for one period, and the number of repetitions in the area are as shown in the table below. If the number of repetitions in the area is an integer, it means that the signal data can be suppressed to 400 words.

Sixteen types of PB signals and a PB signal selection signal for selecting one of them are sent from the central control unit 1 to the flip-flop 2.3. The number of flip-flops corresponds to the PB signal during the channel time slot and the number of assigned channels. In this embodiment, two channels of channel time slots are allocated for the PB signal using two flip-flops. The PB signal selection signal is sent to the data selector 5 according to the timing determined by the selection/timing circuit 9, and is further sent to the ROM 6 to select a memory area.

One of the eight types of tone signals is selected by the selection/timing circuit 9, and is read out from the ROM 4 in accordance with the transmission cycle determined by the transmission cycle generation circuit 4.

PCM of PB signal and tone signal read from ROM6
The data is sent to shift register 8.

The shift register 8 converts the 8-bit parallel data into serial data according to the timing generated by the selection/timing circuit 9, and sends it to the communication path 10.

These timings are shown in FIG. The communication channel time slot is composed of 32 channels, of which PB signals and PCM data are assigned to 2 channels, and PCM data of tone signals are assigned to 8 channels. Each channel has a period corresponding to 8 KHz. 1
The channel consists of 8 bits of data.

In the embodiment, a selection circuit for selecting a tone signal and a PCM
Although the timing circuit and the timing circuit for generating the timing for sending data from the shift register to the communication path are combined, it goes without saying that they may be configured as separate circuits.

As explained above, according to the present invention, the memory circuit is divided into a plurality of areas, and each area is provided with a PC for a PB signal and a tone signal.
Since M data is written in the same formant and read out using a read counter, digital signals can be generated with a simplified circuit, and without using a microprocessor like in the past. Since it is configured in terms of hardware, it has the advantage of excellent noise resistance and fast processing speed.

In addition, it eliminates the need for program development and management, and has the advantage of being more compact than the conventional case of using multiple microprocessors.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the digital signal generator of the present invention, and FIG. 2 is a diagram showing time slots of a communication path. 1... Central control unit 2.3... Memory element 4... Sending cycle generation circuit 5... Data selector 6... Memory circuit 7... Read counter 8... Shift register

Claims (1)

[Scope of Claims] A storage element that stores a PB signal selection signal from a central control unit; a selection circuit that selects one of a plurality of tone signals; a circuit that generates a tone signal transmission cycle; A storage circuit in which PCM data of the PB signal and tone signal is written in the same format in each memory area divided into regions, and a memory of the storage circuit based on signals from the PB signal selection signal and tone signal selection circuit. A data selector that selects one of the memory areas; a read counter that reads out PCM data in the selected memory area at a predetermined timing;
A digital signal generator comprising: a shift register that performs serial conversion and sends the PCM data to a communication path at a predetermined timing; and a timing circuit that generates timing for sending PCM data from the shift register to the communication path.