JP3821682B2 - Data conversion circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data conversion circuit, and more particularly to a data conversion circuit that converts data in a wireless side format into data in a ground side format via a dual port RAM in a wireless communication between a communication satellite and the ground.
[0002]
[Prior art]
In recent years, wireless communication using satellite communication has become widespread due to the development of communication technology. In such satellite communication, it is necessary to convert data sent from a communication satellite by radio to a format for ground communication. Such format conversion is generally performed by providing a TDMA expansion buffer in a time division multiple access (TDMA) satellite communication exchange, and requires a separate device from the speech path memory.
[0003]
An example of the prior art that solves this problem is disclosed in Japanese Patent Laid-Open No. 60-214697 as “Time switch with format conversion function” (prior art 1). In the present technology, a time switch memory including a two-way speech path memory that alternately performs writing and reading every 1 TDMA frame is employed. The first counter outputs a sequential write address to the time switch memory. The second counter generates the frame number in 1 TDMA frame, and the control memory generates the read channel number. The adder circuit adds the frame number and the read channel number and outputs the result as a read address to the time switch memory.
[0004]
In the prior art 1 described above, the time switch memory is provided with the format conversion function, so that the speech path memory is shared for TDMA format conversion, and thus a device separate from the speech path memory is not required. .
[0005]
However, in the prior art 1, since writing and reading of the two-plane memory are alternately performed for each radio side frame, it is necessary to switch the plane of the two-plane memory for each radio side frame. A delay corresponding to the frame occurs. Therefore, when this circuit is used for a voice line, there is a problem that the delay amount is large and the echo becomes large, resulting in deterioration of voice quality (sound quality). Furthermore, since the same circuit is used for the counterpart device that performs wireless communication, a double delay amount occurs between transmission and reception, and sound quality deterioration is further increased.
[0006]
The following technique (prior art 2) that solves this problem is known. In this data conversion circuit, a dual-port RAM is used to form a two-plane memory, and when the data format is converted from the write side (wireless side) format having a time length that is an integral multiple of the read side (ground side) format to the ground side format. As soon as the writing of the time slot data on the wireless side to the two-sided memory is completed, the surface switching of the two-sided memory is performed in units of the time slot data in the ground format without waiting for the end of the wireless side frame, Read data. By doing so, the delay time required for data format conversion from the radio side format to the ground side format is minimized, the generation of unnecessary echoes is prevented, and the voice quality is improved.
[0007]
FIG. 7 shows an image of general data format conversion between the wireless side format and the ground side format. In this example, as shown in FIG. 7, the radio side format is composed of data with a frame period of 4 ms, one frame with 64 time slots V00 to V63, and one time slot with 128 bits. Is 125 μs, one frame is 64 time slots U00 to U63, and one time slot is composed of 4-bit data.
[0008]
One time slot in the radio side format, for example, 128 bits concentrated in V00, is distributed in 4 bits in each time slot U00 of 32 consecutive frames after 125 μs in the ground side format.
[0009]
FIG. 8 is a block diagram showing Prior Art 2 for realizing the format conversion shown in FIG. The data conversion circuit shown in FIG. 8 generates a dual port RAM 21 for temporarily storing data, a serial / parallel conversion unit 22 for converting serial input data into parallel data, and an address corresponding to a channel in the radio side frame. A radio side upper address control unit 23, a radio side lower address control unit 24 that generates an in-channel address of the radio side frame, and a 1/2 frequency divider 25 that generates a signal having a period twice that of the radio side frame. A counter start timing generation unit 26 for generating a start timing of a counter for generating a ground side lower address, a parallel / serial conversion unit 27 for converting parallel output data from the dual port RAM 1 into serial data, and a ground frame Upper address on the ground side that generates an address corresponding to the channel of A control unit 28, a terrestrial side lower address control unit 29 for counting the ground side frame.
[0010]
The dual port RAM 21 has a configuration of 4096 words × 4 bits / word, and in this example, the data input / output is a 4-bit parallel. For example, two addresses are added to quadruple the depth of the dual port RAM 21 and It can be used as a safe data input / output.
[0011]
The operation of this example will be described below. The input serial radio side format data signal 100 is converted in parallel by the serial / parallel converter 22 and stored in the dual port RAM 21. The write address at this time is designated by the address signal 106 output from the radio side upper address control unit 23 and the address signal 107 output from the radio side lower address control unit 24. The relationship between the wireless-side format and the wireless-side upper address signal 106 and the wireless-side lower address signal 107 is as shown in the upper part of FIG. That is, the radio side lower address 107 is counted up from 0 to 31 in the time slot.
[0012]
FIG. 10 shows the configuration of the radio side lower address control unit 24. In FIG. 10, a timing signal generation circuit 44 generates an ENABLE signal every time the radio side frame signal 102 is input, and generates a LOAD signal when the radio side frame 1/2 frequency division signal 108 is input. The cycle of the radio side frame 1/2 frequency-divided signal 108 is twice the cycle of the radio side frame signal 102. When the ENABLE signal and the LOAD signal are input, the 1/64 counter 45 repeats the transition from 0 to 31 32 times in synchronization with the wireless system clock 101 as shown in the upper part of FIG. Address 107 is generated. Further, when only the ENABLE signal is input, as shown in the upper part of FIG. 9, the radio side lower address 107 is generated that repeats the transition of 32 to 63 32 times. The radio side lower address control unit 24 repeats such an operation every time the radio side frame 1/2 frequency division signal 108 is input.
[0013]
On the reading side, the data at the address specified by the ground side upper address control unit 8 and the ground side lower address control unit 29 is read from the dual port RAM 21. At this time, the relationship between the terrestrial format and the terrestrial upper address 111 and terrestrial lower address 112 is as shown in the lower part of FIG. That is, the ground side upper address 111 transits from 0 to 63 corresponding to the time slots U00 to U63 of each ground format, and the ground side lower address 112 transits 32 times every two time slots of each ground format. The value depends on the position of the ground format. As shown in FIG. 9, in the third terrestrial format from the left end, the value of the ground side lower address 112 is 1, 0, 63, 62... 34, and 2 to 33 are missing numbers.
[0014]
A circuit configuration of the ground side lower address control unit 29 is shown in FIG. In FIG. 11, 1/64 counter 92 for address generation (radio side frame length / ground side frame length) is prepared, and as soon as data writing for every two time slots is completed on the radio side, counter start timing The counter start signal 109 is output from the unit 6 to the ground side lower address control unit 29. In response to this, the corresponding 1/64 counter 92 for two time slots is reset, and thereafter counted up every 125 μs (= terrestrial frame length). The 32 → 1 selector 93 switches the output of the 1/64 counter 92 every two time slots in the ground frame to generate the ground side lower address 112.
[0015]
The data 110 read from the dual port RAM 21 is serial-converted by the parallel / serial conversion unit 27 and output as the ground side format data signal 103. As described above, the data format conversion with the shortest delay is realized.
[0016]
[Problems to be solved by the invention]
However, in the above-described prior art 2, the format conversion is performed to minimize the delay time by switching the lower address on the reading side (ground side) for every two time slots in the ground side format. As shown in FIG. 11, the ground side lower address control unit 9 is complicated, and a large number of counters and selectors are required.
[0017]
SUMMARY OF THE INVENTION The main object of the present invention is to provide a data conversion circuit that achieves both minimization of delay required for data conversion from the radio side format to the terrestrial side format and minimization of an increase in circuit scale accompanying the realization of the function. There is.
[0018]
[Means for Solving the Problems]
The data conversion circuit according to the first aspect of the present invention provides data in the terrestrial side format so that the data in the radio side format concentrated on the radio side frame having a time length N times that of the terrestrial side frame is distributed and arranged in a plurality of frames. In a data conversion circuit in satellite communication for conversion to a dual-port RAM serving as a medium for data conversion, a frequency dividing circuit for generating a radio side frame frequency-divided signal having a cycle that is an integral multiple of the radio side frame, and the ground side Each time a terrestrial high-order address control unit that sequentially generates terrestrial high-order addresses corresponding to the time slots constituting the frame and resets the terrestrial high-order address in response to a terrestrial frame signal, It counts up to generate the ground side lower address, and when the radio side frame division signal is received, the ground side lower address The ground side lower address control unit that resets the wireless address, and the radio side upper address corresponding to the radio side frame when the carry signal is received in sequence, and the radio side upper address is reset in response to the radio side frame signal When receiving the terrestrial side frame signal and the terrestrial side frame signal, it generates a radio side lower address based on the value obtained by adding one to the terrestrial side lower address, and carries (N-1) the count at the time of counting up A radio side lower address control unit that outputs a signal to the radio side upper address control unit, and writes data in the radio side format to the address of the dual port RAM specified by the radio side upper address and the radio side lower address, The terrestrial side address is determined from the dual port RAM address specified by the ground side upper address and the ground side lower address. And wherein the reading the mat of the data.
[0019]
In the present invention, the lower address on the reading side (ground side) is fixed in the ground side frame (counts up every frame), and instead the address on the writing side (wireless side) is changed for each time slot on the wireless side. As a result, the write address is changed for each radio-side time slot to realize format conversion that minimizes the delay time. In other words, necessary data rearrangement is completed when data is written to the dual port RAM, and data rearrangement becomes unnecessary after data is read from the dual port RAM. As a result, it is possible to reduce the number of counters for generating the ground side lower address and the selection circuit thereof, which are conventionally necessary, and the circuit for format conversion with the same shortest delay can be realized with a smaller circuit scale.
[0020]
The data conversion circuit according to the second aspect of the present invention is arranged in a concentrated manner in the radio side frame having a time length N times that of the ground side frame, and the data in the radio side format including the non-data portion is distributed and arranged in a plurality of frames. In a data conversion circuit in satellite communication for converting data into ground format data, a data conversion medium for writing data in response to a write enable signal and reading data in response to a read enable signal A dual-port RAM, a write enable control unit that disables the write enable signal in the time slot portion of the non-data portion when the radio side frame signal is input, and enables the write enable signal only in the time slot of the data portion; When a frame signal is input, the time slot of the non-data part The read enable signal is disabled in the data portion, the read enable control unit that enables the read enable signal only in the time slot of the data portion, and the radio side frame division signal having a cycle that is an integral multiple of the radio side frame. The terrestrial upper address is sequentially generated corresponding to the peripheral circuit and the time slot that constitutes the terrestrial frame, but an unnecessary terrestrial upper address is generated for the time slot of the non-data portion and responds to the terrestrial frame signal. The terrestrial upper address control unit that resets the terrestrial upper address, and counts up each time a terrestrial frame signal is received to generate a terrestrial lower address. Terrestrial side lower address control unit that resets and wireless when a carry signal is received The radio side upper address corresponding to the frame is generated in sequence, but the radio side upper address is generated for the time slot of the non-data portion, and the radio side upper address is reset in response to the radio side frame signal. When receiving the terrestrial side frame signal with the upper address control unit, a radio side lower address is generated based on a value obtained by adding one to the terrestrial lower address, and a carry signal is generated at the (N-1) th count up. Wireless side lower address control unit for outputting the data in the wireless side format to the address of the dual port RAM specified by the wireless side upper address and the wireless side lower address, From the address of the dual port RAM specified by the upper address on the side and the lower address on the ground The format data is read out.
[0021]
In the present invention, in addition to the operation of the first invention, by controlling the output of the enable signal to the dual port RAM, even if the non-data portion is included in the radio side frame as for the control signal, etc. Data conversion can be performed in a form that excludes.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
The data conversion circuit of the present invention converts the data in the first format concentrated in the frame having a time length that is an integral multiple of the frame in the second format into the data in the second format so as to be distributed in a plurality of frames. A dual-port RAM comprising a dual-port RAM serving as a medium for data conversion, a means for sequentially transitioning a read upper address for the dual-port RAM for each structural unit of a frame of the second format; Means for fixing the read lower address to the frame number in the frame of the second format, and means for changing the write address for the dual port RAM for each distributed arrangement unit so that the read address can be read with the minimum delay time after the data is written. And is provided.
[0023]
【Example】
Next, embodiments of the present invention will be described with reference to the drawings.
[0024]
Also in the present invention, as in the prior art 2, FIG. 7 showing an image of general data format conversion between the wireless side format and the ground side format is applied. In FIG. 7, the radio-side format is composed of data with a frame period m of 4 ms, one frame with 64 time slots V00 to V63, and one time slot with 128 bits, and the ground-side format has a frame period of 125 μs and one frame The 64 time slots U00 to U63 and one time slot are composed of 4-bit data.
[0025]
One time slot in the radio side format, for example, 128 bits concentrated in V00, is distributed in 4 bits in each time slot U00 of 32 consecutive frames after 125 μs in the ground side format. In such data conversion between the wireless side format and the ground side format described above, it is necessary to correspond 64 ground side frames to 2 wireless side frames. This is because if the address is changed in the cycle of one radio side frame, data is overwritten, that is, a new data is written before it is read out, so that it must be changed in units of two radio side frames.
[0026]
In the present invention, the lower address on the reading side (ground side) is fixed in the ground side frame, that is, counted up in units of the ground side frame, and the lower address on the writing side (wireless side) is replaced with the time slot in the wireless side format. By loading into the dual port RAM 1 every time, format conversion with the shortest delay is realized.
[0027]
Referring to FIG. 1 showing an embodiment of the present invention, this data conversion circuit includes a dual port RAM 1 for temporarily storing data, a serial / parallel conversion unit 2 for converting serial input data into parallel data, and a wireless A radio upper address control unit 3 for generating an address corresponding to a channel in the side frame, a radio side lower address control unit 4 for generating an in-channel address of the radio side frame, and a signal having a cycle twice that of the radio side frame 1/2 divider circuit 5 that generates parallel data, parallel / serial converter 7 that converts parallel output data from dual port RAM 1 into serial data, and the ground side that generates an address corresponding to the channel of the ground frame It is composed of an upper address control unit 8 and a ground side lower address control unit 9 that counts ground frames. There. It should be noted that the counter start / timing generator 26 is removed from the data conversion circuit of the prior art 2 shown in FIG.
[0028]
The dual port RAM 1 has a configuration of 4096 words × 4 bits / word, and in this example, the data input / output is a 4-bit parallel, but for example, by adding two address lines, the depth of the dual port RAM 1 is quadrupled, It can be used as serial data input / output.
[0029]
Upon receiving the terrestrial frame signal 105, the radio side lower address control unit 4 responds to the radio side system clock 102 and adds a value obtained by adding one to the ground side lower address 112 output by the ground side lower address control unit 9. The radio side lower address 107 is counted up by 31 on the base. At the 31st count up, a carry signal is output to the radio side upper address control unit 3.
[0030]
When receiving the carry signal from the radio side lower address control unit 4, the radio side upper address control unit 3 generates a radio side upper address 106 of 0 to 63 in response to the radio side system clock 102. In response to the radio side frame signal 101, the radio side upper address 106 is reset.
[0031]
The ground side lower address control unit 9 counts up every time it receives the ground side frame signal 105 and generates a ground side lower address 112. Also, when the radio side frame 1/2 frequency division signal 108 is received, it is reset. Since the radio side frame 1/2 frequency-divided signal 108 has a cycle twice that of the radio side frame, the ground side lower address control unit 9 generates the ground side lower address 112 of 0 to 63.
[0032]
The terrestrial upper address control unit 8 generates the terrestrial upper address 111 corresponding to the time slots U00 to U63 in the terrestrial format in response to the terrestrial system clock 104. In response to the ground frame signal 105, the ground upper address 111 is reset.
[0033]
The operation of this embodiment will be described below. The input serial radio side format data signal 100 is converted into 4-bit data 109 by the serial / parallel converter 2 and written into the dual port RAM 1. The write address at this time is specified by the radio side upper address 106 output from the radio side upper address control unit 3 and the radio side lower address 107 output from the radio side lower address control unit 4. The relationship between the wireless-side format and the wireless-side upper address 106 and the wireless-side lower address 107 is as shown in the upper part of FIG.
[0034]
In FIG. 2, for example, 1 to 32 of the wireless side lower address 107 are transitioned from 1 to 32 when the wireless side upper address 106 is “0”, and the wireless side upper address 106 is “ 1 ”indicates that the wireless side lower address 107 transits from 1 to 32. That is, the radio side lower address 107 transits 32 times within the radio side upper address 106, but its value is shifted by one for each terrestrial side format. For example, in the first ground side format, the radio side lower address 107 is 1 to 32, and in the second ground side format, the radio side lower address 107 is 2 to 33.
[0035]
In FIG. 2, if the number of each upper frame is 0 to 63 (which is also the value of the ground side lower address 106 in FIG. 2), in order to convert the format with the shortest delay, for example, data in the time slot V02 in the radio side format When the ground side lower address 112 is “1”, 128 bits are written in the dual port RAM 1 and 4 bits are read out by the ground side lower address 112 of 2 to 33. Therefore, when the data of the time slot V02 is written to the dual port RAM 1, the radio side lower address 107 may be set to 2 to 33. The same applies to other time slots. Generally, when the ground side lower address 112 is i (i = 0 to 63), the radio side lower address 107 is changed to (i + 1) to ((i + 1) +32). Just do it.
[0036]
FIG. 3 shows a circuit configuration of the radio side lower address control unit 4 that realizes this operation. In FIG. 3, the ground side lower address 112 is set in the adder 41 and 1 is added. The timing signal generation circuit 42 generates a LOAD signal and an ENABLE signal in synchronization with the radio system clock 102 in response to the ground frame signal 105. As a result, the value set in the adder 41 is set in the 1/64 counter 43 for each ground side frame signal 105. The 1/64 counter 43 counts up 31 times from the set value in synchronization with the wireless system clock 102, thereby generating the wireless lower address 107.
[0037]
Each time the radio side lower address control unit 4 counts up 31 times, a carry signal is output to the radio side upper address control unit 3, and the radio side upper address control unit 3 counts up the radio side upper address 106 by one. The radio side upper address 106 transitions from 0 to 63, but is reset by the radio side frame signal 101.
[0038]
On the other hand, on the reading side, the data 110 of the address designated by the ground side upper address control unit 8 and the ground side lower address control unit 9 is read from the dual port RAM 1 in a 4-bit parallel manner. At this time, the relationship between the terrestrial format, the terrestrial upper address 111, and the terrestrial lower address 112 is as shown in the lower part of FIG. In the ground side frame, the ground side lower address 112 is fixed, and it can be seen that the ground side upper address 111 changes from 0 to 63 in this state. The data 110 read from the dual port RAM 1 is serial-converted by the parallel / serial conversion unit 7 and output as a ground format data signal 103.
[0039]
FIG. 4 shows a circuit configuration of the ground side lower address control unit 9. Although the conventional ground side lower address control unit 9 shown in FIG. 11 has a large circuit scale, the ground side lower address control unit 9 according to the present invention requires only one 1/64 counter 91. The 1/64 counter 91 is reset by the radio-side frame 1/2 frequency-divided signal 108 in synchronization with the ground-side system clock 104, and outputs the ground-side lower address 112 when the ground-side frame signal 105 is received.
[0040]
The terrestrial upper address control unit 8 generates a terrestrial upper address 111 that transitions from 0 to 63 in synchronization with the terrestrial system clock 104 for each terrestrial frame signal 105.
[0041]
According to the present embodiment, as described above, the radio side lower address control unit 4 shown in FIG. 3 can be configured by adding one 6-bit adder to the conventional circuit. Since the side lower address control unit 9 can greatly reduce the circuit, the entire data conversion circuit can be significantly reduced in circuit scale as compared with the prior art.
[0042]
[Other embodiments]
Next, as another embodiment of the present invention, the basic configuration is not different from the above embodiment, but there are portions other than data in the radio side format and the ground side format, that is, a control signal portion and a blank portion. A data conversion circuit that can cope with cases including the above will be described.
[0043]
FIG. 5 shows the configuration of this embodiment. As can be seen from the comparison with FIG. 1, the present data conversion circuit is obtained by adding a write enable control unit 10 and a read enable control unit 11 to the present data conversion circuit shown in FIG. Components other than the wireless upper address control unit 13 and the terrestrial upper address control unit 18 in FIG. 5 have the same functions as those of the components having the same names in FIG.
[0044]
When the wireless side frame signal 101 is input, the write enable control unit 10 disables the write enable signal 114 only for the time slot corresponding to the non-data portion included in the wireless side format, and is included in the wireless side format. The write enable signal 114 is enabled for the time slot corresponding to the data portion. The dual port RAM 1 writes data 109 in response to the write enable signal 114. The radio side upper address control unit 13 generates an unnecessary radio side upper address 106 for the time slot corresponding to the non-data portion included in the radio side format, and the radio side upper address control is performed for the remaining time slots. Similarly to the unit 3, a normal radio side upper address 106 is generated.
[0045]
When the ground side frame signal 105 is input, the read enable control unit 11 disables the read enable signal 115 in the time slot portion in the ground side format in which the non-data portions included in the wireless side format are distributed and arranged. The read enable signal 115 is enabled for a time slot corresponding to the data portion included in the side format. The dual port RAM 1 reads the data 110 in response to the read enable signal 115. The terrestrial upper address control unit 18 generates an unnecessary terrestrial upper address 111 for time slots corresponding to the non-data portion included in the terrestrial format, and terrestrial upper address control for the remaining time slots. Similarly to the unit 8, a normal ground side upper address 111 is generated.
[0046]
FIG. 6 shows the relationship between the radio side format and the radio side upper address 106 and the radio side lower address 107 and the relationship between the ground side format and the ground side upper address 111 and the ground side lower address 112 in this embodiment. FIG. 6 is basically the same as FIG. 2, but the non-data portion of 2 time slots is included in the radio side format. That is, of the 64 time slots constituting one frame of the radio side format, 62 time slots V00 to V61 are for data used for data transmission, but two time slots C00 and C01 are controlled. For signal. Therefore, in the data conversion circuit, only the time slots V00 to V61 are used, and the time slots C00 and C01 are handled as unused.
[0047]
The operation of this embodiment is the same as that shown in FIG. 1 except for the handling of non-data portions. The input radio-side format data signal 100 is converted into 4-bit data 109 by the serial / parallel converter 12 and written into the dual port RAM 1 in response to the write enable signal 114 output from the write enable controller 10. . The write enable signal 114 is disabled in time slots C00 and C01 indicating the control signal portion of the radio side format.
[0048]
The write address is specified by the radio side upper address 106 output from the radio side upper address control unit 13 and the radio side lower address 107 output from the radio side lower address control unit 14. The radio side upper address 106 is disabled as shown by dc (don't care) in the time slots C00 and C01 as shown in FIG. 6, and “0 to 61” corresponding to the time slots V00 to V61. Become. As a result, only the data of the time slots V00 to V61 is written to the address of the dual port RAM 1 designated by the radio side upper address 106 (0 to 61) and the radio side lower address 107.
[0049]
As shown in FIG. 6, the time slot configuration in the terrestrial side format is BLANK after the time slots U00 to U61. On the read side, data 110 is read from the dual port RAM 1 in response to the read enable signal 115 output from the read enable control unit 11, serially converted by the parallel / serial conversion unit 17, and output as the ground side format data signal 103. Is done. The read enable signal 115 is disabled in a time slot indicating BLANK in the ground format.
[0050]
The read address is specified by the ground side upper address 111 output from the ground side upper address control unit 18 and the ground side lower address 112 output from the ground side lower address control unit 19. The ground side upper address signal 111 is disabled as indicated by dc (don't care) in the BLANK time slot as shown in FIG. 6, and becomes 0 to 61 corresponding to the time slots U00 to U61. As a result, only the data of the time slots U00 to U61 are read from the dual port RAM 1 designated by the ground side upper address 111 (0 to 61) and the ground side lower address 112.
[0051]
As described above, according to the present invention, it is possible to perform format conversion in which the format to be converted is slightly changed.
[0052]
【The invention's effect】
As described above, according to the present invention, the lower address on the reading side (ground side) is fixed in the terrestrial frame (counts up every frame), and the address on the writing side (radio side) is replaced with the radio time slot instead. Since the format conversion with the shortest delay is realized by making the transition every time, it is possible to reduce the counter for generating the lower address on the ground side and the selection circuit thereof, which were conventionally required in large numbers. Further, conventionally, every time data for one time slot is written to the dual port RAM, the fact is notified to the reading side by a counter start signal. However, since the above-described configuration is adopted, the necessity is eliminated. The start timing generator is no longer needed. As a result, it is possible to achieve an effect that a format conversion circuit that achieves the same delay minimization can be realized with a smaller circuit scale.
[0053]
For example, when the radio side frame length is 4 ms and the ground side frame length is 125 μs, according to the prior art, 4000/125 = 32 counters are provided in the ground side lower address control unit as shown in FIG. Although 32 selectors are required, one counter is sufficient as shown in FIG. And the additional circuit required for that is only one adder to the radio | wireless lower address control part, as shown in FIG.
[0054]
It should be noted that the present invention is not limited to the above-described embodiments, and it is obvious that the embodiments can be appropriately changed within the scope of the technical idea of the present invention.
[Brief description of the drawings]
FIG. 1 is a diagram showing an embodiment of a data conversion circuit of the present invention.
FIG. 2 is a timing chart of the embodiment shown in FIG.
FIG. 3 is a configuration diagram of a radio side lower address control unit in the embodiment shown in FIG. 1;
4 is a configuration diagram of a ground side lower address control unit in the embodiment shown in FIG. 1;
FIG. 5 is a diagram showing another embodiment of the data conversion circuit of the present invention.
6 is a timing chart of the embodiment shown in FIG.
FIG. 7 is a diagram showing the concept of delay shortest format conversion
FIG. 8 is a diagram showing an example of a conventional data conversion circuit
9 is a timing chart of the conventional example shown in FIG.
10 is a configuration diagram of a radio side lower address control unit in the conventional example shown in FIG. 8;
11 is a block diagram of the ground side lower address control unit in the conventional example shown in FIG. 8;
[Explanation of symbols]
1,11,21 Dual port RAM
2,12,22 Serial / parallel converter
3, 13, 23 Wireless side upper address control unit
4, 14, 24 Wireless side lower address control unit
5, 15, 25 1/2 divider circuit
26 Counter start timing generator
7, 17, 27 Parallel-serial converter
8, 18, 28 Ground side upper address control section
9, 19, 29 Ground side lower address control section
10 Write enable controller
11 Read enable controller
41 Adder
42, 44 Timing signal generation circuit
43,45 1/64 counter
91,92 1/64 counter
93 32 → 1 selector

Claims (5)

In a data conversion circuit for converting data in a first format concentrated in a frame having a time length that is an integral multiple of a frame in a second format into data in the second format so as to be distributed in a plurality of frames,
A dual-port RAM serving as a medium for the conversion;
Means for sequentially transitioning the read upper address for the dual port RAM for each structural unit of the frame of the second format;
Means for fixing the read lower address for the dual port RAM to the frame number in the frame of the second format;
A data conversion circuit, comprising: means for making a transition for each distributed arrangement unit so that a write address for the dual port RAM can be read with a minimum delay time after the data is written. In a data conversion circuit in satellite communication for converting data in a radio side format concentrated in a radio side frame having a time length N times that of a ground side frame into data in a ground side format so as to be distributed in a plurality of frames,
A dual port RAM as a medium for the conversion;
A frequency dividing circuit for generating a radio side frame frequency-divided signal having a cycle that is an integral multiple of the radio side frame;
A terrestrial upper address control unit that sequentially generates a terrestrial upper address corresponding to a time slot constituting the terrestrial frame, and resets the terrestrial upper address in response to a terrestrial frame signal;
Counting up each time the ground side frame signal is received to generate a ground side lower address, and receiving the radio side frame frequency division signal, the ground side lower address control unit that resets the ground side lower address;
A radio side upper address control unit that sequentially generates a radio side upper address corresponding to the radio side frame when receiving a carry signal, and resets the radio side upper address in response to the radio side frame signal;
When the terrestrial frame signal is received, a radio side lower address is generated based on a value obtained by adding one to the terrestrial lower address, and the carry signal is transmitted to the radio at the (N-1) th count up. A radio side lower address control unit that outputs to the side upper address control unit, and writes the data in the radio side format to the address of the dual port RAM specified by the radio side upper address and the radio side lower address A data conversion circuit for reading data in the terrestrial format from an address of the dual port RAM specified by the terrestrial upper address and the terrestrial lower address. Satellite communication that is centrally arranged in a radio side frame having a time length N times that of the ground side frame and converts data in the radio side format including a non-data portion into data in the ground side format so as to be distributed in a plurality of frames. In the data conversion circuit in
A dual port RAM which writes data in response to a write enable signal, reads data in response to a read enable signal and serves as a medium for the conversion;
A write enable control unit that disables the write enable signal in the time slot portion of the non-data portion when a radio side frame signal is input, and enables the write enable signal only in the time slot of the data portion;
A read enable control unit that disables the read enable signal in the time slot portion of the non-data portion when the ground side frame signal is input, and enables the read enable signal only in the time slot of the data portion;
A frequency dividing circuit for generating a radio side frame frequency-divided signal having a cycle that is an integral multiple of the radio side frame;
A terrestrial upper address is sequentially generated corresponding to the time slots constituting the terrestrial frame, but an unnecessary terrestrial upper address is generated for the time slot of the non-data portion, and in response to the terrestrial frame signal, A terrestrial upper address control unit for resetting the terrestrial upper address;
Counting up each time the ground side frame signal is received to generate a ground side lower address, and receiving the radio side frame frequency division signal, the ground side lower address control unit that resets the ground side lower address;
When a carry signal is received, the radio side upper address corresponding to the radio side frame is sequentially generated, but an unnecessary radio side upper address is generated for the time slot of the non-data portion, and the radio side frame signal is responded. A wireless upper address control unit for resetting the wireless upper address,
When the terrestrial frame signal is received, a radio side lower address is generated based on a value obtained by adding one to the terrestrial lower address, and the carry signal is transmitted to the radio at the (N-1) th count up. A radio side lower address control unit that outputs to the side upper address control unit, and writes the data in the radio side format to the address of the dual port RAM specified by the radio side upper address and the radio side lower address A data conversion circuit for reading data in the terrestrial format from an address of the dual port RAM specified by the terrestrial upper address and the terrestrial lower address. The radio side lower address control unit
An adder that adds only one when the ground side lower address is set;
A timing signal generation circuit that generates a LOAD signal and an ENABLE signal in response to the ground frame signal;
A value set in the adder is set for each terrestrial frame signal in response to the LOAD signal and the ENABLE signal, and the radio is counted up (N-1) times from the set value. 4. The data conversion circuit according to claim 2, comprising a counter that generates a side lower address. 3. The ground side lower address control unit is configured by a counter that is reset by the radio side frame frequency division signal and outputs the ground side lower address when a ground side frame signal is input. Item 5. The data conversion circuit according to Item 4.

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