JP3038809B2 - Signal conversion circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal conversion circuit, and more particularly, to an input signal in which a plurality of data signal sequences are time-division multiplexed in one frame, and a phase of each input data signal sequence. The present invention relates to a signal conversion circuit that outputs a plurality of output data signal strings in parallel regardless of the relationship.

[Conventional technology]

FIG. 3 is a block diagram showing a conventional signal conversion circuit of this kind.
The arrangement and timing of the data signal sequence are shown in the timing chart of FIG. As shown in FIG. 4, the input time-division multiplexed multiplexed data signal D1
It is assumed that three data 1, data 2, and data 3 are serially arranged in a frame. The conventional circuit shown in FIG. 3 includes a RAM 7 for writing and reading such a multiplexed data signal D1 for each of data 1, 2, and 3, and an externally input timing for determining the beginning of a frame of the multiplexed data signal D1. A signal generator 8 for generating a write timing signal T1 for writing to the RAM 7 at the beginning of each frame based on the signal S1,
The head of three parallel output data signal sequences D2, D3, D4,
A signal generator 9 for generating a read signal T2 from the RAM 7 based on an externally input timing signal S2 for determining the head of data 1, and a read data signal for data 1, 2,
The circuit includes shift circuits 10, 11, and 12 for sequentially shifting data in units of three, and a signal processing circuit 6 for processing the parallel output data signal strings D2, D3, and D4 for every three groups.

Next, the signal conversion timing in the conventional example will be described with reference to FIG. The multiplexed data signal D1 input in synchronization with the timing signal S1 is written into the RA by the write timing signal T1.
Data 1 to data 3 are sequentially written to M1. Next,
Read timing signal synchronized with timing signal S2
Read from RAM7 by T2. At this time, the difference θ in the positional relationship between the write and read timing signals T1 and T2 is temporarily stored and shifted under control conditions such that writing and reading can be performed in the RAM 7, and data 3 is temporarily stored in the shift circuit 10. At this stage, the data signal strings D4 (data 3), data signal strings D3 (data 2) and data signal strings D2 (data 1) are almost aligned from the shift circuits 10, 11, 12 as shown in FIG. Output in parallel. According to such a procedure, three groups from the group of data 1 to the group of data 3 are output for each frame in parallel.

[Problems to be solved by the invention]

The conventional signal conversion circuit described above has only one RAM, and in digital signal processing, when data signal conversion is performed, there are always restrictions on the delay time θ for writing and reading data to and from the RAM. There is a disadvantage that the timing is inevitably delayed and a delay of approximately 1.5 to 2 frames occurs. As the number of data signal strings increases and the data lengthens, the number of shift circuits increases, the circuit scale increases, and the delay time to the signal processing circuit increases.

[Means for solving the problem]

The signal conversion circuit of the present invention includes a plurality of dual-port RAMs for writing and reading a plurality of data multiplexed into an input multiplexed data signal for each of the data, and a data signal for the plurality of dual-port RAMs. A first signal generating means for generating a common write signal for simultaneously writing data, and an arbitrary delay time corresponding to a processing request of a signal processing circuit corresponding to each of the dual port RAMs and a delay time of the data signal. The read signal for reading the written data is minimized by the dual port
And second signal generating means for generating the same number as the number of RAMs.

〔Example〕

Next, the present invention will be described with reference to the drawings. First
1 is a block diagram of an embodiment of the present invention.
The figure is a timing chart in the case where a multiplexed data signal obtained by multiplexing three data signals of the present embodiment is converted into a data signal sequence of three groups. In the embodiment of FIG. 1, the RAMs 1, 2, and 3 which are dual port RAMs for writing and reading the multiplexed data signal D1 as in the conventional example and the timing signal S1 for determining the head of the data 1 of the multiplexed data signal. Signal generators 4 and 3 that generate a write timing signal T1
A signal generator 5 that generates read signals T2-1, T2-2, and T2-3 of RAMs 1, 2, and 3, respectively, based on a timing signal S2 and a timing signal S1 that determine the beginning of the data signal strings D2, D3, and D4.
And a signal processing circuit 6. Here, the dual-port RAM is a RAM having an input port for an input data signal and an output port for an output data signal, respectively, and capable of simultaneously performing writing and reading.

Next, the operation of this embodiment will be described with reference to FIGS. The multiplexed data signal D1 input in synchronization with the timing signal S1 is written into the RAM1, RAM2,
Write to RAM3. Next, the data signals D2, D3, and D4 output in synchronization with the timing signal S2 are read and the timing signal T2 is read out.
Read from RAM1, RAM2, RAM3 by -1, T2-2, T2-3.
Here, since RAM1,2,3 are dual port RAM, RAM1, RAM2, RAM3 can be used regardless of the positional relationship of timing signals S1, S2.
Can be written and read. Note that the multiplex data signal D1
Are simultaneously written to the RAMs 1, 2, and 3 by the common timing signal T1. Since the read timing signals T2-1, T2-2, and T2-3 are provided corresponding to the RAMs 1, 2, and 3, the data signal train D2
(Data 1) is read with a small delay time θ2 within one frame from T1, and a data signal string D3 (data 2) is read from RAM2.
Can be read from T1 with a delay time θ3, and the data signal sequence D4 (data 3) can be read from RAM3 with a delay time θ4. That is, the delay times θ2, θ3, and θ4 can be read within an arbitrary delay time according to the processing request of the signal processing circuit 6. According to this configuration, as shown in FIG. 2, data 1 in the multiplexed data signal is output to the data signal sequence D2 at least one frame earlier than in the conventional circuit configuration. That is, the data delay for one frame is eliminated. Furthermore, even if the length of the data in the multiplexed data signal changes, the circuit configuration does not need to be changed, and only the read timing signals T2-1, T2-2, and T2-3 need to be changed.

〔The invention's effect〕

As described above, the present invention reduces the delay time of a written data signal by using a plurality of dual-port RAMs and having a signal generator that generates a read timing signal in each RAM. There is an effect that can be. Further, even if the configuration or length of the data signal changes, there is no need to increase the circuit scale or change the circuit, and there is the effect that the same circuit configuration can be used.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a time chart of this embodiment, FIG. 3 is a block diagram of a conventional signal conversion circuit, and FIG. 4 is a time chart of a conventional example. 1,2,3 ... Dual port RAM, 4,5 ... Signal generator, 6
…… Signal processing circuit, 7… RAM, 8,9 …… Signal generator, 1
0,11,12 ... Shift circuit.

──────────────────────────────────────────────────続 き Continuation of front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H04J 3/00-3/26 H03M 9/00

Claims (1)

(57) [Claims] 1. A plurality of dual-port RAMs for writing and reading a plurality of data multiplexed to an input multiplexed data signal for each data, and simultaneously writing data signals to the plurality of dual-port RAMs. A first signal generating means for generating a common write signal; and an arbitrary delay time corresponding to a processing request of a signal processing circuit corresponding to each of the dual port RAMs and a minimum delay time of the data signal. And a second signal generating means for generating the same number of read signals for reading the written data as the dual port RAM.