JP2888048B2 - Time division demultiplexing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time division multiplexing / demultiplexing circuit, and more particularly to a time division multiplexing / demultiplexing circuit used in a time division multiplexing communication device and the like, which can use both time division multiplexing and separation.

[0002]

2. Description of the Related Art A conventional time-division multiplexing circuit of this kind is shown in FIGS.
The configuration shown in FIG. 7 is general.

FIG. 4 is a block diagram showing a case where the number of channels of a conventional time division multiplexing circuit is four. Channel (C
H) First-in / first-out memory 9 (hereinafter, referred to as FIFO) that receives signal 101 and performs speed conversion. Similarly, FIFOs 10-12 corresponding to CH2-4
And a selector 13 for time-division multiplexing the output signals of the FIFOs 9 to 12. The FIFOs 9 to 12 receive the signals of the respective channels and the write clock 105, the write control signal 114, the read clock 107, and the read control signal 113. ing. The selectors (SEL) 13 have FIFOs 9-1.
2 and a plurality of selection signals 115 and 116 are input.

FIG. 5 is a timing chart of FIG. The write control signals of the FIFOs 9 to 12 corresponding to each channel are controlled, and data is written simultaneously for four channels (time T1 in FIG. 4). Subsequently, a read control signal 110 of the memory 9 corresponding to CH1 is controlled to read a signal corresponding to CH1 and select signals 115 and 116 of SEL13.
To select the output signal of the FIFO 9 (time T2 in FIG. 5). Similarly, the read control signal 111 of the FIFO 10 is controlled to read data and
To select the output signal of the FIFO 10 (see FIG. 4).
Time T3). Thereafter, the operations for four channels are sequentially performed in the same manner, so that the selector 13 outputs the time-division multiplexed signal 20.
9 is output.

FIG. 6 is a block diagram showing a case where the number of channels of the conventional time division multiplexed signal separation circuit is four. In FIG. 6, the selector (SEL) 14 has switching control signals 215, 2
The multiplexed signal 109 input by 16 is converted into four FIFOs.
15, 16, 17, 18 are input. FIFO15-1
Reference numeral 6 writes a time-division multiplexed signal with a common write block 205 and write control signals 210 to 213 corresponding to the respective channels, and outputs a signal written to the FIFO with a common read clock 207 and read control signal 214.

FIG. 7 is a timing chart of FIG. At time T1 in FIG. 7, the SEL 14 switches so that the input multiplex signal 109 is input to the FIFO 15,
CH1 is determined by the write clock 205 and the write control signal 210.
Is written into the FIFO 15. Next, at time T2, S
The EL 14 switches so that the input multiplexed signal is input to the FIFO 16, and writes the CH2 signal to the FIFO 16 by the write clock 205 and the write control signal 211.
Similarly, at time T3, the signal of CH3 is written to the FIFO 17 in the FIFO, and at time T4, the signal of CH4 is written to the FIFO 18.

After the writing of the signals of each channel to the four FIFOs 15 to 18 is completed, at time T5, the signals of each channel are simultaneously read out and output from the four FIFOs 15 to 18 by the read clock and the read control signal, whereby the multiplexed signal is output. It is separated into signals for each channel.

[0008]

As described above, in the conventional circuit, the read control signal or the write control signal of the FIFO is required for the number of channels, the control signals of the selectors are also required, and the scale of the control signal generation circuit is required. There is a problem that becomes large. Further, since the time division multiplexing circuit and the time division signal separation circuit are separate circuits, there is a problem that the efficiency of design and production is not good.

[0009]

According to a time division multiplexing / demultiplexing circuit of the present invention, n input signals from a first to an n-th (n is an integer) are written by a first write control signal, respectively. The first to n-th n values to be read out by the read control signal, respectively.
First-stage first-in / first-out memory,
The signals read from the n pre-stage first-in / first-out memories are respectively written by a second write control signal and read out by a second read-out control signal. A first-out memory, an output terminal of a k-th (k is an integer, k <n) number of the n subsequent first-in / first-out memories,
Connection lines for connecting the input side of the first post-first-in / first-out memory, respectively.

In this time division demultiplexing circuit, the n
When the input signals are respectively input to the first to n-th first-in / first-out memories, the first to n-th input signals are output from the output side of the first post-stage first-in / first-out memory. When a multiplexed signal obtained by time division multiplexing is output and the multiplexed signal is input to the n-th pre-stage first-in / first-out memory, the n-th first to n-th post-stage first-in / first-out memory From each output side, each signal corresponding to the first to n-th input signals obtained by separating the multiplexed signal is output.

[0011]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a case where the number of channels is four in this embodiment. FIFO1 to FIFO4 before receiving the CH signal 101 to CH4 signal 104 and performing speed conversion.
There are FIFOs 5 to 8 at the subsequent stage for performing time division multiplexing or separation. The common write clock 105 and write control signal 106 and the common read clock 107 and read control signal 108 as well as the signals for the first to fourth FIFO channels are input. However, when used as a separation circuit, only the FIFO 4 is used for speed conversion. FIFO 5 to 8 have speed-converted signals, common write clock 205 and write control signal 206, and common read clock 207 and read control signal 20.
8 has been entered. The output of FIFO8 and the input of FIFO5 are similarly connected.

Next, the operation of the multiplex circuit in FIG. 1 will be described with reference to FIG. The write control signals 106 of the FIFOs 1 to 4 are controlled, and signals for 1 to 4 channels are transmitted to the FIFOs.
Each of the data is taken into 1 to 4 (time T1 in FIG. 2). Subsequently, the data written at time T1 is controlled by the read control signal 108 to simultaneously read data of channels 1 to 4. FIFO
FIFO5 to 8 in accordance with the read timing from 1 to 4
And the signal corresponding to CH1 is stored in FIFO5, and the signal corresponding to CH2 is stored in FIFO6.
Similarly, the signal corresponding to CH4 is written to FIFO8 (time T2 in FIG. 2).

The data in FIFO5 is output at time T3, and the data in FIFO6 is written into FIFO5.
The data of FO7 is written to FIFO6, and the data of FIFO8 is written to FIFO7. (Time T in FIG. 2
3). The above operation is repeated and the data of CH1 to CH4 becomes FI
Multiplexed signal 209 written to FO5 and sequentially read out by read control signal 208 (T3 to T6) and time-division multiplexed
Is output as

Next, the operation of the separation circuit in FIG. 1 will be described with reference to FIG. The multiplexed signal 109 is controlled by controlling the common write control signal 106 of the FIFOs 1-4.
(Time T1 to T4 in FIG. 3). Subsequently, time T1 to T
4 is controlled by the read control signal 108 to read FIFO data (time T2 to T5). FI
F is stored in FIFO3 in accordance with the readout timing from FO4.
Write the data of FIFO8 to FIFO7,
Is written with CH2 data. By the same operation, T5
Since the data of each channel is written to each FIFO,
At T6, the multiplexed signal is read out by the FIFOs 5 to 8 to separate the multiplexed signal into original data.

[0016]

As described above, the time-division multiplexing / demultiplexing circuit of the present invention employs a configuration of a first-stage FIFO and a second-stage FIFO, thereby reducing the types of read control signals or write control signals and simplifying control. And the scale of the external control signal generator can be reduced. Further, since the same circuit can be used as a multiplexing circuit or a separating circuit, there is an effect of improving design and production efficiency.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a timing chart when FIG. 1 is used as a multiplexing circuit.

FIG. 3 is a timing chart when FIG. 1 is used as a separation circuit.

FIG. 4 is a block diagram showing a conventional time division multiplexing circuit.

FIG. 5 is a timing chart of FIG.

FIG. 6 is a block diagram showing a conventional time-division signal separation circuit.

FIG. 7 is a timing chart of FIG.

[Explanation of symbols]

1-8 First In First Out Memory (FIFO)

Claims (2)

(57) [Claims] The first to n-th input signals are written by a first write control signal and read by a first read control signal, respectively, from n to n (n is an integer) input signals. a first read-in signal which is written by a second write control signal and a read-out signal is read by an n first-stage first-in / first-out memory and a second read-out control signal, respectively; To n-th subsequent first-in / first-out memory;
The output side of the k-th (k is an integer, k <n) post-stage first-in / first-out memory of the first-out memory is connected to the input side of the (k-1) -th post-stage first-in / first-out memory, respectively. A time division multiplexing / demultiplexing circuit comprising a connection line. 2. When the n input signals are respectively input to first to n-th first-in / first-out memories, the first to n-th first-in / first-out memories output the first to n-th first-in / first-out memories from the first to n-th first-in / first-out memories. A multiplexed signal obtained by time-division multiplexing the nth input signal is output, and when the multiplexed signal is input to the nth preceding first-in / first-out memory, the n first to nth subsequent stages are output. The first to n-th separated multiplexed signals from each output side of a first-in first-out memory
2. The time division multiplexing / demultiplexing circuit according to claim 1, wherein each signal corresponding to the input signal is output.