JPH0563673A - Time division multiplex circuit - Google Patents

Abstract

PURPOSE:To reduce number of control signals by providing a time division multiplex memory which connects a speed conversion memory and plural first-in first-out memories directly and multiplexing signals to the circuit. CONSTITUTION:A write control signal 1 of a memory 1 is controlled to write signals for 8 channels to the memory 1. Succeedingly, data by 8 channels written in the memory 1 are read simultaneously by controlling the read control signal 1. A write control signal 2 of a memory 2 is controlled in matching with a read timing to write data corresponding to a channel 1 to an internal memory 21, to write data corresponding to a channel 2 to an internal memory 22,..., and to write data corresponding to a channel 8 to an internal memory 28. In this case, the read control signal 2 of the memory 2 is inhibited to bring an output of the memory 2 to a high impedance. Then a time division multiplex signal is being outputted as output data of the memory 2 by shifting data corresponding to each channel into the memory 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for time division multiplexing signals of a plurality of channels into one signal.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing the structure of a conventional time division multiplexing circuit.

This time division multiplexing circuit is provided corresponding to the data of eight channels, and is given a channel data, a write clock, a write control signal, a read clock and a read control signal to each of them. The memories 51, 52, ... 58 and the first-in / first-out memories 51, 52, ...
The selector 4 receives the data read from 58 and a plurality of selection signals and generates a multiplexed signal.

FIG. 6 is a timing chart showing the operation of the conventional time division multiplexing circuit.

The write control signals of the memories 51 to 58 corresponding to the respective channels are controlled to simultaneously write data for eight channels (time T1). Then, the read control signal of the memory 51 corresponding to the channel 1 is controlled to read the data corresponding to the channel 1 and the selection signal of the selector 4 is controlled to select the output signal of the memory 51 (time T2).
Similarly, the read control signal of the memory 52 is controlled to read the channel 2 data and the selector 4 selects the output signal of the memory 52 (time T3). Similarly, when the operation for 8 channels is performed, the time-division multiplexed signal is output from the selector 4.

[0006]

However, in such a conventional circuit, the first-in / first-out memory for receiving the data for a plurality of channels and converting the transmission rate is required for the number of channels, and the read-out is required. There is a problem in that control signals are required for the number of channels and a plurality of control signals for the selector for time division multiplexing are required.

An object of the present invention is to eliminate such problems and to provide a time division multiplexing circuit in which the number of control signals is reduced.

[0008]

According to the present invention, there is provided a time division multiplexing circuit having an output terminal for outputting multiplexed data having a single channel number obtained by converting data assigned to a plurality of channels. A first control for receiving a write control signal and one first read control signal, and for simultaneously reading the data of a plurality of channels written in response to the first write control signal in response to the first read control signal. Memory and
An internal memory provided corresponding to the data of the plurality of channels and connected in series is provided, and one second write control signal and one second read control signal are provided, and the second read control signal is prohibited. Under the state, the data read from the first memory is written in response to the second write control signal of the timing which coincides with the timing of the first read control signal, and the data is read under the prohibited state of the first read control signal. In response to the second read control signal, the data written in one of the internal memories is read out and given to the internal memory whose input is connected to the output of the internal memory, and the output is connected to the output terminal. And a second memory for giving the data written in the internal memory to the output terminal.

Here, it is desirable that the internal memories included in the first memory and the second memory are first-in first-out memories.

Further, in a circuit for time-division-multiplexing signals of a plurality of channels, a first-in-first-out circuit for receiving a plurality of channel signal outputs and converting a transmission rate.
A plurality of first-in first-out memories having a plurality of memory units and converting a plurality of signals whose speeds have been converted from the connections of the outputs of the n-th internal memories of the respective memory units into one time division multiplexed signal. It is characterized by having a memory unit connected in series.

[0011]

[Function] The first memory, which is composed of a first-in first-out memory, etc., simultaneously writes and reads data of a plurality of channels by the first write and read control signals. The second memory which is connected in series with each other and is associated with the data of a plurality of channels sets the second read control signal to the disabled state, writes the plurality of channel data read from the first memory to the corresponding internal memory, Since the read control signal of the memory is disabled and the multi-channel data written in the second memory is sequentially shifted and read out to the output terminal, the multi-channel data written in the first memory is stored in one It can be output as multiplex data.

Alternatively, when there are a plurality of first-in / first-out memory units for receiving a plurality of channel signal outputs and converting the transmission rate, the n-th internal memory of each transmission rate conversion memory section group is included. The time-division multiplexing memory unit configured by connecting in series the first-in first-out memory connected corresponding to each output of the n-th channel by connecting the outputs to each other is the channel signal of the memory unit group for the transmission speed conversion. Since the output is shifted and output, the group data of the plurality of transmission rate conversion memory units can be output as one time division multiplexed signal.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a time division multiplexing circuit according to a first embodiment of the present invention.

In the first embodiment, as shown in FIG. 1, the number of channels is 8 and the data for 8 channels and the write clock 1, the write control signal 1, the read clock 1 and the read control signal 1 are input to correspond to the channels. Memory 8 for outputting each of the above data, and eight memories 21 to 28 of first-in / first-out provided for each data corresponding to the channel, including a write clock 2, a write control signal 2, a read clock 2 and a read. A memory 2 to which a control signal 2 is applied. That is, an output terminal for outputting multiplexed data having a single channel number obtained by converting data assigned to a plurality of channels is provided, and further, one first writing is provided as a feature of the first embodiment of the present invention. Control signal 1 and one first read control signal 1
And a plurality of (8) channels that have been simultaneously written in response to the first write control signal 1 and data of a plurality of (8) channels that are simultaneously read in response to the first read control signal 1. 8) provided with eight internal memories 21 to 28 which are provided corresponding to the data of the channel and are connected in series, and are supplied with one second write control signal 2 and one second read control signal 2. (2) Under the prohibited state of the read control signal 2, the data read from the memory 1 is written in response to the second write control signal 2 of the timing which coincides with the timing of the first read control signal 1, and the first read control signal Under the prohibited state of 1, the internal memory 2 is responsive to the second read control signal 2.
The data written in one of the Nos. 1-28 is read out and given to the outputs of the internal memories 21-28 to the internal memory having its input connected, and written in the internal memory having its output connected to the output terminal. A memory 2 for giving data to this output terminal. Here, the memory 1 and the internal memory 21
28 is a first-in first-out memory.

FIG. 2 is a diagram showing the operation timing of the time division multiplexing circuit according to the first embodiment of the present invention.

Next, the operation of the first embodiment will be described with reference to FIGS.
Will be described.

By controlling the write control signal 1 of the memory 1, 8
The signals for the channels are written in the memory 1 (time T1). Subsequently, at time T1, the data of 8 channels written in the memory 1 are simultaneously read by controlling the read control signal 1. The write control signal 2 of the memory 2 is controlled according to the timing of reading, and the data corresponding to the channel 1 is stored in the memory 21.
The data corresponding to channel 2 is stored in the memory 22, the data corresponding to channel 3 is stored in the internal memory 23, the data corresponding to channel 4 is stored in the internal memory 24, the data corresponding to channel 5 is stored in the internal memory 25, and the channel 6 is stored. Corresponding data is written to internal memory 26, data corresponding to channel 7 is written to internal memory 27, and data corresponding to channel 8 is written to internal memory 28 (time T2). At this time, the read control signal 2 of the memory 2 is prohibited so that the output of the memory 2 becomes high impedance. Next, the write control signal 2 and the read control signal 2 of the memory 2 are controlled to control the time T2.
Read the data written in. At this time, the read control signal 1 of the memory 1 is prohibited and the output of the memory 1 is set to high impedance. The data read from the internal memory 28 is written in the internal memory 27. Similarly, internal memory 2
The data read from 7 is stored in the internal memory 26, the data read from the internal memory 26 is stored in the internal memory 25, the data read from the internal memory 25 is stored in the internal memory 24,
The data read from the internal memory 24 is stored in the internal memory 23.
First, the data read from the internal memory 23 is written in the internal memory 22, and the data read from the internal memory 22 is written in the internal memory 21 (time T3). At this time, the data read from the internal memory 21 is output as a multiplexed signal. Similarly, by controlling writing and reading, the data corresponding to each channel is shifted in the memory 2 so that the time division multiplexed signal is output from the internal memory 21 as memory output data as shown in the lower part of FIG. It will be output.

Next, the time division multiplexing circuit of the second embodiment will be described with reference to the drawings.

FIG. 3 is a block diagram showing a case where the number of channels of the time division multiplexing circuit according to the second embodiment of the present invention is 16.

There are a memory for receiving signals for 16 channels and speed conversion, a memory, and a memory for time division multiplexing. A signal for 1 to 8 channels and a write clock, a write control signal, a read clock, and a read control signal are input to the memory, and a signal for 9 to 16 channels, the same write clock, write control signal as the memory, A read clock and a read control signal are input. A speed-converted signal of each channel, a write clock, a write control signal, and a read control signal are input to the memory. First-in first-out memory (hereinafter abbreviated as FIFO) FIFO
Connect O4, FIFO12 and memory output to
The outputs of O5 and FIFO13 are connected to be the input of FIFO37, and next, FIFO6, FIFO14 and FIFO36.
Make the same connection as below.

FIG. 4 is a diagram showing the operation timing of the time division multiplexing circuit according to the second embodiment of the present invention.

Next, the operation will be described with reference to FIGS.

Memory, write control signals for the memory are controlled to output signals for 1 to 8 channels to the memory, 9 to 16
The signal for the channel is taken into each internal memory of the memory (FIG. 4, time t1). Then, the data written in the memory at time t1 is controlled by the read control signal to
~ Read data for 8 channels. The write control signal of the memory is controlled according to the timing of reading from the memory, the signal corresponding to the channel 1 is directly output as a multiplex output, and the signal corresponding to the channel 2 is output to the FIFO 37.
The signal corresponding to channel 3 is written to FIFO 36, and the signal corresponding to channel 8 is written to FIFO 31 (FIG. 4, time t2). At this time, the memory is prohibited from being read by the read control signal.

Next, the memory is controlled by a write control signal and a read control signal, the output of the memory is prohibited by setting it to a high impedance, and the data read from the FIFO 31 is written in the FIFO 32. Similarly F
The data read from the IFO 32 is transferred to the FIFO 33,
... The data read from the FIFO 36 is the FIFO 3
7 is written and shifted (FIG. 4, time t3). At this time, the data read from the FIFO 37 is output as a time division multiplexed signal. By the above operation, the data of channels 1 to 8 are time-division multiplexed. After time t10, reading of the memory is disabled, and the signals of channels 9 to 16 can be time-division multiplexed by performing the above-described operation between the memories. By time t17, data for 16 channels can be multiplexed. Can be time-division multiplexed.

The case where the number of channels is increased to 16 has been described above as an example. However, even if the number of channels is further increased by the method according to the embodiment, there is an advantage that it can be dealt with by similarly increasing the speed conversion memory. ..

[0027]

As described above, in the time division multiplexing circuit of the present invention, the read control signal of the first-in / first-out memory can be reduced, the read control can be simplified, and the read control signal generating circuit of the memory can be realized. The scale can be reduced. Further, since the number of channels can be increased by increasing the number of memory units for speed conversion, the circuit scale of the memory unit can be minimized.

[Brief description of drawings]

FIG. 1 is a block diagram of a time division multiplexing circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an operation timing of the time division multiplexing circuit according to the first exemplary embodiment of the present invention.

FIG. 3 is a block diagram showing a case where the number of channels of the time division multiplexing circuit according to the second embodiment of the present invention is 16.

FIG. 4 is a diagram showing an operation timing when the number of channels of the time division multiplexing circuit according to the second exemplary embodiment of the present invention is 16.

FIG. 5 is a block diagram showing a configuration of a conventional time division multiplexing circuit.

FIG. 6 is a diagram showing operation timing of a conventional time division multiplexing circuit.

[Explanation of symbols]

 1 First Memory 2 Second Memory 21-28 Internal Memory, Speed Conversion Memory Time Division Multiplexing Memory 30-37 Time Division Multiplexing Internal Memory

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Shunji Sato 3-20-4 Nishishinbashi, Minato-ku, Tokyo Inside NEC Engineering Co., Ltd. (72) Inventor Atsushi Nakamichi 4-2 Shimomata, Kakegawa-shi, Shizuoka Shizuoka Inside NEC Corporation

Claims (3)

[Claims] 1. A time division multiplexing circuit having an output terminal for outputting multiplexed data having one channel number converted from data assigned to a plurality of channels, wherein one first write control signal and one first write control signal are provided. A first memory for simultaneously reading data of a plurality of channels, which are simultaneously written in response to the first write control signal, in response to the first read control signal; and the plurality of channels. Of the internal memory connected in series and corresponding to the data of 1), one second write control signal and one second read control signal are given, and the second read control signal is inhibited under the above-mentioned condition. One of the data read from the first memory is written in response to the second write control signal having a timing that coincides with the timing of the one read control signal, and the first read control signal is in the prohibited state. In response to the second read control signal, the data written in one of the internal memories is read out and given to the internal memory whose input is connected to the output of the internal memory, and the output is connected to the output terminal. And a second memory for giving the data written in the internal memory to this output terminal. 2. The time division multiplexing circuit according to claim 1, wherein the internal memories included in the first memory and the second memory are first-in first-out memories. 3. A circuit for time-division-multiplexing signals of a plurality of channels, having a plurality of first-in first-out memory units for receiving a plurality of channel signal outputs and converting a transmission rate, the n-th memory unit. The output of the second internal memory is characterized by having a memory unit in which a plurality of first-in first-out memories are connected in series to convert a plurality of speed-converted signals from one connection to another into a single time division multiplexed signal. Split multiplex circuit.