JPH0194731A - Time-division multiplexing device - Google Patents

Abstract

PURPOSE:To execute economical interconnection by providing multiple FIFO buffers and converting the each channel of a time-division multiple signal at one side into the each channel of the time-division multiple signal at the other side through these buffers. CONSTITUTION:A signal is received at a multiple separating circuit 20a, and at the circuit 20a, a channel signal classified with a channel number is separated based on corresponding information in communication in a holding memory 24. The signal classified with the channel number is stored in each buffer corresponding to the channel number out of FIFO buffers 21a-22a the number of which is the same as that of the channels. Next, the channel signal stored in the buffer corresponding to the channel number is selected out of the buffers 21a-22a based on the corresponding information of the channel number and the FIFO number in a holding memory 25 and transmitted to an internal bus 11 through a bus connecting circuit 23a. Thus, the time-division multiplexing system having two different forms can be interconnected.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to a communication system that accommodates a plurality of lines that perform multiplex transmission of a plurality of channels using a time division multiplexing method, and interconnects the multiplexed channels between the lines. The present invention relates to a time division multiplexing device as a device, and in particular to a circuit that converts multiplexed signals when interconnecting lines with different time division multiplexed signal formats.

(Prior Art) FIG. 3 shows the configuration of a conventional time division multiplexing device. In FIG. 2, (1) is a time division multiplexing device, (2) is a communication line, (4a), (4b) ), (5a),
(5b) is a terminal. In the figure, two time division multiplexing devices (1) are connected by a communication line (2), and data from a plurality of terminals is transmitted by time division multiplexing, whereby terminals (4a) and (5a), (4b) and (5b) communicate with each other.

Here, the time division multiplexing device (1) is configured to perform communication by putting terminal data in frames divided into fixed lengths on a communication line (2). Generally, the time length of a frame is 125 μs, and when using a communication line at 1.544 Mbit/sec, one frame consists of 193 bits, and each bit of the frame can carry 8 bits/sec of data. . However, multiplexing using bits within a frame as the minimum unit is inefficient for low-speed terminals. Therefore, a method is used in which a certain number of consecutive frames are collected to form a multiframe, and data from low-speed terminals is allocated and transmitted within this multiframe.

FIG. 4 shows an example of transmission using this multiframe. In Figure 4, (δ) is a frame, (7) is a terminal (
4a) data, (8) is the data of terminal (4b), (9
) indicates multi-frame. Multi frame (9
) is generally composed of 20 or 24 consecutive frames (6), and here we will consider the case of a multi-frame (9) composed of 20 frames (6). In this case, the cycle of one multiframe (9) is 2.516S. In FIG. 4, a terminal (4a) having a speed of 2.4 bits/sec generates 6 bits of data (7) to be transmitted during one multiframe time (2.5 m5). Similarly, at 4.8 bit/sec terminal (4b) generates data (8) to be transmitted in 12 bits within the same time. Fourth
In the figure, data (7) of terminals (4a) and (4b).

In (8), there are 6 bits and 12 bits in each multiframe (9), and in the multiframe (9), each bit is sequentially transferred from the first frame (6) to the subsequent frames (
6).

Furthermore, FIG. 4 shows the internal configuration of the time division multiplexing device (1), in which (10a) and (fib) are terminal interfaces, (11) is an internal bus, and (12) is a communication line interface. . Terminal interfaces (10a) and (10b) connect terminals (4a) and (4) respectively.
b) and holds it until the transmission timing of the communication line (2) comes. The internal bus (11) operates in synchronization with the multiframe (9) in Fig. 5, and when the transmission timing of the terminal (4a) arrives on the communication line (2), data is transmitted from the terminal interface (10a). The data is read out to the internal bus (11), and the data is transferred from the internal bus (11) via the line interface (12) to the communication line (2).
sent to. The above is a description of the conventional time division multiplexing device (1).

[Problem that the invention seeks to solve]

By the way, in a system using such a time division multiplexing device (1), it may be necessary to interconnect systems with different multiplexing formats. In Figure 6, (4
c), (4d), (5c), (5d) are terminals, (13) and (14) are time division multiplex communication systems,
Both systems have different multiplex formats, and these two systems (13) and (14) are connected via a terminal interface. That is, the connection method is such that when viewed from one system, the other system appears to be a terminal.

Furthermore, Figure 7 shows two systems (13) and (14
) shows the details of the connection part. In Figure 7, (
10c) , (IQd) , (L5c) , (1
5d) are terminal interfaces, (16c) respectively.
, (16d) shows the cable connecting the two systems. Such a method has the disadvantages of requiring a large number of cables when a large number of terminals are connected between two systems, and the disadvantage of requiring a large number of terminal interface cards in each system. In order to connect division multiplex systems, a time division multiplexer (1) for both systems is required at the connection point, which has the disadvantage of being uneconomical.

The present invention has been made to overcome the drawbacks of such conventional systems, and its purpose is to transfer information carried in the multiframe (9) of one time division multiplexing system to the multiframe (9) of the other system. By replacing it with 9),
The purpose is to enable communication between terminals connected to both systems (13) and (14).

[Means for Solving the Problems] A time division multiplexing device according to the present invention is a communication device accommodating a plurality of communication lines that multiplex transmits information of a plurality of channels by time division. A FIFO buffer that is allocated to each channel and holds data in the order in which it is input for each channel and outputs it in this order, and a holding memory that holds the correspondence between the channel number multiplexed on the communication line and the FI"FO buffer 1 number. , a holding memory that receives information on a communication line and holds the above-mentioned correspondence from the channel number to which the information belongs; a demultiplexing circuit that calculates a corresponding FIFO buffer number and stores the received information in the FIFD buffer; When outputting information, calculate the FIFO buffer 1 number from the channel number,
It includes a bus connection circuit that reads data from the FIFO buffer and transmits it as channel information of the communication line, and also transmits channel information of any communication line to the FIFO buffer.
The time division multiplexing, holding and converting circuit includes a control circuit that stores data in an IFO buffer and controls reading of data from the FIFO buffer when channel information is transmitted over another communication line.

(Operation) The time division multiplex signal conversion circuit in this invention has a large number of FIs.
An FO buffer is provided to convert each channel of one time-division multiplexed signal to each channel of the other time-division multiplexed signal through the buffer to achieve economical interconnection.

〔Example〕

FIG. 1 shows the configuration of a communication system in an improved time division multiplexer, and (17) in the figure is a time division multiplex signal conversion circuit according to the present invention. In the illustrated system, the time division multiplex signal conversion circuit (17) directly converts one time division multiplex signal into the other time division multiplex signal, so the time division multiplexer (1) of both systems is required at the connection point. A similar function can be performed without using the two systems, and the time division multiplex signal conversion circuit (17) according to the present invention may be installed in one device of one system. There are also two systems (13), (1
4), the communication line (2) of one system is simply connected directly to the time division multiplex signal conversion circuit (17), so there is no need for many cables or terminal interface cards as in conventional systems. .

FIG. 2 shows a time division multiplex signal conversion circuit (1) according to the present invention.
7) shows the internal structure. In Figure 2, (20
a), (20b) are demultiplexing circuits, (21a) ~
(22a), (21b) ~ (22b) are FI
FO buffer, (23a).

(23b) is a bus connection circuit, (24) and (25) are holding memories that hold correspondence information between channel numbers and FIFO numbers on the communication line side and internal bus side, respectively;
6) is a control circuit.

Here, FIFO buffer y (21a) ~ (22a)
and (21b) to (22b) exist in the same number as the arbitrary number of channels. That is, when there are n channels, the FIFO buffer y (21a) to (22a)
There are n pieces of FIFO buffer y (21b) ~ (2
There are also n pieces of 2b). The time division multiplexed signal of the communication line (2) is first received by the demultiplexer circuit (20a), where it is separated into channel signals for each channel number based on the correspondence information between channel numbers and FIFO numbers on the communication line side. Then, the channel signal for each channel number is stored in each FIFO buffer corresponding to the channel number from among the FIFO buffers (21a) to (22a) of the same number as the number of channels.

Next, the channel signal stored in the FIFO buffer corresponding to the channel number is assigned from the channel number determined by the transmission timing based on the correspondence information between the channel number on the internal bus side and the FIFO number in the holding memory (25). The number of FIFO buffers to be used is the same as the number of channels.
One bit is selected from among the buffers (21a) to (22a), taken out from the FIFO buffer, and transmitted to the internal bus (11) via the bus connection circuit (23a).

On the other hand, the data sent from the internal bus (11) is
First, it is received by the bus connection circuit (23b), and based on the correspondence information between channel numbers and FIFO numbers on the internal bus side, FIFO buffers (21b) of the same number as the number of channels are received.
) to (22b) are stored in each FiFO buffer corresponding to the channel number. Next, the channel signal stored in the FIFO buffer corresponding to the channel number is stored in the corresponding FIFO buffer from the channel number determined by the transmission timing based on the correspondence information between the channel number on the communication line side and the FIFO number. F of
One bit is selected from the IFO buffers (21b) to (22b), taken out from the FIFO buffer, passed through the demultiplexing circuit (20b), and becomes a time division multiplexed signal, which is transmitted to the communication line (2). .

Note that in the above description, the demultiplexing circuit (20a) is referred to as the demultiplexing circuit (20a).

(20b), and bus connection circuit (23a), (
23b) are used separately for uplink and downlink, but the present invention is not limited to this.
3a) and (23b) may be shared.

Further, a time division multiplex signal conversion circuit (17) according to the present invention
It is also possible to realize it with LSI.

〔Effect of the invention〕

As described above, in this invention, by using a time division multiplex signal conversion circuit, time division multiplex systems having two different formats can be interconnected without using a terminal interface, and the system can be configured economically. There are advantages that can be achieved.

[Brief explanation of the drawing]

Fig. 1 is a system configuration diagram showing an embodiment of this invention;
Figure 3 is an internal configuration diagram of a time division multiplex signal conversion circuit, Figure 3 is a configuration diagram of a conventional time division multiplexing device, Figure 4 is an explanatory diagram showing an example of multiframe transmission, and Figure 5 is a time division multiplexing diagram. FIG. 6 is an internal configuration diagram of the device; FIG. 6 is a configuration diagram showing an example of interconnection between systems with different multiplexing formats using a conventional device; and FIG. 7 is a configuration diagram showing a connection between two systems with different multiplexing formats. In the figure, (1) is a time division multiplexing device, (2) is a communication line, (4a), (4b), (4c), (
4d), (5a), (5b). (5c) and (5d) are terminals, (13) and (14
) is a time division multiplex communication system, (17) is a time division multiplex conversion circuit, and (20a). (20b) is a demultiplexing circuit, (21a), (21b
), (22a). (22b) is a FIFO buffer, (23a) (23b
) is a bus connection circuit, (24) and (25) are holding memories, and (26) is a control circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] In a communication device that accommodates multiple communication lines that multiplex transmit information on multiple channels by time division, a FIFO that is assigned to each of the multiple channels on each communication line, holds data in the order in which it is input for each channel, and outputs it in this order.
Buffer, holding memory that holds the correspondence between the channel number multiplexed on the communication line and the FIFO buffer number, holding memory that receives information on the communication line and holds the above correspondence from the channel number to which the information belongs. , a demultiplexing circuit that calculates the corresponding FIFO buffer number and stores the received information in the FIFO buffer; when outputting information to a communication line, calculates the FIFO buffer number from the channel number, reads data from the FIFO buffer, and performs the communication. It includes a bus connection circuit that transmits channel information of a line, stores channel information of an arbitrary communication line in the FIFO buffer, and controls reading of data from the FIFO buffer when transmitting channel information on another communication line. A time division multiplexing device comprising a time division multiplexing holding conversion circuit comprising a control circuit.