JPH0258940A - Time division multiplexer - Google Patents

Abstract

PURPOSE:To flexibly deal with a branch service and a faced connection by separating the signals of the multiframe phases of different frames mixedly existing in the same frame and executing a multiframe phase matching. CONSTITUTION:By a line interface part 2, a frame synchronization control is executed, and the synchronizing bit insertion information and compulsory designated instruction information of a channel control part 12 is set-changed according to a transmission service to be applied. A multiframe synchronizing bit inserting part 13 inserts a multiframe synchronizing bit into the signal bit of a signal bit string according to the synchronizing bit insertion information among them, and a compulsory signal processing part 14 changes the unused slot of the frame of each line into a prescribed value according to the compulsory designated instruction information. Thus, a necessity to change the line interface part according to the applied transmission service is eliminated, it can be dealt with by the rewrite of control information, and further, the constitution of the line interface part can be simplified.

Description

[Detailed Description of the Invention] [Industrial Field of Application] This invention is a system that time-division multiplexes the signals output from each terminal when a plurality of terminals transmit and receive data using a line such as a high-speed digital line. This relates to a time division multiplexing device for sending out data to a line.

[Conventional technology]

FIG. 5 is a block diagram showing the configuration of this type of conventional time division multiplexing device. In the figure, (10) is a time division multiplexing device, (1) is a line termination device (hereinafter referred to as DSU) such as a high-speed digital line provided by Nippon Telegraph and Telephone Corporation, etc., (2) ) is a line interface unit that controls transmission and reception when transmitting and receiving data to and from a high-speed digital line via the DSU (1);
3) is a terminal device, (4) is a terminal interface unit that sends and receives data to and from the terminal device (3), and (5) is a time division multiplexing unit from each line interface unit (2) or each terminal interface unit (4). This is a time slot converter (hereinafter referred to as TSI) that exchanges the time slots of a signal. In addition, in the TSI (5), (6) is a communication path memory, (7) is an address counter that specifies the address of the communication path memory (6), and (8) is a counter that controls the count value of the address counter (7). control unit,
(21) is where the TSI (5) outputs transmission data, and the terminal interface section (4) and line interface section
(2) The transmit data bus, where (
22), the terminal interface section (4) and the line interface section (5) output the received data, and the TSI (
5) is a receive data bus that accesses received data.

Furthermore, FIG. 6 is an example of a frame structure on a 1,544 Kbps digital transmission service that is exchanged between conventional time division multiplexers (1o). (31) is the frame synchronization bit used for frame synchronization, (32) is 20
Multi-frame synchronization bit used for multi-frame synchronization, (33) is a frame, (34) is an 8-bit time slot that makes up frame (33),
(35) is a multiframe consisting of 20 frames (33).

Next, the operation will be explained. A frame (33) consists of a 1-bit frame synchronization pin 1-(31) and 24 time slots (34). One bit out of 192 bits is used as a multiframe synchronization bit (32). In the illustrated example, the first bit of the first time slot T S I (34) of the frame (33) is the multi-frame synchronization bit (32). A code having one period of 20 frames is used for the multi-frame synchronization bit (32), and a multi-frame (35) composed of 20 frames is 2.5 m5ec. Therefore, using 1 bit in multiframe (35), 2.5 m
Since there is 1 bit per 5ec, it is possible to transmit information at 400 bps, which is 400x n bps (n i, 2
...m), it is sufficient to allocate n bits of the multiframe (35).

Next, in FIG. 5, when a frame (33) is manually input from o S U (1), the line interface section (2) synchronizes the frame using the frame synchronization bit (31), and then synchronizes the frame using the multi-frame synchronization bit. (3
2), 20 multi-frame synchronization is achieved. In addition, each terminal interface section (4) time-division multiplexes input signals (speeds differ depending on the terminal) from the plurality of terminals (3) connected to it while maintaining frame synchronization and multiframe synchronization. . The line interface unit (2) and the terminal interface unit (4) transmit the processed signal to the TSI (5) via the reception data bus (22).
).

TSI (5) is the time slot (3
4) and outputs it to the line interface section (2) or terminal interface section (4) via the transmission data bus (21). Line interface section (2
) takes in the signal sent from TSI (5),
A frame synchronization bit (31) and a multiframe synchronization bit (32) are inserted into the data and sent to DSU (1). The terminal interface unit (4) takes in the signals on the transmission data bus (21), performs frame synchronization phase control and multi-frame phase control, and transmits the signals to each terminal (3).
Separate the data into separate data and transfer the separated data to the terminal (3)
, and sends it to the terminal (3).

The TSI (5) transfers the multi-frame synchronized data bits output from each line interface section (2) and each terminal interface section (4) to two of the TSI (5) indicated by the address counter (7). The information is sequentially written into one channel memory (6a) which has a two-dimensional configuration. After writing the output from each interface section for one frame, the counter control section in TSI (5)
According to the command (8), when sequentially reading the data written to the communication path memory (6a), the order of the addresses of the communication path memory (6a) to be accessed is changed, and the address order of the communication path memory (6a) is changed.
Transfer the data in 6a) to the line interface section (2)
Then, it is transmitted to the terminal interface unit (4). In addition,
The communication path memory (6b) on the other side performs an operation opposite to that of the above-mentioned communication path memory (6a).

[Problem to be solved by the invention]

Conventional time division multiplexing devices are configured as described above, so for example, when using the branching service described in "Technical reference material for high-speed digital transmission services, 2nd edition" published by Nippon Telegraph and Telephone Corporation, At each branch point on a high-speed digital line, only the frame synchronization of the human-powered frames from each line is performed, and the human-powered data from each line is simply logically ANDed and output, so the time division multiplexing device on the transmitting side , the bits in the frame (33) that are not related to the own communication
1'' and not transmitting, there was a problem in that it would interfere with communication between other time division multiplexers on the same line using the branch service.

In addition, in the case of transmission using a branching service, data sent from multiple time division multiplexers with different multi-frame phases coexists on the same frame.
As in a conventional time division multiplexer, the frame (33)
If the multiframe synchronization bit (32) in the frame is used to synchronize all data bits within a frame, it is impossible to synchronize each data bit on the frame, and branching services It may not be applicable. To solve this problem, the time division multiplexer needs to insert a multiframe synchronization bit (32) into each time slot group (hereinafter referred to as a channel) of a frame (33) for each branch destination during transmission. Furthermore, during reception, it is necessary to add a circuit for determining the multi-frame synchronization bit (32) added to each channel within the frame and a multi-frame alignment circuit for the received data.

Therefore, a circuit for inserting a multi-frame synchronization bit (32) into each channel to which frame (33) is allocated in line interface section (2), and
It is conceivable to add a circuit that inserts "1" into all bits of unused channels in 3), but this would increase the amount of hardware in each line interface section (2).
Furthermore, if it is not applied to branching services, the cost of the line interface section (2) will be relatively high due to the extra circuitry, and one time-division multiplexing device usually requires 10
Since only a few lines are supported, there is a problem in that the price of the device as a whole becomes relatively high in proportion to the number of lines supported.

This invention was made to solve the above problems, and can flexibly support branching services and opposite connections.
Moreover, it is an object of the present invention to obtain a time division multiplexing device that can realize the above functions at a low cost.

[Means to solve the problem]

The time division multiplexing device according to the present invention includes synchronization bit insertion information indicating the insertion point of a multi-frame synchronization bit in a multiplexed signal bit string, and forcibly changing the signal bit inside the signal bit string to a predetermined value. a communication path control unit that holds and can change forced setting instruction information indicating that a multiframe synchronization bit is to be set, a multiframe synchronization bit insertion unit that inserts a multiframe synchronization bit into a signal bit string according to the synchronization bit insertion information; A forced signal processing unit that changes signal bits according to instruction information is installed inside the TSI,
Alternatively, it is provided independently from this TSI.

[Effect]

In this invention, the line interface section performs frame synchronization control, and changes the settings of synchronization bit insertion information and forced specification instruction information of the channel control section according to the transmission service to be applied, such as for branching services. According to the insertion information, the multiframe synchronization bit insertion unit inserts the multiframe synchronization bit into the signal bit of the signal bit string, and according to the forced specification instruction information, the forced signal processing unit inserts an unused time slot of each line frame into a predetermined value. Change to

(Example) An embodiment of the present invention will be described below.

In FIG. 1 and FIG. 5, which shows a conventional device, the same reference numerals indicate the same elements. Other than these (11) are each line interface section (2)
Alternatively, it is a multiframe control unit that performs multiframe synchronization control of time division multiplexed signals from each terminal interface unit (4).

In addition, FIG. 2 is a diagram showing the detailed configuration of TSI (5), and (6) has data of bpsX n at 8 and 0.4
a channel memory for exchanging data of Kbps x n;
(12) is a communication path control unit that controls communication path memory (6), etc.; (13) is a multiframe synchronization bit insertion unit; (13) is a multiframe synchronization bit insertion unit;
14) is a forced signal processing unit that inserts "1" into the bits of unused channels, and (15) is a manual input to the channel memory (6) for data with only frame synchronization and data with multiframe synchronization. A selector that selects (41
) is a multi-frame memory in the multi-frame control unit (11), (42) is a multi-synchronization detection/protection unit that performs multi-frame synchronization detection and protection, and (43) is a multi-frame memory control unit.

In addition, the line interface section (2
) does not perform multi-frame synchronization control, but only performs frame synchronization control. Furthermore, although not shown in FIGS. 1 and 2, the communication path control unit (12) is a CPU that monitors the status of the entire time division multiplexing device (IO).
According to the control information sent from this CPU, the communication path memory (6), multi-frame control section (11), multi-frame synchronization bit insertion section (13), forced signal processing section (14) , controls the selector (15).

FIG. 3 shows an example of this control information. (100) is control information, (101) to (107) are this control information (100)
), in which (101) is the TSI information via the transmission data bus (21) or the reception data bus (22).
(5) Input/output line/terminal interface unit number indicating the destination or source of input/output data, (102)
is 8 KbpsX n or 0.
4 is the time slot conversion information used to exchange data of bps
), forced setting instruction information indicating the position of the bit in the frame to be forcibly set to "1", (105) is multiframe bit extraction instruction information indicating the extraction location of the multiframe synchronization bit, and (106) is The multiframe channel number indicates which channel's data bits are to be multiframe aligned based on the multiframe synchronization bit indicated by the multiframe bit insertion/extraction instruction information (103), and (107) is a signal that requires multiframe synchronization control. This is multi-frame synchronization necessity information indicating whether or not. In addition, the numbers at the left end of the figure are the consecutive bit numbers for the entire multiplexed signal output to TSI (5),
Alternatively, it is a timeslot number.

When the multi-frame synchronization necessity information (106) indicates that it is not necessary (when the human input signal is 8 bpsX n), the input signal from the reception data bus (22) to the TSI (5) is directly into the channel memory (6).

Next, the operation will be explained. First, the overall data signal flow will be explained. The line interface unit (2) performs frame synchronization using a frame synchronization bit (31) in response to a human input signal from the DSU (1) to the line interface unit (2). In addition, the terminal interface section (4) performs frame synchronization and time-division multiplexing of input signals from the terminal (3) to the terminal interface section (4) (speeds differ depending on the terminal) while also maintaining multi-frame synchronization. . The line interface section (4) is
Output the processed signal onto the reception data bus (22) and
SI (5) takes in the signal on the reception data bus (22).

TSI (5) is 8 Kbps of the captured signal.
The Xn signal is input directly to the communication path memory (6),
0.4Kbpsx requiring multi-frame alignment
After the multi-frame phase of each signal is matched in the multi-frame control unit (11), the n signals are input to the communication path memory (6). In the channel memory (6), each frame (33) has 8 KbpsX n and 0.4
The signals of bps X n are exchanged between frames (
(Hereinafter, this will be referred to as time slot conversion), and each frame (33)jI consisting of a time slot converted signal
At the L position, a multiframe synchronization bit inserting section (13) inserts a multiframe synchronization bit (32) at a necessary location according to the communication path control section (12), and then inserts a multiframe synchronization bit (32) at a necessary location according to the communication path control section (12).
) to all unused bits of each frame (33)
is set and output on the transmission data bus (22). Each line interface section (2) has a transmission data bus (2
1) The upper line interface unit takes in the signal destined for (2), inserts the frame synchronization bit (31), communication bit (S bit), etc. at the beginning of the frame (33), and
Send to S U (1). The terminal interface section (4) takes in the signal on the transmission data bus (21), takes out the data to be sent to the terminal (3), converts the taken data to the speed of the terminal (3), and sends it to the terminal (3). do.

The operation of the TSI (5) will be described in more detail below, taking as an example when the frame shown in FIG. 4 is manually input from the line interface section (2) and when it is output to the line interface section. The frame (33) shown in FIG. 4 consists of a collection of three types of time slots (34). A collection of homogeneous time slots (34) is hereinafter referred to as a channel.

Channel 1 has the first time slot (34a) (
Hereinafter, the nth time slot (34) will be referred to as TSn) to the time slot (34e) of T S 5 (34e).
4), and channel 2 consists of T S 6 (34f)
channel 3 consists of TSI5 (34m) from TSI5 (34m).
It consists of S 1B (34n) to T S 24 (34h). Furthermore, in this example, channel 2 is an unused channel that is not used for communication between this time division multiplexer (10) and other time division multiplexers (IO). It is assumed that the first bit of the TSI (34a) of channel 1 is allocated to the multiframe synchronization bit (32a) and is used for multiframe synchronization control of the signal on channel 1.

Similarly, it is assumed that the first bit of T S lli (34n) of channel 3 is allocated to the multiframe synchronization bit (32n) and is used for multiframe synchronization control of the signal on channel 3. The multi-frame channel number (106) corresponds to channels 1, 2, 3, . . . described above.

A. Operation line interface section when outputting a frame from TWI Frame (33) shown in Figure 4 is sent to (2) from TWI.
The operation when outputting from SI (5) is shown below.

■, The first bit of T S 1 (34a) is
When outputting from (5) to the line interface section (2) indicated by the input/output line terminal interface section number (101) in the control information (11), the communication path control section (12)
The multiframe synchronization bit insertion unit (13) operates according to the multiframe bit insertion instruction information (103) of the control information (100) in the bit (1), and sets the multiframe synchronization bit in the bit (1) and outputs it. . After that T.S.
5 (34e) until the last bit in the channel memory (6) according to the time slot conversion information (102).
The time slot converted signal is output as is.

00 Next, when outputting the first bit of T S 6 (34f), forced setting information is output. This operation follows the forced setting information (104) and T S 15 (34m)
continues until the last bit.

■, T S 18 (When the first bit of 34ml is output, the multiframe synchronization bit insertion unit (13) operates again according to the multiframe bit insertion instruction information (103), and performs multiframe synchronization on the bit. Set the bit and output from TSI (5).After that,
The signal that has been time-slot-converted in the channel memory (6) using the time-slot conversion information (102) up to the last bit of T S 24 (34h) is directly transferred to the TSI (S
) is output.

■The frame (33) is then output to another line interface section (2) or terminal interface section (4)
In accordance with the control information (100) in the channel control section (12), the channel memory (6) performs time slot conversion, the multiframe synchronization bit insertion section (13) inserts a multiframe synchronization bit, and Forced signal processing section (
14), “1” is forcibly inserted.

In addition, in the case of a frame (33) that does not require the insertion of the multi-frame synchronization bit (32), that is, a frame (33) in which only a signal of bps When involved in communication between a division multiplexer (10) and another time division multiplexer (10), multi-frame bit insertion instruction information (10
3) According to the forced setting instruction information (104), the multi-frame synchronization bit insertion unit (13) and the forced signal processing unit (14) do not operate, and the multi-frame synchronization bit is inserted into the relevant frame (33). , force “1”
” is never set.

B. Operation when inputting a frame to the TSI Line interface section The operation when the frame (33) shown in FIG. 4 is manually input from (2) to the TSI (5) is shown below.

■The first bit of T S 1 (34a) is TSI (
5), multiframe bit extraction instruction information (105) and multiframe channel number (106) are received.
), the multiframe synchronization detection/protection unit (42) extracts the corresponding bit as a multiframe synchronization bit,
The multi-frame synchronization of the channel is detected, and the synchronization state of channel 1 is detected by the multi-frame memory control unit (4
3) Notify.

(2) The multi-frame memory control unit (43) holds a modulo 20 frame counter (not shown in FIG. 2) for each channel indicated by the multi-frame channel number (108), The human signals of the channel are written in the area of the multi-frame memory (41) indicated by the signal frame counter in the order of input. As a result, multi-frame alignment of signals for each channel is achieved. Note that when a signal from a channel that is out of synchronization is input, a certain specific value, for example, logic "1" is written instead of the input signal, and the input signal is squelched.

(2) When reading out the signals in the multi-frame memory (41), they are read out in the input order starting from frame number 1 of the channel indicated by the multi-frame channel number (106). After reading out the signal of frame number 0 of all frames, the signal of frame number 1 is next read out, and when the signal of frame number 20 of all frames has been read out, the signal of frame number 1 is read out again.

■The signal read from the multi-frame memory (41) is processed according to the multi-frame synchronization necessity information (107).
A selection is made by the selector (15) as to whether or not to input the call path memory (6) manually. In other words, the signal read from the multi-frame memory (41) becomes 0.4 b/sxn
If the terminal (3) is assigned to transmit a signal with a speed of 8 Kb/s 3), the selector (15) selects the input from the receive data bus (22) without multi-frame synchronization delay and stores it in the channel memory (6). Manpower. Note that the selector (
Naturally, the two-way input signals selected in step 15) are those at the same bit position on the same time slot output from the same line interface section (2) or terminal interface section (4).

Note that in the above embodiment, the multiframe synchronization bit insertion unit that inserts the multiframe synchronization bit, the forced signal processing unit, the multiframe control unit that performs multiframe alignment of all signals manually input to the time division multiplexing device, etc. Although it is provided in the slot conversion section, the same effect can be obtained even if it is provided independently in addition to the time slot conversion section.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the line interface section does not perform multi-frame synchronization control, but controls related to multi-frame control, and
Equipped with a device that sets and inserts instruction information into unused bits when using branching services, and enables multi-frame phase matching by separating signals with multi-frame phases of different frames coexisting within the same frame. Therefore, there is no need to change the line interface section depending on the applied transmission service, such as branching service, and it can be handled by rewriting the control information.Furthermore, the configuration of the line interface section is simplified, which keeps equipment costs low. It has the effect of being able to

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.
FIG. 2 is a block diagram showing the detailed configuration of the main elements of the embodiment, FIG. 3 is a diagram showing an example of the configuration of control information for explaining the operation of the embodiment, and FIG. 4 is a block diagram showing the detailed configuration of the main elements of the embodiment. FIG. 5 is a block diagram showing the configuration of a conventional time division multiplexing device; FIG. 6 is a diagram showing the frame configuration to explain the operation of the device. . (l...Terminal device, (2...Line interface section, (3)...Terminal device, (4...Terminal interface section, 5...Time slot conversion section, 6)...Telephone call path memory, 10... time division multiplexing device, 11)... multi-frame control section, 12... speech path control section, (13... multi-frame synchronization bit insertion section, (14)...
. . . Forced signal processing unit, (21 .

Claims (1)

[Claims] The terminal interface section converts the signal from the terminal into a time division multiplexed signal, and swaps the time slots between this time division multiplexed signal and the time division multiplexed signal from the line input via the line interface section. , in a time division multiplexing device that sends the switched time division multiplexed signal to a designated interface section, synchronization bit insertion information indicating the insertion point of a multi-frame synchronization bit in a multiplexed signal bit string; A channel control unit that holds forced setting instruction information that indicates forcibly changing a signal bit to a predetermined value and is capable of changing the same; It includes a multi-frame synchronization bit insertion section that inserts into a bit string, and a forced signal processing section that changes the signal bit according to the forced setting instruction information, frame synchronization control is executed by the line interface section, and the system At the same time, the multi-frame synchronization bit insertion section inserts a multi-frame bit into the time slot on the frame of each line, and the forced signal processing section inserts the multi-frame synchronization bit into the unused time slot of the frame of each line. A time division multiplexing device characterized in that the time division multiplexing device changes the value to a predetermined value.