JP3492006B2 - Communication device and communication method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication device and a communication method thereof, for example, to communication performed by connecting to a plurality of logical lines.

[0002]

2. Description of the Related Art As a digital communication line consisting of an information channel and a signal channel, an ISDN interface has been standardized in ITU-T and its practical use is being promoted.

As a communication terminal that handles media such as voice and video by using this ISDN service, there is a multimedia communication terminal typified by a videophone. Such multimedia communication terminals communicate with each other by using a common function among the mutual functions. Therefore, it is necessary for such multimedia communication terminals to have a common transmission frame structure for multiplexing signals of respective media such as voice, video and other data on the communication line. This transmission frame structure is defined in ITU-T Recommendation H.221, and various transmission modes between terminals communicating with each other are defined in ITS-TS Recommendation H.242.

FIG. 1 is a diagram showing an example of a transmission frame structure defined by Recommendation H.221. FAS shown in the figure is a frame synchronization signal and is composed of framing information, control information, alarm information and the like. Further, BAS shown in the figure is a bit rate allocation signal, and is composed of a terminal capability for structuring channels in a frame in various ways. The configuration that consists of 80 bits in the vertical direction corresponding to the octet number shown in the figure is called a subchannel.
1, sub-channel # 2, ..., Sub-channel # 8 are numbered sequentially. However, in the sub-channel # 8, the first 16 bits are assigned to FAS and BAS, and thus the remaining 64 bits form data.

Data of each medium to be transmitted is assigned in subchannel units. When transmitting frame structure data according to Recommendation H.221, FAS and BAS are added to each frame one by one. As for a frame, a sub multi-frame is composed of a pair of an even frame and an odd frame, and further, a multi-frame is composed of eight sets of sub multi-frames. FAS and BAS are defined by a pair of an even frame and an odd frame, and a bit pattern of a frame synchronization word called FAW is inserted in the FAS of the even frame and the FAS of the odd frame. As shown in Fig. 2, the FAW bit pattern has octets # 2 to # 8 of even frames of '0011.
At 011 ', octet # 2 of odd frame becomes'1'.

In the multimedia communication according to the above-mentioned recommendation H.221, it is possible to dynamically divide the transmission rate from 64 kbps to 1,920 kbps for transmission. For example,
When connecting to an ISDN basic rate (2B + D) line for communication, the frame structure is divided into two B channel lines for transmission. The frame is divided into a master frame and a slave frame, and the master,
Transmission data is sequentially divided into slave, master, and slave, and master is assigned to B1 channel and slave is assigned to B2 channel for communication. Therefore, at the time of reception, the data of the master frame and the data of the slave frame are alternately received. However, it is arbitrary whether the master frame is transmitted on the B1 channel or the B2 channel, and it differs for each communication. Even if the transmitting side fixes the master frame to the B1 channel and the slave frame to the B2 channel, the receiving side determines whether the B1 channel is the master frame or the slave frame due to the nature of the ISDN line. , Cannot be determined. On the other hand, the line control unit of the communication line transmits / receives data in the order of B1 channel / B2 channel and generates a synchronization signal in B1 + B2 data units.

[0007]

However, the above-mentioned technique has the following problems. That is, in the above-mentioned multimedia communication terminal, as described above, it is not possible to determine which of the master frame and the slave frame including the continuous data sequence is received first, so that the order of the master frame / slave frame is It is necessary to execute the processing for the case of receiving the data in step 1 and the case of receiving in the order of the slave frame / master frame, which has a drawback that the processing of the received data becomes complicated.

[0008]

The present invention is intended to solve the above problems, and an object thereof is to facilitate the processing of received data regardless of the order of receiving master frames / slave frames.

[0010]

[0011]

The present invention has the following structure as one means for achieving the above object.

A communication device according to the present invention is a communication device which is connected to a communication line having a plurality of logical lines and which outputs first serial data composed of a plurality of data received from the communication line. Means, delay means for outputting the second serial data by delaying the first serial data by a predetermined amount based on the first synchronous clock, and first and second converting means for converting the serial data into parallel data. Switching means for inputting one of the first and second serial data to the first converting means and inputting the other one to the second converting means, and the first synchronous clock, And a generating means for generating a second synchronous clock based on a signal indicating the logic line that has received the first serial data, and the first and second converting means respectively. , Detecting a specific bit pattern from the serial data string input in synchronization with the second clock to generate a synchronization timing, and converting the input serial data into parallel data according to the synchronization timing. .

A communication method according to the present invention is a communication method of a communication device which is connected to a communication line having a plurality of logical lines, the method comprising receiving a plurality of data from the communication line and composing the plurality of data. Output first serial data, output second serial data obtained by delaying the first serial data by a predetermined amount based on the first synchronous clock, outputting the first synchronous clock, and the first synchronous clock. The second synchronous clock is generated based on the signal indicating the logical line that has received the serial data, and when the first and second serial data are converted into parallel data, respectively, in synchronization with the second clock. A specific bit pattern is detected from the input serial data string to generate synchronization timing, and the input serial data is parallelized according to the synchronization timing. And converting the over data. It is characterized by

[0014]

[0015]

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A communication device according to an embodiment of the present invention will be described in detail below with reference to the drawings.

[Structure] FIG. 3 is a block diagram showing an example of the structure of a communication apparatus according to an embodiment of the present invention, showing an example of a multimedia communication terminal apparatus.

In the figure, 301 is an image pickup unit such as a camera for inputting an image to be transmitted, 305 is an image encoding unit for converting an image signal input from the camera 301 into a predetermined communication data format, and 302 is an image transmitting unit. A sound collecting unit such as a microphone for inputting voice, 306 is an audio encoding unit for converting an audio signal input from the microphone 302 into a predetermined communication data format, and 317 is a video encoding unit 305 or an audio encoding unit 306. The multiplexer 319 selects input media to be transmitted and multiplexes them into a predetermined format. Reference numeral 319 denotes connection control of the communication line 331 and communication line.
A line control unit that controls data transmission / reception via the 331.
The communication line 331 is, for example, an ISDN basic interface (2B + D).

Reference numeral 318 is a separation unit for separating communication data received by the line control unit 319 for each medium, and 307 to 310.
Is a video decoding unit that restores a video signal from the received coded data, and 315 selects any one or a plurality of video signals from the four video signals restored by the video decoding units 307 to 310. A display control unit for displaying on the video display unit 303 such as a monitor, 311 to 314 are voice decoding units for restoring voice signals from the received code data, and 316 are four voices restored by the voice decoding units 311 to 314, respectively. An audio signal control unit that selects any one or a plurality of audio signals from the signals, adds them, and reproduces them by the audio reproduction unit 304 such as a speaker.

Further, 320 and 321 are LSD communication control units for controlling data communication between terminals respectively, 322 is an operation unit for an operator to operate the apparatus, and 323 is a general control section for controlling the overall operation of the apparatus. Is. In addition, the overall control unit 323 is
PU, ROM for storing programs and data, work RAM, I /
An instruction input from the operation unit 322, including
The operation of the entire device is controlled by the program stored in the ROM in advance.

The video encoding unit 305 encodes the video signal according to ITU-T Recommendation H.261 and inputs it to the multiplexing unit 317.
Recommendation H.261 uses correlation between frames of video signals to
It is a video signal coding method that adaptively performs high-efficiency coding using three types: nter (interframe), Intra (intra-frame), and MC (Motion Compensation). In the coding method according to this Recommendation H.261, the generation amount of code data can be adaptively controlled, and thus coding corresponding to an arbitrary bit rate of communication data becomes possible. The video decoding units 307 to 310 use this recommendation H.
Received data encoded according to 261 is received from the separation unit 318 and restored to a video signal.

Further, the voice coding unit 306 is based on ITU-T Recommendation G.71.
1 or G.726 to encode the audio signal and
Input to 317. Recommendation G.711 is a PCM encoding method that converts audio signals up to 4 kHz band into 8-bit quantized data.
The amount of code data generated is 64 bits / second. Also recommendations
G.726 uses ADP to convert PCM-encoded data according to Recommendation G.711.
It is a coding method for further compression by the CM method.There are four coding modes, and the amount of code data generated is 40k and 32k, respectively.
It is k, 24k, 16k bits / sec. The voice decoding units 311 to 314 receive the reception data encoded according to the recommendation G.711 or G.726 from the separating unit 318 and restore the voice signals.

The LSD communication units 320 and 321 handle the data communication function between the communicating terminals. This embodiment uses a known HDLC protocol as a communication protocol. LS
The data transfer rates of the D communication units 320 and 321 can be set to arbitrary values. The content of data to be communicated depends on the application of the device, but is, for example, text file data such as a document or communication line connection information between terminal devices.

The multiplexing unit 317 selects data of an arbitrary medium from the video coding unit 305, the audio coding unit 306, the LSD communication unit 320, and the LSD communication unit 321, and follows a predetermined multiplexing method. , Multiplex them. Separation unit 318 separates the received data for each medium, and these data are video decoding units 307 to 310, audio decoding units 311 to 314, LSD communication unit 320,
Assigned to the LSD communication unit 321. The return path 330 that is returned from the demultiplexing unit 318 to the multiplexing unit 317 is a path for returning the received data of any media and newly multiplexing it with other transmission data for transmission.

The multiplexing method is a method of allocating one or more of the sub-channels described with reference to FIG. 1 to a data channel of an arbitrary medium. Prior to communication, a terminal for transmission and a terminal for reception receive each other. Set the same quota. FIG. 4 is a diagram showing an example of subchannel allocation. Audio data 1 is allocated to subchannels # 1 and # 2, and audio data 2 is allocated to subchannels # 3 and # 4. Since data can be transmitted and received at 8 kbps per sub-channel, voice data 1 and 2 can be communicated at a rate of 16 kbps, respectively. Also, sub-channel # 5 is assigned to video data 1 and sub-channel # 7 is assigned to video data 2. Both have one sub-channel, so both video data 1 and 2 are 8k
The communication rate is bps. Also, subchannel # 6 is LSD1
Although subchannel # 8 is assigned to LSD2, subchannel # 6 has a dummy FAS / BAS assignment, so the communication rate of both subchannels is 6.4 kbs. In addition, the dummy
FAS / BAS will be described later.

As described above, the communication line 331 is the basic interface (2B + D) of ISDN, which is two logical communication lines of 64 kbps called B channel and call setting called D channel. It consists of one communication line (16kbps). The B channel is a communication channel for transmitting / receiving data to / from the communication partner, the D channel is a communication channel for communicating call setting information between the terminal and the network, and the communication line 331 is 192
Data strings are transmitted and received serially at a rate of k bits / second.

The line control unit 319, via the communication line 331,
Performs call setting control and data transmission / reception with the communication partner. Specifically, the line control unit 319 separates the data of the two B channels from the data string received via the communication line 331, and separates them in a data format in which each octet (8 bits) is time division multiplexed. While inputting to the unit 318, the data of the two B channels are time division multiplexed and sent to the communication line 331. Further, the line control unit 319 supplies the 128 kHz transmission synchronization clock and the transmission channel synchronization signal to the multiplexing unit 317, and the multiplexing unit 317
Sends the transmission data to the line control unit 319 in synchronization with the transmission synchronization clock. Note that the transmission data consists of B1 channel and B2 channel.
Channels are time-division multiplexed every 1 octet.
The transmission channel synchronization signal is a signal indicating whether the transmission data is the B1 channel or the B2 channel.

Furthermore, the line control unit 319 sends to the separation unit 318
The reception data synchronized with the reception synchronization clock is sent together with the 128 kHz reception synchronization clock and the reception channel synchronization signal.
Note that the received data is the same as the transmitted data on the B1 channel.
B2 channel data is time-division multiplexed every 1 octet. The reception channel synchronization signal is a signal indicating whether the reception data is the B1 channel or the B2 channel. FIG. 5 is an example of a timing chart of these reception synchronization clocks, reception channel synchronization signals, and reception data, and the timings of these signals regarding transmission are also the same. The details of the timing shown in FIG. 5 will be described later.

The display control unit 315 synthesizes the video signals restored by the video decoding units 307 to 310 and displays them on the video display unit 303. FIG. 6 is a diagram showing a display example of the video display unit 303, showing an example in which the display screen is divided into four windows 1101 to 1104, the window 1101 is the video restored by the video decoding unit 307, and the window 1102 is the video. A window 1103 displays the image restored by the decoding unit 308, a window 1103 displays the image restored by the image decoding unit 309, and a window 1104 displays the image restored by the video decoding unit 310.

Multiplexing Unit and Separating Unit FIG. 7 is a block diagram showing a detailed configuration example of the multiplexing unit 317 and the separating unit 318 including the folding path 330.

In the figure, 400 is a control CPU of this block.
Then, according to the program pre-stored in ROM402, the bus 43
Through 0, the multiplexing unit 317 including the folding path 330 and the demultiplexing unit 3
Controls each operation of 18. A RAM 401 is used as a work memory of the CPU 400 and for temporarily storing transmission data and reception data.

Next, each component of the multiplexing unit 317 will be described. Four
03 is a serial-parallel (S / P) converter, which converts the input serial data string into parallel data. In addition, S / P
The serial data input to the converter 403 includes transmission data input from the video encoding unit 305 and the audio encoding unit 306, and transmission LSD1 and transmission LSD2 input from the LSD communication unit 320 and LSD communication unit 321 respectively. And.

Numeral 404 is a slot allocator for allocating the data and return data from each medium to an arbitrary slot of the sub-channel. 405 to 408 are I / O ports, I / O ports 405 and 406 for the CPU 400 to read the data output from the slot allocator 404, and the channel switch 409 for the data output from the CPU 400.
There are I / O ports 407 and 408 for sending to.

Reference numeral 409 denotes a channel switch, which is I / O ports 407 and 4
The assignment of the two types of transmission data written in 08 and the two B channels of the communication control unit 319 is switched. 410
Is a parallel-serial (P / S) converter, and the channel switch 40
The parallel data input from 9 is converted into serial data that is multiplexed into two B channel data. The serial data output from the P / S converter 410 is input to the communication control unit 319.

Next, each component of the separating unit 318 will be described. A delay circuit 411 delays the data string received by the communication control unit 319 by one octet. 412 is a channel switch, which receives the reception data output from the communication control unit 319 and the reception data delayed by the delay circuit 411, and switches the connection between the two types of data and the FAW detectors 413 and 414. It is a thing.

FAW detectors 413 and 414 respectively detect the frame synchronization signal FAW defined in Recommendation H.221 from the input data sequence. 415 to 418 are I / O ports, and 7 (415) and I / O ports 8 (416) are I / O ports for the CPU 400 to read the received data in synchronization with the FAW timing detected by the FAW detector 413 or 414. / O port 415 and
There is 416 and I / O ports 417 and 418 for sending the received data to P / S converter 419 and folding port 420.

Reference numeral 419 denotes a P / S converter, which is an I / O port 417 or 41.
Convert the parallel data written in 8 into serial data for each functional block. The serial data output from the P / S converter 419 includes the video data 1 to 4 sent to the video decoding units 307 to 310, the audio data 1 to 4 sent to the audio decoding units 311 to 314, and the LSD communication unit. Receive LSD sent to 320 and 321
There is one and receive LSD2.

The return port 420 included in the multiplexing unit 317
Selects the return data from the received data written in the I / O port 417 or 418 and sends it to the slot distributor 404.
The data returned by the return port 420 is assigned to any transmission sub-channel and transmitted.

Call-back Communication FIG. 8 is a diagram showing the concept of call-back communication. Multimedia communication terminal devices A to E (1
201 to 1205) are connected by the B channel (64 kbps). The ISDN basic interface is a single line interface that accommodates two logical lines called B channels, and each B channel can set up a call with a different communication partner. Focusing on terminal A, the two B channels are terminal B and terminal E, respectively.
It is connected to the.

Here, the transmission data of the video imaged by the camera 301 provided in each terminal is Va, Vb, Vc, Vd, Ve respectively.
Then, the transmission data of the sound collected by the microphone 302 of each terminal is defined as Aa, Ab, Ac, Ad, Ae, respectively. Figure 9 shows terminal A (1201)
FIG. 3 is a diagram showing an example of a sub-channel structure of communication data transmitted / received on each B channel, and Bb / a-Rx shown in FIG.
Structure of B channel received from terminal (1202) by (1), same figure (2)
Ba / b-Tx shown in Fig. 3 is the structure of the B channel transmitted from terminal A (1201) to terminal B (1202), and Be / a-Rx shown in Fig. 3 (3) is terminal A (120
Structure of B channel received from terminal E (1205) by 1), same figure
Ba / e-Tx shown in (4) shows the structure of the B channel transmitted from the terminal A (1201) to the terminal E (1205), each having eight sub-channels and having a total rate of 64 kbps.
Further, in the figure, reference numerals 1301, 1311, 1321, 1331 indicate FAS / BAS, respectively, and reference numerals 1302, 1312, 1322, 1332 indicate dummy FAS / BAS, respectively. FA for dummy FAS / BAS
Secure the same number of empty bits as S / BAS and insert no data into this empty bit part.

In the Bb / a-Rx shown in FIG. 9 (1), the audio data Ac of the terminal C (1203) is on the subchannels # 1 and # 2, and the terminal B (is on the subchannels # 3 and # 4. 1202) audio data Ab, sub-channel # 5 and # 6 terminal C (1203) video data Vc,
Subchannels # 7 and # 8 have terminal B (1202) video data Vb
Are assigned respectively.

In the Be / a-Rx shown in FIG. 3C, the voice data Ad of the terminal D (1204) is on the subchannels # 1 and # 2, and the terminal E (is on the subchannels # 3 and # 4. 1205) audio data Ae, sub-channel # 5 and # 6 terminal D (1204) video data Vd,
Video data Ve of terminal E (1205) is sent to subchannels # 7 and # 8.
Are assigned respectively.

In Ba / b-Tx shown in FIG. 2B, first,
Sub-channels # 7 and # 8 for video data Va of own terminal A (1201)
The audio data Aa of own terminal A (1201) to subchannels # 3 and #
Assign to 4 and send. Also, the video data Ve included in the data received from the terminal E (1205) on the opposite side of the destination terminal B (1202) is assigned to the subchannels # 5 and # 6, and the audio data
Allocate Ae to subchannels # 1 and # 2 and send back.

In the Ba / e-Tx shown in FIG. 4 (4), first,
Sub-channels # 7 and # 8 for video data Va of own terminal A (1201)
The audio data Aa of own terminal A (1201) to subchannels # 3 and #
Assign to 4 and send. Also, the video data Vb included in the data received from the terminal B (1202) on the opposite side of the destination terminal E (1205) is assigned to the subchannels # 5 and # 6, and the audio data
Assign Ab to subchannels # 1 and # 2 and send back.

That is, although the terminal A (1201) receives the data of the terminal C (1203) and the terminal B (1202) from the terminal B (1202), the data of the adjacent terminal B (1202) and its own terminal A ( The data of 1201) is multiplexed and transmitted to terminal E (1205) on the opposite side of terminal B (1202). Further, terminal A (1201) is connected to terminal D (1204) and terminal E (1204).
The data of (1205) is received from the terminal E (1205), but the data of the adjacent terminal E (1205) and the data of its own terminal A (1201) are multiplexed, and the data on the opposite side of the terminal E (1205) is received. Send to terminal B (1202). In this way, when returning, the allocation position of the sub-channel is exchanged and the data of the adjacent terminal is always # 3, # 4,
Since it is assigned to each channel of # 7 and # 8, data does not keep looping the line.

For example, when the transmission data of the terminal A (1201) is received by the terminal C (1203) via the terminal B (1202), the loopback ends, and the transmission data of the terminal A (1201) passes through the terminal E (1205). The loopback ends when it is received by D (1204). Thus, terminal B
All the terminals ~ E (1202 to 1205) loop back the data by the same method as the terminal A (1201), so that each terminal can receive the audio and video data from all the terminals.

Next, the above-mentioned dummy FAS / BAS will be described. Since FAS and BAS are signals for setting frame synchronization and communication capability between terminals communicating with each other, FAS and BAS between terminals communicating with each other
Need not be returned for communication between terminals different from that terminal. However, the FA of subchannel # 8 shown in Figure 9 (1)
When S / BAS is extracted and the received video data Vb is looped back, an empty bit with no data occurs at the FAS / BAS position of subchannel # 6 because the data amount is the same. Therefore, this empty bit position is set in advance as a dummy FAS / BAS, and the data at this bit position is ignored during reception. This is dummy FAS / BAS 1302 and 1322 of subchannel # 6 shown in FIGS. 9 (1) and 9 (2), and the receiving terminal ignores the data at this bit position.

Delay Circuit and Channel Switch FIG. 10 is a block diagram showing a detailed configuration example of the delay circuit 411, the channel switch 412 and their peripheral circuits.
Are D flip-flops (hereinafter referred to as “DF / F”), 509 and 512 to 515 are AND gates, and 510 and 511 are OR gates.

Reference numeral 520 is an initialization signal, which is an initialization signal for the delay circuit 410 input from the CPU 400 prior to the start of communication. When the initialization signal 520 is input, DF / F501 to 5
Output Q of 08 is initialized to H level. 521 is the line control unit 3
In the received data sent from 19, two B channel data are time division multiplexed in octet units. 522
Is a synchronous clock of the received data, which is 128 kHz, for example.
A reception channel synchronization signal 523 indicates whether the reception data 521 is B1 channel data or B2 channel data. A reception channel selection signal 524 is a control signal for the CPU 400, and is a signal for determining the connection relationship between the two FAW detectors 413 and 414 and the two B channels.

The reception channel selection signal 524 is set to H using FIG.
The operation timings of the delay circuit 411 and the channel switch 412 at the level will be described.

The delay circuit 411 buffers the received data 521 for eight clocks in synchronization with the reception synchronization clock 522, and delays the received data 521 by one octet (hereinafter referred to as “delayed data”) 525. To generate. Also, A
The ND gate 509 ANDs the reception synchronization clock 522 and the channel synchronization signal 523 to generate a reception data synchronization clock 528. As shown in FIG. 5, the reception data synchronization clock 528 is a clock signal only when the channel synchronization signal 523 is at L level, and is input to the FAW detectors 413 and 414 as a data synchronization clock of the reception data 526 and 527. .

When the reception channel selection signal 524 is at H level, the reception data 521 is input to the FAW detector 413 as reception data 526 via the AND gate 512 and the OR gate 510.
Further, the delay data 525 is input to the FAW detector 414 as reception data 527 via the AND gate 513 and the OR gate 511.

When the reception channel selection signal is at the L level, the reception data 521 is input to the FAW detector 414 as the reception data 527 via the AND gate 515 and the OR gate 511. On the other hand, the delay data 525 is the AND gate 514 and the OR gate 5
The received data 526 is input to the FAW detector 413 via 10.

FAW Detector FIG. 11 is a block diagram showing a detailed configuration example of the FAW detector 413. Since the FAW detectors 413 and 414 have the same configuration, the description of the FAW detector 414 will be omitted.

In the figure, reference numerals 701 to 707 denote delay circuits, respectively, which have the same structure as the delay circuit 411 described above. 7
08 to 714 are DF / F, and 715 is an 8-bit register. Reference numeral 724 denotes a sync detection gate, which outputs an H level signal when '0011011', which is a part of the FAW sync pattern, is detected from the input signal.

Further, 725 is a preset / resettable DF / F, 726 and 727 are AND gates respectively, and 728 is DF / F.
F, 729 and 738 are inverters, 730 is an 80-ary counter, 731 is a hexadecimal counter, 732 is an OR gate, and 733 and 734 are switching circuits.

Reference numeral 740 is a detection circuit initialization signal, which is an initialization signal for the FAW detector input from the CPU 400 prior to the start of communication. 741 is a through mode setting signal, which is a control signal of the CPU 400 for controlling the switching circuits 733 and 734 to cause the FAW detector to bypass the received data 526. A next FAW detection enable signal 742 is a control signal of the CPU 400 for starting the FAW search by the FAW detector.

Reference numeral 743 is a FAW synchronization enable signal, which is a control signal of the CPU 400 for controlling whether or not the initialization of the frame synchronization signal generating circuit of the FAW detector is enabled when FAW is detected.

First, the B1 channel data is selected and FA
The case of bypassing the W detector will be described.

When the through mode is set by the through mode setting signal 741, the switching circuits 733 and 734 select the reception data 526 and the channel synchronization signal 523, respectively. Therefore,
The received data 526 is input to the DF / F 708 via the switching circuit 733 and sequentially synchronized with the received data synchronization clock 528 to the DF.
/ F708 to 714 will be shifted. At the timing indicated by reference numeral 601 in FIG. 5 (the rising edge of the channel synchronization signal 523), the received data 526 is directly input to the D0 input of the register 715, and the received data delayed by one clock by the DF / F708 is input to the D1 input. The received data 754 delayed by 8 clocks is input to the D7 input. Therefore, D1 to D8 (B1 channel) of the reception data 526 shown in FIG.
The serial data is converted into parallel data by being input to 15 and stored in the register 715 at the timing of 601. Then, at the next rising edge of the channel synchronization signal 523, the data D17 to D24 (B1 channel) are stored in the register 715 and converted into parallel data.
In this way, only the data of the B1 channel is serial / parallel converted and written into the register 715 sequentially.

Next, the B2 channel data is selected and FA
When bypassing the W detector, D9 to D16 (B2 channel) of the reception data 527 shown in FIG. 5 are converted into parallel and written in the register 715 at the timing indicated by reference numeral 601 as in the above case. Then, at the next rising edge of the channel synchronization signal 523, the data D25 to D32 (B2 channel) are registered.
It is stored in 715 and converted into parallel data. In this way, only the B2 channel data is serialized.
/ Parallel converted and written to register 715.

Next, the B1 channel data is selected and FAW
The operation when the detector is not bypassed will be described.

DF / F725 is initialized by the detection circuit initialization signal 740 from the CPU 400, and the next FAW detection enable signal is output.
When 742 becomes H level, it is cleared and its output becomes L level, and the AND gate 726 closes. And
When the sub-multiframe period currently being processed has elapsed,
Next, the FAW detection enable signal 742 becomes L level and the AND gate 726 opens, so that FAW detection is started.

The FAW is detected at the beginning of communication, and during communication, a data error or the like occurs during some reason and the bit pattern of FAW cannot be found at a predetermined bit position. When it is determined that the frame is out of alignment, the process is performed again to establish frame synchronization.

The frame synchronization signal generation circuit includes a hexadecimal counter 731 that generates a reception octet synchronization signal 752, an 80-base counter 730 that generates a reception frame synchronization signal 751, and a binary system that generates a reception sub-multiframe synchronization signal 750. It consists of a counter 739. The binary counter 739 is DF / F728.
And inverters 729,738. FIG. 12 is a timing chart showing an operation example of these counters.

The hexadecimal counter 731 has a reception synchronization clock 522.
Is a counter that counts up in synchronization with, and is initialized to zero by the output of the AND gate 727, which is a synchronization detection gate,
When the count value is zero, the L level signal is sent to the OR gates 732 and 80.
Output to the decimal counter 730. The octal counter 730 is initialized to zero by the output of the AND gate 727, and the hexadecimal counter 731
Is a counter that counts up in synchronization with the output of the L-level receive frame synchronization signal 751 when the count value is zero.
Is output. The binary counter 739 is initialized to zero by the output of the AND gate 727, and outputs the L level and the H level repeatedly in synchronization with the output of the 80-ary counter 730 (received frame synchronization signal 751). The output of 739 becomes the reception sub-multiframe synchronization signal 750.

First, the reception data 526 and the reception data synchronization clock 528 output from the channel switch 412 are input to the delay circuit 701 and the synchronization detection data 724. Delay circuit
The received data delayed by the octet in 701 is delayed by the octet in each of the five delay circuits 702 to 706 in the next stage, and the six received data delayed in the six delay circuits 701 to 706 are transferred to the sync detection gate 724. Is entered. Therefore, a total of 7 bits of 1-octet intervals included in the serial reception data string are input to the synchronization detection gate 724. Further, the received data delayed by a total of 6 octets output from the delay circuit 706 is input to the delay circuit 707 of the next stage, delayed by a total of 7 octets, and then input to the DF / F 708 via the switching circuit 733. To be done.

As shown in FIG. 1, the frame structure of Recommendation H.221 constitutes a sub-multiframe structure with a pair of an odd frame and an even frame. FAS for even frames
In order to synchronize the frame, a sync bit pattern of '0011011', which is a part of the FAW signal, is always inserted at a position of 2 to 8 octets. That is, in the even-numbered frame, there is a bit pattern of "0 ... 0 ... 1 ... 1 ... 0 ... 1 ... 1" at 1-octet intervals for each bit in the serial data string. Therefore, the synchronization pattern of '0011011' is monitored at intervals of 1 octet from the serial data string, and if this synchronization pattern is detected, an even frame is constructed from the bits 15 bits backward from the first bit at the time of detection. Can be determined.
The synchronization detection gate 724 is a gate for detecting the synchronization bit of "0011011", and when detecting the synchronization bit of "0011011", outputs an H level signal. And at this time, D
-The output of the F / F 714 corresponds to the head bit data of the frame, and the data of the first octet of the frame is input to the register 715.

In the initial state at the start of communication, DF / F7
The output of 25 is at H level, and the AND gate 726 is in the ON state. Therefore, after the FAW sync enable signal 743 becomes valid, when the sync detection gate 724 detects the bit pattern of '0011011', the hexadecimal counter 731 and the 80th decimal counter 730
And the binary counter 739 is initialized. The FAW detection timing indicated by reference numeral 801 in FIG. 12 is the initialization timing of these counters.

Once FAW is detected and frame synchronization is established, the received data 526 is transmitted to the delay circuits 701 to 707 and the DF / F.
Received octet sync signal, which is sequentially shifted from 708 to 714
The octet data of the frame structure is written to the register 715 in synchronization with 752.

Operation Control Flow of FAW Detector FIG. 13 is a flow chart showing an example of operation control of the FAW detector, which is an example of a control procedure executed by the CPU 400.

In the figure, the CPU 400 prior to communication
In step S1402, the FAW detector is initialized. In particular,
Control initialization signal 520 to delay circuits 701-707, DF / F708
~ 714 and the register 715 are initialized, the detection circuit initialization signal 740 is controlled, and the output of the DF / F 725 is set to the H level. Next, the CPU 400 controls the FAW sync enable signal 743 to turn on the AND gate 727 (FAW sync on) to enable the FAW sync detection function in step S1403, and then in step S1403.
In 1404, the reception octet synchronization signal 752 waits for the L level, and when the reception octet synchronization signal 752 becomes the L level, the data is read from the register 715 in the step S1405 and the RAM 401
Transfer to.

Subsequently, the CPU 400 performs AND in step S1406.
The output of gate 726 (FAW detect signal 754) is examined to determine if a FAW has been detected. If FAW is not detected, it is determined that frame synchronization has not been established, and the process returns to step S1403. On the other hand, when FAW is detected and frame synchronization is established, the count values of the hexadecimal counter 731, the 80th base counter 730, and the binary counter 728 are initialized to zero. Therefore, when FAW is detected, the FAW synchronization enable signal 743 is turned off in step S1407 to prohibit the initialization of those counters when the next FAW is detected.

Next, the CPU 400 determines in step S1408 whether or not the communication is completed, and if the communication is completed, the process is completed. If not completed, in step S1409,
Wait for the reception octet sync signal 752 to go to L level.
During this time, the FAW detector is converting the serial data into parallel data in octet units.

When the reception octet synchronization signal 752 becomes L,
The CPU 400 reads the data from the register 715 in step S1410 and transfers it to the RAM 401, and in step S1411, in order to determine whether or not the read data is the first octet data of an even frame, the reception sub-multiframe synchronization signal It is checked whether 750 is at L level (that is, even frame) and the received frame synchronization signal 751 is at L level (that is, first octet data). If these two conditions are not satisfied, the process returns to step S1408, and steps S1408-
Repeat S1411. On the other hand, if the two conditions are satisfied, it is determined that the first octet data of the even frame has been read, and in step S1412, the output of the AND gate 726 (FAW detection signal 754) is checked to detect FAW. It is determined whether or not

When FAW is detected, CPU 400 processes the data read from register 415 up to that point as one sub-multiframe data in step S1417, and then returns to step S1408. If the FAW is not detected at the first octet timing of the even frame, it is determined that the frame synchronization has been lost and the next FAW detection enable signal 742 and the FAW synchronization enable signal are detected in step S1413 to detect the next FAW. Turn on the 743. Then, in synchronization with the octet timing in step S1414, the FAW detection signal 754 is inspected in step S1415, and when the FAW detection signal 754 is detected, it is determined that frame synchronization is reestablished in step S1416, and step S1416. After turning off the FAW sync enable signal 743 with, return to step S1408 and perform the sub-multiframe data read routine step.
The process returns to S1408 to S1412 and S1417.

CPU 400 repeats the above processing until the communication is completed.

DF / F725 Operation Timing FIG. 14 is an example of an DF / F725 operation timing chart during FAW detection operation. As shown in the figure, the DF / F725 operates at the rising edge timing of its clock input (CK), and is cleared when the next FAW detection enable signal 742 goes to H level. Until the beginning of the sub-multiframe, its output is at L level, so the AND gate 726 for FAW detection is turned off.

AND gate 726 at the beginning of the sub-multiframe
When is turned on, the data input to the FAW synchronization detection gate 724, that is, the reception data 526 shown in FIG. 11 and the reception data delayed by the delay circuits 701 to 706 are the second from the beginning of the sub-multiframe. Clock timing, or figure
The received data is at the clock timing indicated by reference numeral 901 in FIG. Therefore, the FAW search is started from the bit position delayed by one cycle from the beginning of the sub-multiframe, and the FAW synchronization signal pattern search is started from the bit position delayed by one clock from the conventional detection timing.

The FAW detectors 413 and 414 have the same structure, and their operations are also as described above. FAW detectors 413 and 414
Due to the action of the delay circuit 411, the received data input to is the same for both the B1 channel and the B2 channel. The CPU 400 synchronizes with the reception octet synchronization signal 752 output from the FAW detectors 413 and 414, and synchronizes with the I / O port.
Data is read from the registers 415 and 416. On the other hand, with respect to the I / O ports 405 to 408, 417, 418, reading and writing are performed in synchronization with the octet data transfer timing of the same transmission data.

I / O Ports 417, 418 and P / S Converter 419 FIG. 15 is a block diagram showing a detailed configuration example of the I / O ports 417, 418 and P / S converter 419.

Each of the I / O ports 417 and 418 has a two-stage structure register. The input terminals D0 to D7 of the registers 417a and 418a in the first stage are connected to the bus 430 of the CPU 400,
Data is written by the master reception register write signal 1610 and the slave reception register write signal 1611 sent from. The input terminals D0 to D7 of the registers 417b and 418b in the second stage are connected to the output terminals Q0 to Q7 of the register in the first stage, respectively.
Ingest data in sync with. In this way, by making the register a two-stage structure, the CPU 400 can be connected to the I / O ports 417 and 418.
It becomes possible to write data at the timing synchronized with the transmission octet and the timing asynchronous with the transmission octet, and it becomes possible to synchronize the outputs of the I / O ports 417 and 418 with the transmission octet.

A hexadecimal counter 1605 is initialized to zero in synchronization with the octet timing of transmission data, and counts up in synchronization with the bit timing of transmission data. The outputs C4 to C1 are sequentially counted up from '0000' to '1111'.

Reference numeral 1601 denotes a hexadecimal decoder, which has input terminals in4 to in1
According to the value input to, any one of the output terminals O0 to O15 is set to H level. Since the output terminals C4 to C1 of the hexadecimal counter are connected to the input terminals in4 to in1, the output of the hexadecimal decoder 1601 is that the output O0 is H level and O1 to O15 is L level at the beginning of the transmission octet timing. After 1 clock, the output O1 goes to H level and the outputs O0 and O2 to O15 go to L level.
The level output shifts to O2, O3, ..., O15, O0, O1, ....

Gates 1603 and 1604 are for the hexadecimal decoder 1601.
According to the H level output, any one of the input signals SD0 to SD15 is selected. OR gate 1602 is gate 1603 or
The signal selected by 1604 is output as serially converted received data 1613. In other words, the hexadecimal counter 1605 counts up in synchronization with the transmission data timing of 128 kHz, so that the P / S converter 419 converts the parallel reception data written in the I / O ports 417 and 418 at a rate of 128 kHz. Parallel-to-serial conversion to convert to serial data will be performed.

R-V1 enable signal 1620 to R-V4 enable
1623 is recommended for each of the first to fourth received video data
It is a signal indicating which subchannel in the H.221 frame is assigned. For example, the first received video data is the sub-channel # 7 and sub-channel # 8 of the master frame.
Output of hexadecimal decoder 1601 when assigned to
Or when O7 is H level, R-V1 enable signal 1620
Also becomes H level, and the R-V1 enable signal 1620 becomes L level at other timings. R-V2 enable signal 162
The same applies to 1 to R-V4 enable 1623, which is always at the L level when the corresponding received video data is not assigned.

R-A1 enable signal 1624 to R-A4 enable
1627 is recommended by the 1st to 4th received voice data respectively
It is a signal indicating which subchannel in the H.221 frame is allocated, and becomes the H level at the timing of the corresponding subchannel, like the R-V1 enable signal 1620.

The R-L1 enable signal 1628 and the R-L2 enable signal 1629 are signals indicating to which subchannel in the frame of Recommendation H.221 the first and second received LSD communication data are assigned, respectively. Yes, R-V1 enable signal 16
Similar to 20, etc., it goes high at the timing of the corresponding subchannel.

In the received FAS / BAS mask signal 1630, the corresponding bit of the serial data 1613 is F of the frame structure of Recommendation H.221.
It is a signal that indicates the bit allocation timing of AS or BAS. It is not the timing of the bit position of FAS and BAS.
It is at the L level, and is at the H level at other timings.

The serial data 1613 has the gates 1606 to 1608.
, Enable signal indicating each data type described above
1620 to 1629 and the received FAS / BAS mask signal 1630 are gated to the video decoding units 307 to 310 as the received video data and the audio decoding units 311 to 314 as the received audio data.
It is sent to the communication units 320 and 321 as a reception LSD. Therefore, for example, when the R-V1 enable signal 1620 is at the H level and the reception FAS / BAS mask signal 1630 is at the H level, the serial data 1613 is input to the video decoding unit 307 as valid reception video data, The decryption is executed. The same applies to other video decoding units, audio decoding units, and LSD communication units.

Reception FAS / BAS Mask Signal FIG. 16 is a block diagram showing a configuration example of a generation circuit of the reception FAS / BAS mask signal 1630. In the figure, 1605 counts up in synchronization with the transmission data clock described above.
It is a binary counter and is initialized to zero in synchronization with the transmission octet timing. Reference numeral 1506 is an 80-ary counter that counts up in synchronization with the transmission octet timing, and generates the timing that constitutes the recommended H.221 frame structure of the transmission data.

Reference numeral 1501 denotes an octal decoder, which has an input terminal in
Input the count value of the hexadecimal counter 1605 to 2 to in0, and output any one of the outputs O0 to O7 corresponding to the count value,
Set to H level sequentially. Input terminals in2-in0 have 1
Since the lower 3 bits C3 to C1 of the count output of the hexadecimal counter 1605 are connected, the output O7 of the octal decoder 1501 becomes H level when the count value of the hexadecimal counter 1605 is “7” and “15”. Become. Therefore, the output of the octal decoder 1501 is the subchannel of the master transmission frame and the slave transmission frame.
It indicates the timing of # 1 to # 8.

Reference numeral 1502 is also an octal decoder.
Similarly, according to the value input to the input terminals in2-in0,
Any one of the outputs O0 to O7 corresponding to that value is set to the H level. Since the upper 3 bits C7 to C5 of the count output of the 80-base counter 1506 are connected to the input terminals in2 to in0,
The output O0 of the octal decoder 1502 becomes H level when the count value of the 80-ary counter 1506 is "0" to "15", and the output O1
Goes to the H level when the count value of the 80th base counter 1506 is "16" to "31", and similarly, the outputs O2 to O7 sequentially go to the H level for every 16 counts of the octet timing.

Dummy reception FAS / BA sent from CPU 400
S mask control signal 1521 is a dummy reception F of subchannel # 6.
A signal that controls the validity / invalidity of the AS / BAS mask signal (output Q5 of the decoder 1501). The control signal 1 is output by the AND gate 1507.
When 521 is at H level, the dummy FAS / BAS mask signal is valid.

The OR gate 1503 logically sums the signal output from the AND gate 1507 and the output Q7 of the decoder 1501,
Generate the received FAS / BAS mask signal.

The reception FAS / BAS mask control signal 1522 sent from the CPU 400 is a signal for controlling the validity / invalidity of the reception FAS / BAS mask signal, and the AND gate 1504 controls the control signal 152.
When 2 is H level, the received FAS / BAS mask signal is valid. If the FAS / BAS mask signal is invalid, the communication data is recommended in H.2.
It occurs when the frame structure of 21 is not adopted and when it is in the non-frame mode of Recommendation H.221.

FIG. 17 is an example of a timing chart of the received FAS / BAS mask signal.

In the figure, the M sub-multi-frame sync signal is a sub-multi-frame sync signal on the master channel side of the recommended H.221 frame of the transmission data, and indicates an even frame when it is at the L level, Indicates that it is an odd frame. The OCT16 mask signal is
A signal indicating the period from the first octet timing to the 16th octet timing, which is the octal decoder 1502 shown in FIG.
Is the output O0 of. # 6 / # 8 mask signal is for subchannel # 6
And a signal indicating the timing of sub-channel # 8, which is the output signal of the OR gate 1503 shown in FIG.

As shown in FIG. 17, if the received FAS / BAS mask signal is used to gate the serial data 1613 shown in FIG. 15, the FAS / BAS and dummy FAS / BAS shown in FIG. The corresponding data can be removed.

S / P Converter 403 FIG. 18 is a block diagram showing a detailed configuration example of the S / P converter 403.

In the figure, the TV enable signal is a signal permitting the transmission video data to be read from the video encoding unit 305, and the TA enable signal is a signal permitting the transmission audio data to be read from the audio encoding unit 306. , The T-L1 enable signal is a signal for permitting the transmission data to be read from the LSD communication unit 320, and the T-L2 enable signal is a signal for permitting the transmission data to be read from the LSD communication unit 321. It is sent from CPU400.

The selector including the AND gates 1818 to 1821 and the OR gate 1817 serves as the enable signal and the transmission FAS /
Transmission data is selected according to the BAS mask signal 1840. DF
/ F1816 to 1801 configure a 16-stage shift register, which is initialized by the initialization signal 520, reads the selected transmission data in synchronization with the transmission synchronization clock 1831, and outputs it as transmission parallel data 1830.

Next, as an example, using the B1 channel,
A case of transmitting data with the frame configuration shown in FIG. 4 will be described. In this case, the TV enable signal is valid at the timing of subchannel # 5 of the transmission frame, the TA enable signal is valid at the timing of subchannels # 1 and # 2 of the transmission frame, and the T-1 enable signal is at the transmission frame. It becomes valid at the timing of subchannel # 6.

The voice encoding unit 306 receives the TA enable signal.
At the H level and when the transmission FAS / BAS mask signal 1840 is at the H level, valid transmission voice data is output. The video encoding unit 305 has the TV enable signal at the H level, and
When the transmit FAS / BAS mask signal 1840 is at H level, valid transmit video data is output. The LSD communication unit 320 outputs a valid transmission LSD when the T-L1 enable signal is at H level and the transmission FAS / BAS mask signal 1840 is at H level.
The LSD transmission section 321 outputs a valid transmission LSD when the T-L2 enable signal is at H level and the transmission FAS / BAS mask signal 1840 is at H level.

Therefore, in synchronization with the transmission synchronization clock 1831, first, the transmission voice data is sequentially input to the DF / F 1816 and shifted. During the periods of sub-channels # 3 and # 4, all enable signals are at L level, and as a result, H level invalid data is input to the DF / F1816. Then, the transmission video data and the transmission LSD are sequentially input to the DF / F 1816 and shifted. Even during sub-channels # 7 and # 8, all enable signals are at L level and H level invalid data remains.
Input to DF / F1816.

Next, the B2 channel data is input. Since this example uses only the B1 channel for communication,
During the period of the B2 channel, that is, the period of 8 clocks, all the enable signals are at the L level, and the H level invalid data is input to the DF / F1816 and shifted.

When the transmission data is shifted in this way for 16 clocks, the first input transmission audio data is DF / F1801 and 1802, and the transmission video data is DF / F1805.
The transmission LSD data is stored in the DF / F1806. Therefore, by reading each data stored in the DF / Fs 1801 to 1816, it is possible to obtain parallel data 1830 in which serial transmission video data, transmission audio data, and transmission LSD data are assigned to the respective sub-channels.

Foldback Port 420, Slot Distributor 404 and I / O Ports 405, 406 FIG. 19 shows the turnback port 420, slot distributor 404 and I / O.
FIG. 3 is a block diagram showing a detailed configuration example of ports 405 and 406.

In the figure, 1901, 1902, 1905 and 1906 are 8-bit registers, 1903 and 1904 are CPU 40 respectively.
8x8 switching circuit controlled by 0, 1907 and 1908
Are input selection circuits respectively controlled by the CPU 400.

When the loopback data 1612 is looped back from the I / O ports 417 and 418 shown in FIG. 15, the slave side register for reception is used.
Data SD8 to SD15 output from 418b are input to the input terminals D7 to D0 of the master side register 1901 for transmission, and data SD0 to SD7 output from the master side register 417b for reception are transmitted to the slave side register 1902 for transmission. Input to D7 to D0. Registers 1901 and 1902 contain transmit octet sync signal 16
Switching circuit 1903 that reads back loop data 1612 in synchronization with 14
And output to 1904.

The switching circuit 1903 is controlled by the CPU 400.
Select any bit from the outputs D0 to D7 of register 1901,
Connect to any bit position LPD0-LPD7. Switching circuit 1904
Similarly, the output of register 1902 is controlled by the CPU 400.
Select any bit from D0 to D7 and select any bit position LPD8
~ Connect to LPD15.

Under the control of the CPU 400, the input selection circuit 1907 selects either LPD0 to LPD7 or TPD0 to TPD7 (transmission parallel data) for each bit, and the master side register
Connect to input terminals D7 to D0 of 1905. The register 1905 synchronizes with the transmission octet synchronization signal 1614, and the input selection circuit 19
The data selected in 07 is read and output to the I / O port 405. Similarly, the input selection circuit 1908 is also controlled by the CPU 400 to control LPD8 to LPD15 and TPD8 to TPD15 (transmission parallel data).
Either of them is selected for each bit and connected to the input terminals D7 to D0 of the slave side register 1906. Register 1906
Outputs the data selected by the input selection circuit 1908 to the I / O port 406 in synchronization with the transmission octet synchronization signal 1614.

I / O ports 405 and 406 respectively register 1905 in accordance with master transmission register read signal 1913 and slave transmission register read signal 1914 sent from CPU 400.
Since the transmission data input from the and 1906 are transmitted to the bus 430, the CPU 400 can read the transmission data.

Channel Switch 409, P / S Converter 410 and I / O Ports 407, 408 FIG. 20 is a block diagram showing a detailed configuration example of the channel switch 409, P / S converter 410 and I / O ports 407, 408. Is.

In the figure, 2003 and 2004 are 8-bit registers, 2001 and 2002 are selectors, and 2006 are selectors.
And 2007 are AND gate groups, and 2008 is an OR gate. In addition, I / O ports 407 and 408 have initialization signal 5
It consists of an 8-bit register initialized by 20.

The CPU 400 sends the master transmission register write signal 20
11 and the slave transmission register write signal 2012 transmits the data of the master frame to be transmitted to the register 4 via the bus 430.
The data of the slave frame to be transmitted is written to 07 in the register 408 via the bus 403. Registers 407 and 40
The transmission data written in 8 is written in the register 2003 or 2004 via the selector 2001 or 2002 in synchronization with the transmission octet synchronization signal 1614.

The selectors 2001 and 2002 select the inputs A0 to A7 when the transmission channel selection signal 2014 controlled by the CPU 400 is at the H level, and select the inputs B0 to B7 when the transmission channel selection signal 2014 is at the L level. The transmission data written in registers 2003 and 2004 are
The AND gate groups 2006 and 2007 and the OR gate 2008 sequentially select bit by bit according to the output of the above-described hexadecimal decoder 1601, convert the serial data into 2013, and output the serial data 2013. The serial data 2013 is sent to the line controller 319 shown in FIG.

In the above description, each B channel is connected to different points at one ISDN basic rate. However, by using a plurality of basic rates, each basic rate line is separated. You may make it connect to a point. Further, the communication rate is not limited to the basic rate of ISDN and may be a higher speed data communication line or, of course, a lower speed communication line, for example, MODEM may be used to connect to a public line.

Furthermore, the same configuration, such as the third delay means and the third switching means, the fourth delay means and the fourth switching means, may be constructed in a plurality of stages. In addition, the data of the channel to which the dummy FAS / BAS signal that is the pseudo sync signal is added may be any kind of data, and the pseudo sync signal is not limited to one, and multiple pseudo sync signals may be sent to different subchannels. May be added to.

As described above, according to this embodiment, the received master frame and slave frame are the B1 channel and the B2 channel.
Regardless of which of the channels is used, the processing timings are substantially the same, which makes it easy to process the received data. Furthermore, when receiving the loopback data and separating the data of each media, the subchannel
Not only can FAS and BAS of # 8 be separated, but pseudo signals can also be separated.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of a single device.

It goes without saying that the present invention can also be applied to the case where it is achieved by supplying a program to a system or an apparatus.

[0123]

As described above, according to the present invention,
It is possible to easily process the received data regardless of the master frame / slave frame reception order.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of a transmission frame structure defined in Recommendation H.221;

FIG. 2 is a diagram showing a bit pattern of a frame synchronization word FAW,

FIG. 3 is a block diagram showing a configuration example of a communication device according to an embodiment of the present invention,

FIG. 4 is a diagram showing an example of sub-channel allocation according to the present embodiment,

FIG. 5 is a timing chart example of a reception synchronization clock, a reception channel synchronization signal, and reception data in the present embodiment,

6 is a diagram showing a display example of the video display unit shown in FIG. 3;

7 is a block diagram showing a detailed configuration example of a multiplexer and a demultiplexer shown in FIG.

FIG. 8 is a diagram showing a concept of return communication.

9 is a diagram showing an example of a subchannel structure of communication data transmitted and received on each B channel of terminal A shown in FIG.

10 is a block diagram showing a detailed configuration example of the delay circuit shown in FIG. 7, a channel switcher, and their peripheral circuits;

11 is a block diagram showing a detailed configuration example of the FAW detector shown in FIG.

12 is a timing chart showing an operation example of the counter shown in FIG.

13 is a flowchart showing an operation control example of the FAW detector shown in FIG. 7,

FIG. 14: Example of DF / F725 operation timing chart during FAW detection operation,

15 is an I / O port 417, 418 and P / S converter 419 shown in FIG.
Block diagram showing a detailed configuration example of

FIG. 16 is a block diagram showing a configuration example of a reception FAS / BAS mask signal generation circuit,

FIG. 17 is a timing chart example of a reception FAS / BAS mask signal,

18 is a block diagram showing a detailed configuration example of the S / P converter shown in FIG.

19 is a block diagram showing a detailed configuration example of the folding port, the slot distributor, and the I / O ports 405 and 406 shown in FIG.

20 is a block diagram showing a detailed configuration example of the channel switcher, P / S converter 410, and I / O ports 407, 408 shown in FIG.

[Explanation of symbols]

301 Imaging unit 305 Video encoder 302 Sound Collection Department 306 Speech coding unit 317 Multiplexer 319 Line control unit 318 Separation unit 307-310 Video decoding unit 315 Display control unit 311 to 314 Speech decoding unit 316 Audio signal controller 320,321 LSD communication controller 322 Control 323 Overall control unit

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04L 12/56 H04M 3/00 H04M 3/56

Claims (5)

(57) [Claims] 1. A communication device connected to a communication line having a plurality of logical lines, the receiving unit outputting first serial data (521) composed of a plurality of data received from the communication line, Second serial data (525) obtained by delaying the first serial data by a predetermined amount based on the first synchronous clock (522 ).
A delay means (411) for outputting, first and second conversion means (411, 413) for converting serial data to parallel data, and one of the first and second serial data for the first Switching means (412) for inputting the other one to the second converting means, the first synchronous clock, and the first serial
Based on the signal (523) indicating the logical line that received the data,
Second have a generation means (509) for generating a synchronizing clock (528), each of said first and second conversion means, said second
Special data is input from the serial data string that is input in synchronization with the clock.
Detect the constant bit pattern and set the synchronization timing (752).
Generate the input serial according to its synchronization timing
A communication device that converts data into parallel data . 2. The communication device according to claim 1, wherein the communication line is an ISDN line. 3. The receiving means connects to the ITU-T from the communication line.
3. The communication device according to claim 1 or 2, which receives data having a frame structure defined in Recommendation H.221. Wherein said delay means communication apparatus according to any one of claims 1 to 3, characterized in that the delay data transmission unit of the logical line the first serial data. 5. A communication method for a communication device connected to a communication line having a plurality of logical lines, the first serial data comprising a plurality of data received from the communication line. To output second serial data obtained by delaying the first serial data by a predetermined amount based on the first synchronous clock, the first synchronous clock, and the first serial clock.
Based on the signal indicating the logical line that received the data, the second
When a synchronous clock is generated and each of the first and second serial data is converted into parallel data , the synchronous clock is generated in synchronization with the second clock.
Specific bit pattern from the input serial data string
To generate sync timing and
The input serial data into parallel data according to
A communication method characterized by conversion .