JPH05252176A - Input/output information control system for digital switching - Google Patents

Abstract

PURPOSE:To improve the efficiency of information transfer by transmitting a synchronous cell at the same (time slot) position for every frame, and sending an asynchronous cell to a free cell in the frame successively. CONSTITUTION:The synchronous cell which takes synchronism at every frame of 125mu on a switching bus is distinguished from the asynchronous cell set independently from the frame and arranged at a position, and transmission is performed by attaching information requiring real time processing on the synchronous cell, and information to permit waiting on the asynchronous cell. Such control is performed by a transmission control part 18. Therefore, a cell transmission part 17 receives the control of the transmission control part 18, and sends code information switched and accumulated at an asynchronous cell conversion part 13 and a synchronous cell information part 14 to a transmission line 22 in a cell format. In such a case, since a time slot position of respective octet in the synchronous cell can be effectively used, a means which sets one of line interface devices as a master device and attaches a master function on the transmission controller 18 is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output information control system for digital switching, in which a plurality of line interface devices for accommodating and connecting input / output lines transmit and output input / output information as digital codes on an exchange bus for exchange control. In particular, the present invention relates to an input / output information control system for digital switching that handles both data and voice, such as an intra-company switching network.

[0002]

2. Description of the Related Art Conventionally, in this type of digital switching input / output information control system, a line interface device for connecting an input / output line for inputting / outputting information to one side is connected to a switching bus which serves as one high-speed transmission line. The connection is established, and the exchange bus is used to connect to another incoming / outgoing line through another line interface device.

A variety of systems have been put to practical use, such as a ring-shaped exchange bus and a bus that uses a common bus under competitive control.

As a method for occupying the exchange bus, various transmission medium access methods described in, for example, the Electronic Information and Communication Handbook (edited by Institute of Electronics, Information and Communication Engineers, 1988 edition, PP2658-2661) can be listed.

In recent years, DQDB (Distributed Q) proposed as the IEEE802.6 standard has been proposed.
The UE Dual Bus method is about to become the mainstream of high-speed packet communication services. This system is applicable to both public networks and intra-company networks, and covers a natural multiple of 150 Mbps, which is considered in next-generation communication networks.

First, FIG. 6 is a relay system diagram showing an example in which a line interface device is connected to a ring-shaped switching bus. As shown in the figure, a plurality of line interface devices 91 are connected in a skewered pattern by an exchange bus 93, and the line interface device 91 connects the other end with a terminal 94.
Accommodates 2.

When the transmission information is received from the input / output line 92, the line interface device 91 sends the transmission information to the transmission path of the exchange bus 93.

Among the various access methods described above, the token access method is often used as a technique for transmitting the transmission information to the exchange bus 93.

In the token access method, one bus use right (token) is passed to the line interface device one after another in a predetermined order on the exchange bus. The line interface device, which has obtained the right to use the bus, can send out the transmission data requested from the incoming line through the exchange bus.

On the other hand, in the DQDB system, as shown in FIG. 5, a fixed-length (53 octet) digital code on the exchange bus is called a "cell", and a 5-bit octet at the neck is used as a header to identify a 20-bit channel. Including the number
The remaining 48 octets are used as the transfer information area, the area identification number is included in the first 2 octets, and the length information indicating the effective information length in the cell is included in the last 2 octets.

The central 44 octets of the transfer information area are transfer information.

[0012]

As described above, in the conventional digital exchange input / output information control system, in the case of the token access method, the dialogue voice which requires real-time processing interrupts the data transfer due to the bus use right. However, in the case of the DQDB method, the identification code of each cell is included, and especially in the cell of the asynchronous transfer mode, a header of 5 octets is required. Therefore, the transfer processing procedure or the octet position by the header is required. However, there is a problem in that the transmission capacity of the exchange bus is deteriorated.

An object of the present invention is to transmit voice information and the like on the exchange bus in octet units every 125 μs by frame synchronization, manage allocation in a cell usage status memory, and collect packet data in a plurality of cells for bus use. An object of the present invention is to provide an input / output information control system for digital exchange that solves the above problems by adopting a configuration of transmitting by rights.

[0014]

The basic configuration of the input / output information control system for digital switching according to the present invention is such that a plurality of line interface devices for accommodating and connecting input / output lines transmit the input / output information by digital codes on the exchange bus. In the input / output information control method of digital exchange for performing exchange control by means of a switch, a 125 μs frame is formed on the exchange bus by a plurality of cells forming a digital code to be transmitted into a fixed length information code,
When the line interface device receives, from the incoming line, either the voice information that requires real-time processing or the control information using the minority code, the cell in which this information is inserted in octets is used as a synchronization cell on the frame. While transmitting at the same position every 125 μs to the exchange bus, when the synchronous cell received from the exchange bus is received, octet unit information is taken out from the received cell and converted into predetermined information of the outgoing line. Call to this outgoing line,
Also, when a large amount of data information that allows a transmission delay is received from the incoming line, this data information is formed into one or more cells to make an asynchronous cell, and when the usage right on the exchange bus is obtained, on the frame While the cells are sequentially inserted into empty cell positions and transmitted to the exchange bus, when the asynchronous cell arriving from the exchange bus is received, data information is taken out from the received cell and converted into predetermined information of the output line, Send to.

When the exchange bus described in this basic configuration forms a ring, when the line interface device transmits the asynchronous cell, it sequentially transmits to the vacant cell position which is received from this exchange bus, and then from the exchange bus. The received synchronous cell and asynchronous cell may be directly transferred to the exchange bus.

Further, when the line interface device described in the basic configuration transmits the asynchronous cell, when the bus usage right (token) is received from the exchange bus, the idle cell positions are sequentially received on the exchange bus. The right of use may be transmitted to a predetermined next-order device when all the asynchronous cells have been transmitted, and the synchronous cell received from the exchange bus may be directly transferred to the exchange bus.

The first predetermined number of bit codes for each frame described in the basic configuration form a frame header containing cell position information assigned to a synchronization cell in this frame, and the frame is provided in each cell. The frame header may be created by either one of the means for giving the right to use the inner cell position and the means for monitoring the cell position on this frame to know the usage status.

Further, the first cell of each frame described in the above basic structure is used as a frame header, and the synchronization / asynchronization of each cell in this frame and the presence or absence of the header of each cell are arranged in this frame header, received and fetched. Cells may be processed according to the notification information of the frame header.

Further, in one embodiment of the basic configuration, a control bus connects between the plurality of line interface devices connected to the one exchange bus, and one of these line interface devices becomes a master device. The master device assigns a cell position to be used on the exchange bus to each of the line interface devices via the control bus upon request and gives the right to use the originating cell.

The master device according to this embodiment is
The cell positions for transmitting the synchronous cells are preset in the frame in a predetermined number range that is continuous according to traffic, and the allocation of the synchronous cells is determined, and the usage status of each cell position in the frame is notified. You may.

Further, the master device described in the above-mentioned specific configuration notifies the line interface devices of the synchronization / asynchronization of each cell and the presence / absence of a header of each cell for each frame via the control bus. You may notify.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A digital exchange input / output information control system of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the illustrated line interface device 10, the receiving path 21 and the transmitting path 22 of the exchange bus 20 are connected to one side, and the outgoing line 31 and the incoming line 32 of the multiplexed outgoing and incoming line 30 are connected to the other side.

The cell receiving unit 11 of the line interface device 10 receives a cell on the exchange bus 20 from the receiving path 21. The cell type determination unit 12 determines the cell type received by the cell reception unit 11, that is, whether it is a synchronous cell or an asynchronous cell.

Synchronous cells are dialogue voices that require real-time processing,
Also, because of the small number code, it carries control information that can be transmitted in octet units, and the asynchronous cell carries data information that allows queuing. Voice information such as voice mail can be carried by asynchronous cells.

The asynchronous cell conversion unit 13 is a cell type determination unit 1
Asynchronous cells are received from 2 and output to the output line 31, converted and accumulated into an information format, output from the multiplexing transmission unit 15, and input from the input line 32 with the data separated by the reception separation unit 16 to be asynchronous. Cell transmission unit 1
7 to output on the transmission path 22.

The synchronous cell information unit 14 is a cell type determination unit 1
2 inputs the synchronous cell discriminated and received from the cell receiving unit 11, extracts information in octet units from the time slot in the cell according to an instruction from the transmission control unit 18, and outputs the outgoing line 3
It is converted into information to be output to 1 and accumulated, and is sent out under the control of the multiplexing transmission unit 15.

Further, the sync cell information unit 14 inputs and stores the voice information and the control information for requesting the transmission in units of octets separated and identified by the reception / separation unit 16 from the incoming line 32.

Under the control of the transmission control unit 18, the cell transmission unit 17 inserts this accumulated information into a predetermined time slot position in the synchronous cell and transmits it.

The multiplexing transmission section 15 multiplexes the input data and voice information and outputs the multiplexed information to the outgoing line.
6 outputs the multiplexed information input from the input line 32 to the synchronous cell information unit 14 or the asynchronous cell conversion unit 13 by separating and separating the data and voice information for each channel according to the necessity of octet unit transmission.

A feature of the present invention is that 125 μs is on the exchange bus.
Information that requires real-time processing is provided for synchronous cells, and information that allows waiting is provided for asynchronous cells, by distinguishing between synchronous cells that synchronize on a frame-by-frame basis and asynchronous cells that are placed at empty positions independently of the frame. Put and transmit. This is controlled by the transmission controller 18.

Therefore, the cell transmission unit 17 has the transmission control unit 18
Under the control of, the code information converted and accumulated by the asynchronous cell conversion unit 13 and the synchronous cell information unit 14 is sent to the transmission path 22 in the cell formation.

In order to effectively use the time slot position of each octet in the sync cell, one of the line interface devices is a master device, and there is a means for giving a master function to the transmission control device 18.

The master device has a cell usage memory 19
Obtains and stores the usage status of each octet position in the synchronous cell on the exchange bus 20 from the cell type determination unit 12, and connects the other octet positions with other devices via the control bus 40.

The transmission control unit 18 of the master device is connected to the transmission control unit 18 of the other line interface device 10 and the control bus 4.
0 is connected, the cell use status is notified at the request of the transmission control unit 18, and the time slot position is assigned at the use request.

When the exchange bus 20 is a single common bus as shown in FIG. 1, all the line interface devices 10
Therefore, the connection between the cell receiving unit and the cell transmitting unit is unnecessary.

When the exchange bus 20 separates into a reception path and a transmission path, the master device couples the reception path to the transmission path by transferring the information code on the exchange bus from the cell reception section to the cell transmission section.

When the exchange bus 20 is ring-shaped, all the line interface devices have a connection configuration in which the cell reception unit receives the transmission code information from the reception path and transfers the transmission code information other than the incoming call information to the transmission path.

The cell type determining unit 12 other than the master device may determine only the incoming call information. Further, the transmission control unit 18 may obtain information from the master device and directly control the cell type determination unit 12 without having the cell usage memory 19.

Of course, all line interface devices 1
0 has components having the same function, and the function processing is a means for distinguishing between the master device and the other devices, and the hardware is unified.

Next, referring to FIG. 2A together with FIG. 1, the procedure for transmitting the synchronous cell information onto the exchange bus will be described. FIG. 2A is a flowchart showing an example of the procedure for transmitting the synchronized cell information in FIG.

Normally, in voice information transmission that requires real-time processing, a position setting request (101) on the exchange bus 20 for synchronous cell information corresponding to an incoming line occurs at the time of calling, and the line interface device 10 that has received the request. The control bus 40 and the transmission controller 18 are added to the cell usage memory 19 of the master device.
Since a request for vacant position check and setting (102) is requested via the, the master device registers (103) the position on the frame corresponding to the line set in the cell usage memory 19 and notifies the request source.

Thereafter, unless the line is disconnected (104), the sync cell information received (105) from the incoming line 32 through the reception separation unit 16 in the sync cell information unit 14 is transferred to
It is converted into an 8-bit (octet) code and transmitted (106) in synchronization with each frame at one time slot position in the synchronization cell registered for the line.

When the line is disconnected in step 104, the line interface device 10 deletes the position registration of the cell usage status memory 19 of the master device via the control bus 40 together with the built-in memory (107).

In the description of the present embodiment, the control bus 40 is used to exchange the cell usage status with the master device, but a predetermined cell position on the exchange bus 20, a header or a special usage status cell is used. You can also

Next, referring to FIG. 2B together with FIG. 1, a transmission procedure by the asynchronous cell will be described. FIG. 2B is a flowchart showing an example of the asynchronous cell transmission procedure of FIG.

First, the case where the bus access right is acquired by the token access method will be described. In this method, the exchange bus may be a common bus or a ring bus.

The line interface device 10 receives the tokens (asynchronous cells having the bus use right) in a predetermined order, and the cell type judging unit 12 judges and confirms (11
When 1), the cell transmitting unit 17 checks whether there is an asynchronous cell waiting to be transmitted in the asynchronous cell converting unit 13 (11
2) Do.

If there is an asynchronous cell waiting to be transmitted, an empty cell on the exchange bus 20 is searched (113), asynchronous cells are sequentially transmitted to the empty cell position (114), the transmission is completed, and the waiting asynchronous cell is reached in step 112. When the cell is exhausted, the token is transmitted to the next device in the sequence to transfer the bus use right (11
5) Do.

Although the token access method has been described in the present embodiment, even if the competing system for the common bus is another means, when there is an asynchronous cell waiting for transmission, a request for the bus usage right is issued to secure the bus usage right. By doing so, the asynchronous cell can be transmitted to the empty cell position.

Further, in the ring bus, an asynchronous cell can be transmitted to an empty cell position on the frame at each line interface section.

FIG. 3 is a time chart showing an example of cell arrangement on the exchange bus. Synchronous cells A, B, and C are arranged at the same time slot position every 125 μs frame on the illustrated switching bus.

In this state, from the incoming line to the synchronous cell information section 14
The voice or control information received via the is specified and inserted in vacant positions of the synchronization cells A, B, and C in units of octets.
If there is no information to be transmitted, the synchronous cell B will be in an empty cell position in the next frame.

The data information D, F, G received from the incoming line via the asynchronous cell conversion unit 13 forms an asynchronous cell, waits for the transfer of the synchronous cells A, B, C on the exchange bus 20, and becomes empty. It is sent to the cell position.

The data information F has a free space at the time of receiving the information and one asynchronous cell is transmitted. However, since the synchronous cell A is at the next cell position, the second asynchronous cell is the empty cell next to the synchronous cell A. Sent to a position.

Since the data information G is received after the data information F, it is sent to the next empty cell position after the sending of the data information F to the exchange bus 20 is completed.

Next, the frame header for notifying the usage status of mixed synchronous / asynchronous cells will be described with reference to FIG. When the first cell is the frame header,
This is called a template cell.

In FIG. 4A, the 125 μs frame is (N +
1) It has a cell, sets the bit position corresponding to the number N of cells in this frame header with the first cell as the frame header, and synchronizes with the binary code 1 for each of the cell numbers 1 to N, and binary The code 0 indicates an asynchronous or empty transmission cell position.

In FIG. 4A, normally, each cell sets a binary code 0 for asynchronous cell transfer, and at the time of transfer of a synchronous cell occupying the same position in each frame, the same cell is released until the synchronous cell is eliminated. A binary code 1 is set at the cell position to prevent interruption of an asynchronous cell.

In FIG. 4B, the first cell of the 125 μs frame is used as the frame header as in FIG. 4A.
For cell numbers 1 to N, synchronization of transfer method /
The presence or absence of asynchronous and cell header is indicated by a binary code.

Since the synchronous cells occupy the same position for each frame, the synchronous transfer method is used, and the asynchronous transfer method is applied to the asynchronous cells that use consecutive cell positions.

In both the synchronous cell and the asynchronous cell, if the first cell includes the identification number, the cell header can be omitted in the subsequent cells, and all fixed length cells can be used in the transfer information. A binary code 0 without a cell header is written in a cell in which the cell header is omitted.

FIG. 4C shows an example in which the cell type of FIG. 4A is divided into two and the area is encoded and included in the frame header. This area can be variable.

[0064]

As described above, according to the input / output information control system of the digital exchange of the present invention, 1 is provided on the exchange bus.
While constructing a 25 μs frame, the transmission information is placed on a cell with a fixed-length digital code, and a synchronous cell that requires real-time processing and an asynchronous cell that allows queuing are provided. The synchronous cell is the same for each frame (time slot). )
While transmitting at the position, asynchronous cells are continuously sent to empty cells in the frame so that voice and data can coexist on a high-speed exchange bus and packet transfer by the conventional token access method can also be used. This can be easily realized in the transfer gap, and a part of the header in the cell unit by the DQDB method can be deleted, so that the effect of improving the efficiency of information transfer can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an input / output information control system for digital exchange according to the present invention.

FIG. 2A is a flowchart showing an example of a procedure for transmitting synchronous cell information according to FIG. (B) is a flow chart showing an example of a transmission procedure of an asynchronous cell according to FIG. 1.

FIG. 3 is a time chart showing an example of a cell array on an exchange bus according to the present invention.

FIG. 4 is a frame configuration diagram showing an example of a frame header according to the present invention.

FIG. 5 is a frame configuration diagram showing an example of a cell configuration according to the DQDB method.

FIG. 6 is a relay system diagram showing an example of interconnection between a line interface device and a switching bus.

[Explanation of symbols]

 10 line interface device 11 cell receiving unit 12 cell type determining unit 13 asynchronous cell converting unit 14 synchronous cell information unit 15 multiplexing transmitting unit 16 receiving / separating unit 17 cell transmitting unit 18 transmission control unit 19 cell usage memory 20 switching bus 21 Receiving channel 22 Transmitting channel 30 Multiplexing in / out line 31 Outgoing line 32 Incoming line 40 Control bus

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 8529-5K H04L 11/20 Z

Claims (8)

[Claims] 1. A digital switching input / output information control system in which a plurality of line interface devices for accommodating and connecting incoming / outgoing lines transmit input / output information by digital codes onto a switching bus for switching control, wherein A 125 μs frame is formed by a plurality of cells that form a digital code to be transmitted into a fixed length information code, and the line interface device inputs either voice information that requires real-time processing or control information using a minority code. When received from the line, the cell into which this information is inserted in octet units is placed as the synchronization cell in the same position on the frame every 125 μs and is transmitted to the exchange bus, while the synchronization cell is received from the exchange bus. Octet unit information is extracted from the received cell, converted to the specified information of the outgoing line, and sent to this outgoing line. Outgoing,
Also, when a large amount of data information that allows transmission delay is received from the incoming line, this data information is formed into one or more cells to make it an asynchronous cell. While the cells are sequentially inserted into the empty cell positions of the cells and transmitted to the exchange bus, when the asynchronous cell arriving from the exchange bus is received, the data information is extracted from the received cells and converted into the predetermined information of the outgoing line, A digital switching input / output information control method characterized by transmitting to a line. 2. When the switching bus forms a ring, when the line interface device transmits the asynchronous cell, it sequentially transmits to an empty cell position which is received from the switching bus, and synchronization which is received from the switching bus. 2. An input / output information control system for digital switching according to claim 1, wherein the cells and the asynchronous cells are transferred to the switching bus as they are. 3. When the line interface device transmits the asynchronous cell, when the bus use right (token) is received from the exchange bus, the line interface device sequentially transmits to the empty cell position to be received by the exchange bus, 2. The digital switching system according to claim 1, wherein when the transmission of all asynchronous cells is completed, the usage right is transmitted to a predetermined next-order device, while the synchronous cells received from the exchange bus are directly transferred to the exchange bus. Input / output information control method. 4. The first predetermined number of bit-codes for each frame forms a frame header containing cell location information assigned to sync cells within this frame, and each cell uses the intra-frame cell location. 2. The input / output information control for digital switching according to claim 1, wherein either one of the means for giving a right and the means for monitoring the position of each cell on the frame to know the use status creates the frame header. method. 5. The first cell of each frame is used as a frame header, and the synchronization / asynchronization of each cell in this frame and the presence / absence of a header of each cell are arranged in this frame header, and the cell received and captured is the frame. 2. An input / output information control system for digital exchange according to claim 1, wherein processing is performed according to the notification information in the header. 6. A control bus connects between a plurality of said line interface devices connected to one said exchange bus, and one of these line interface devices becomes a master device, and this master device is connected via said control bus. 2. The input / output information control system for digital switching according to claim 1, wherein a cell position to be used on the exchange bus is allocated to each of the line interface devices upon request to give a right to use the transmission cell. 7. The master device preliminarily sets cell positions for transmitting the synchronous cells in a predetermined number range that is continuous according to traffic on the frame, determines the allocation of the synchronous cells, and 7. An input / output information control system for digital switching according to claim 6, wherein the use status of each cell position in the inside is notified. 8. The master device notifies each of the line interface devices via the control bus of the synchronization / asynchronization of each cell for each frame and the presence / absence of a header of each cell. The digital exchange input / output information control system according to claim 6.