JPH0245879B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention is applicable not only to time slot replacement in a time division switch of a time division exchange, etc.
It relates to a time switch for speed conversion and also for multiplexing or demultiplexing.

[Background of the invention]

In the current digital telephone network, the voice signal has a cycle of 125 μs and a data rate of 64 kb/cycle of 8 bits/cycle.
It is exchanged and transmitted as a digital signal. Therefore, time-division switching equipment used in digital telephone networks is generally developed to perform switching in units of 64 kb/s.

On the other hand, in order to economically support services such as facsimile communication, data communication, etc., where speeds of less than 64 kb/s are sufficient, 8 kb/s x N
There is a strong desire to realize a multi-speed digital network that can handle multiple speeds (N=1, 2, 3, 8).

FIG. 1 is a block diagram of an example of a communication path system of a conventional time-division exchange compatible with a multi-dimensional digital network.

Here, 1 is a time division switch with a configuration of T (time switch) x S (spatial switch) x T (time switch), and 2 is a bearer multiplexed signal (at a bearer speed specific to the terminal etc.) from the transmission path 101. A bearer universal multiplex converter 3 converts a multiplexed signal into a universal signal (a basic speed signal for time division exchange obtained by speed converting the bearer signal, for example, a 64 kb/s signal); The signal is converted into a bearer multiplexed signal and sent to the transmission path 104.
This is a universal bearer multiplexing conversion device that sends data to

Such conversion to a universal signal is necessary for each of the multiple speeds, since operations within a time division exchange are generally performed using the above-mentioned basic speed signal.

On the transmission line 101, 8kb/s×N (N=1,
2, 4) 8/N lines of signals are multiplexed into one time slot of 64 kb/s. (Of course, bearer multiplexing is not possible for a bearer speed of 64 kb/s with N=8.) The bearer universal multiplex converter 2 converts the input into N universal signals (64 kb/s) and transmits them to the internal highway 10.
Send to 2.

This universal signal is transmitted by time division switch 1.
After being exchanged in units of 64 kb/s, it is input to the universal bearer multiplex conversion device 3 via the internal highway 103, where it is inversely converted into a bearer multiplexed signal and sent to the transmission path 104.

Furthermore, both of the above multiplex conversion devices 2 and 3 will be explained in detail.

First, FIG. 2 is a block diagram of an example of a bearer universal multiplex conversion device.

Here, 21 is a separation circuit, 22, 23, 24
8 kb/s x 8 bearer multiplexed signal to universal signal (64 kb/s) x 8, 16 kb/s
a conversion circuit for converting an s×4 bearer multiplexed signal into a universal signal and a 32kb/s×2 bearer multiplexed signal into a universal signal×2;
25 is a multiplexing circuit.

The transmission path 101 includes time slot #1 with 8 kb/s x 8 bearers multiplexed, time slot #2 with 16 kb/s x 4 bearers multiplexed,
It consists of time slot #3 for 32 kb/s x 2 and time slot #4 for signals with a bearer rate of 64 kb/s.

The separation circuit 21 separates each of the above signals according to the time slots #1 to #4 and sends them to the corresponding leads 26,
Output to 27, 28, 29.

Conversion circuits 22, 23, 24 each bearer speed
It is provided for 8kb/s, 16kb/s, and 32kb/s, and separates each bearer multiplex and converts each bearer speed to the universal speed (64kb/s), and transfers it to leads 26A, 27A, and 28. Send.

The universal signal obtained in this way is
The internal highway 1 is multiplexed by the multiplexing circuit 25.
02. Furthermore, the bearer speed is 64kb/s.
There is no need to perform speed conversion on the signals, and after being separated by the separation circuit 21, they are immediately input to the multiplexing circuit 25.

Next, FIG. 3 is a block diagram of an example of a universal bearer multiplex conversion device.

Here, 31 is a separation circuit, 32, 33, 34
are each 8kb/s universal signal x 8
×8 bearer multiplexed signal, universal signal ×
4 to a 16 kb/s x 4 bearer multiplex signal, and a conversion circuit 35 for converting the universal signal x 2 to a 32 kb/s x 2 bearer multiplex signal,
It is a multiplexing circuit.

Internal highway 103 has a bearer speed of 8kb/s
Time slots #1 to #8 of the universal signal for signals with a bearer speed of 16 kb/s, time slots #9 to #12 of the universal signal for signals with a bearer speed of 16 kb/s, and a bearer speed of 16 kb/s.
Same time slot #1 for 32kb/s signal
3, #14 and a time slot #15 of a signal with a bearer speed of 64 kb/s.

The separation circuit 31 separates each of the above signals for each time slot #1 to #15, and #1 to #8 are sent to the lead 36, #9 to #12 are sent to the lead 37, and #13 and #14 are sent to the lead 37. The signal #15 is sent to the lead 38 and the signal #15 is sent to the lead 39.

Conversion circuits 32, 33, 34 each bearer speed
It is equipped to support 8kb/s, 16kb/s, and 32kb/s, and performs speed conversion from universal signal to bearer signal in accordance with each bearer speed.
Performs bearer multiplexing at 64kb/s.

The 64 kb/s bearer multiplexed signal thus obtained is sent to leads 36A, 37A, and 38A, and together with the 64 kb/s signal on lead 39,
The signals are multiplexed by the multiplexing circuit 35 and sent to the transmission line 104.

As described above, the above-mentioned conventional example is uneconomical because it requires separate multiplex converters 2 and 3, which are quite complicated, before and after the time division switch 1. is allocated in a fixed manner, making it impossible to flexibly deal with traffic fluctuations between bearer speeds.

This means that the time division switch 1 is, for example, T×
It has an S×T configuration and is designed to perform exchange only at a basic speed of 64kb/s.In particular, as a time switch T, there is only a fixed time slot switching function in 64kb/s units, and the bearer This is because there was no one that also had the functions of speed conversion between signals and universal signals and bearer multiplexing/demultiplexing.

[Purpose of the invention]

An object of the present invention is to overcome the difficulties of the prior art described above, eliminate the need for special equipment for speed conversion between bearer signals and universal signals, and for bearer multiplexing, and eliminate the need for special equipment for speed conversion between bearer signals and universal signals, and eliminate the need for special equipment for speed conversion between bearer signals and universal signals. An object of the present invention is to provide a time switch for realizing a flexible time division switch.

[Summary of the invention]

The configuration of the time switch according to the present invention allows data to be written from the incoming highway only to separately designated bit positions in synchronization with the variable address designation corresponding to each time slot. a communication path memory that performs reading by specifying a fixed address corresponding to each time slot of an outgoing highway; and a write control circuit that specifies a write bit position in the communication path memory based on a write mode specification. , and a holding memory for providing variable address designation to the communication path memory and write mode designation to the write control circuit.

In short, this is to convert a universal signal into a bearer multiplexed signal by performing random writing and sequential reading of the channel memory, and by variably controlling the writing on a bit-by-bit basis.

Therefore, by using this time switch as the final stage switch of the time division switch,
This eliminates the need for the universal bearer multiplex conversion device 3 in the conventional example described above, thereby achieving significant economical savings.

[Embodiments of the invention]

Embodiments of the present invention will be described below based on the drawings.

First, FIG. 4 is a block diagram of an embodiment of a time switch according to the present invention, and FIG. 5 is a timing chart of its main parts.

Here, 10 is an 8-bit shift register, 1
1 is an 8-bit register, 12 is an 8-bit, 4-word channel memory, 13 is a write control circuit, and 14 is an 8-bit register.
Bit register 15 is a counter, 16 is a 7-bit, 16-word holding memory. Note that each waveform in FIG. 5 is given the same number as the corresponding lead number in FIG. 4.

The input highway 201 is, for example, a 1024 kb/s highway in which 16 time slots TS0 to TS15 each having an 8-bit structure are multiplexed at an 8 kHz cycle.
The data is transferred to shift register 10 from clock 2.
02, shifted by one time slot, and set in parallel in register 11 by clock 203.

The holding memory 16 sets a write mode for specifying the write address to the communication path memory 12 and the bit position and speed class to be written for the input highway 201 data set in the register 11, corresponding to the time slot of the input highway 201. I remember it.

The counter 15 outputs a count value synchronized with the time slot number of the incoming highway 201 to the address line 21.
5 to determine the read address of the holding memory 16.

The read result is designated as the write address of the channel memory 12 through the lead 217 (variable address designation). In addition, other reading results are as follows.
The signal is input to the write control circuit 13 through the lead 216, and the write control circuit 13 outputs a write bit designation 207 based on it. That is, the data on the incoming highway 201 is stored in the lead 2 at the address in the communication path memory 12 specified by the lead 217.
Only the bits designated by 07 are written.

On the other hand, reading of the communication path memory 12 is performed sequentially according to the output 214 of the counter 15 (fixed address designation), and is set in the register 14 at the timing of the clock 210.

Next, time slot of input highway 201
The bearer speed is 32kb/s and 64kb/s for TS1 and TS2.
The operation of this time switch will be explained in more detail by taking as an example a case where a signal converted into an s universal signal is allocated and this signal is multiplexed and output to time slot TS3 of outgoing highway 208. For other examples, see Section 6 below.
Since it is easy to make an analogy from FIGS.

FIG. 6 is a format diagram of the connection command, and shows the format of the connection command sent to the holding memory 16. FIG. 6 is an explanatory diagram of the write control truth value, showing the truth value of the write control circuit 13 and the relationship between the write mode and enable signal for each speed class.
Note that in FIG. 7, the x mark indicates that the value may be either 0 or 1.

The controller of the exchange, which is not shown in the figure, specifies the input time slot, output time slot, and write mode (speed class, bit position specification) using the address bus 212 and data bus 211, and writes to the clock line 213. Memory 1 held by input signal
Write the connection command to 6. That is, data "1010000" is written to address "0001" of the holding memory 16 by the first connection command, and data "1010001" is written to address "0010" by the second connection command.

At the timing corresponding to the time slot TS1 of the input highway 201, the stored content "1010000" at the address "0001" of the holding memory 16 is read out, and the upper two bits corresponding to the output time slot O ₁ O ₂ =
“10” is the write address WA of the communication path memory 12
1 and 2 are input.

In addition, the upper 2 bits of the above data (O ₃ O ₄ )
“10” corresponds to a bearer speed class of 32kb/s, for example “00” to a speed class of 8kb/s, “01” to a speed class of 16kb/s, and “11” to a speed class of 16kb/s. corresponds to a speed class of 64 kb/s.

In addition, the lower 5 bits O ₃ corresponding to the write mode
~O ₇ =“10000” is input to the control inputs C1 to C5 of the write control circuit 13.

The write control circuit 13 controls the enable terminals G1, G3,
“1” for G2, 4, 6, and 8, “0” for G2, 4, 6, and 8
Output.

Data "aacceegg" of time slot TS1 of input highway 201 is given to inputs I1 to I8 of communication path memory 12, but only the bits for which the corresponding enable signals G1 to G8 are "1", that is, data "aceg" of odd number bits, are applied. ” is written to address 2.

Similarly, in response to the second connection command, even-numbered bit data "bdfh" in the data "bbddffhh" of time slot TS2 of the incoming highway 201 is
is written to address 2 of the communication path memory 12.

As a result, the address 2 of the channel memory 12 contains the 32kb/32kb data of the time slots TS1 and TS2.
Data "abcdefgh" obtained by bearer multiplexing the data of s will be written.

In this way, even in the case of a large number of speed classes, it is possible to multiplex and write the signals converted to the original bearer speed from the universal signals on 201 that have been similarly converted into the communication path memory 12.

The above contents of address 2 of the communication path memory 12 are the time slot of the outgoing highway 208.
It is read at a timing corresponding to TS2.

Note that in the above embodiment, the communication path memory 12
has a gate function (enable terminals G1 to G8) that allows selective writing in bit units, but the same function cannot be achieved even if a memory element without such a function is used. can.

FIG. 8 is a block diagram of a channel memory in another embodiment of the time switch according to the present invention, which may replace channel memory 12 of FIG. 4.

Here, 12A is a channel memory element, 12B,
12C is a selector, and the same signal lines as in FIG. 4 are given the same reference numerals.

When writing data to the register 14, read addresses RA1 and RA2 of the channel memory element 12A are used.
The selector 12C is controlled so that the value of the signal line 214 or the signal line 217 is input to the signal line 214 or the signal line 217.

Furthermore, when writing data from the input highway 201 to the communication path memory element 12, the output signal 207 of the write control circuit 13 selects the input highway data 205 and the stored data 206 at the corresponding address of the communication path memory element 12A to the selector 12B.
to select and write. As a result, the channel memory element 12A, selectors 12B, 12C
can realize the same function as the communication path memory 12 shown in FIG.

[Effects of the Invention] As is clear from the description of each of the above embodiments, according to the present invention, compared to the conventional time switch, the bit width of the holding memory can be expanded and the channel memory can be selected in bit units. By simply adding the physical write function, it becomes possible to handle signals at multiple bearer speeds, making the time division switch significantly more economical, and the amount of traffic that can be handled is the sum of the traffic of each bearer signal. Since it depends only on the traffic ratio of each bearer signal and does not depend on the traffic ratio of each bearer signal, extremely large flexibility can be obtained with respect to traffic fluctuations between bearer signals, and the effect is remarkable.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an example of a communication path system of a conventional time division switch compatible with a multi-dimensional digital network, Fig. 2 is a block diagram of an example of a bearer universal multiplex converter, and Fig. 3 is a block diagram of an example of a bearer universal multiplex converter. FIG. 4 is a block diagram of an example of a bearer multiplex conversion device; FIG. 4 is a block diagram of an embodiment of a time switch according to the present invention; FIG. 5 is a timing chart of its main parts;
FIG. 6 is a format diagram of the connection command, FIG. 7 is an explanatory diagram of the write control truth value, and FIG. 8 is a block diagram of the channel memory in another embodiment of the time switch according to the present invention. be. 10...shift register, 11...register,
12... Channel memory, 12A... Channel memory element, 12B, 12C... Selector, 13... Write control circuit, 14... Register, 15... Counter, 16... Holding memory.

Claims (1)

[Scope of Claims] 1. Data can be written from an incoming highway to a separately specified bit position according to variable addressing corresponding to each time slot, and data can be read out at each time slot of an outgoing highway. a communication path memory for specifying a fixed address corresponding to a lot; a write control means for specifying a write bit position in the communication path memory based on a write mode specification; A time switch comprising a control means for specifying a mode. 2. In what is stated in claim 1,
A time switch characterized in that the write mode designation for the write control means consists of a speed class and a write bit position designation. 3. In the device described in claim 1 or 2, the bit length of each time slot is 8, and the speed class is 64 kb/s, 32 kb/s,
A time switch characterized in that the speed is either 16 kb/s or 8 kb/s, or any combination thereof. 4 In what is stated in claim 3,
A time switch characterized in that in a write mode of speed class 64 kb/s, all 8 bits input to the communication path memory are written. 5 In what is stated in claim 3,
A time switch characterized in that, in a write mode of a speed class of 32 kb/s, only the even or odd bits of the 8 bits input to the communication path memory are written. 6 In what is stated in claim 3,
In the write mode of speed class 16kb/s, only one bit of each of the upper and lower four bits of the eight input bits input to the communication path memory is written, according to the bit position specified. A time switch characterized by: 7 In what is stated in claim 3,
A time switch characterized in that, in a write mode of a speed class of 8 kb/s, only one bit of the 8 bits input to the communication path memory, the bit position of which is specified, is written. 8 In what is stated in claim 1,
A time switch characterized in that the control means for giving the variable address designation and the write mode designation is configured to give the variable address designation and the write mode designation synchronously. 9 In what is stated in claim 8,
A time switch characterized in that the synchronized control described above is performed by a holding memory.