JPS62120740A - Signal multiplexing circuit - Google Patents

Abstract

PURPOSE:To simplify circuit constitution by writing an N-series PCM signal synchronized by a staff control section in a duplicated memory and reading the signal at a high speed to apply multiplexing the signal in the unit of voice channel. CONSTITUTION:The staff control section 1 synchronizes #1-#N PCM signals by using a read pulse or a clock from a memory write control section 51 at first and the result is fed to the duplicated memory 6. The memory is a large capacity speed converting memory comprising plural random access memory ICs, for example, and when the one part is in writing operation, the other part applies read operation. Then the #1-#N PCM signals to be inputted are written in memories 621-62N, the address of the PCM signal already written in memories 611-61N in a line assignment table 53 scanned by a scan signal from a memory read control section 52 driven by the read timing from a memory write control section 51 is fed sequentially to the memories 611-61N via a changeover control section 54 and the corresponding part is read.

Description

[Detailed Description of the Invention] [Summary] In the signal multiplexing circuit, after writing the N series of PC1'l signals synchronized by the stuff control unit into the corresponding duplex memories, TaP
Since the CM signal is read out at high speed and multiplexed at any position on the time axis, the circuit configuration is simplified. [Field of Industrial Application] - The present invention relates to an improvement of a signal multiplexing circuit used, for example, in a TDMA i star communication device.

In the case of TDMA communication, the sanitary communication channel (hereinafter referred to as c
(abbreviated as h) is allocated to audio Ch (64Kbit/s
) units may be used. For example, 64Kbit/
In the case of s x 24Ch = 1536Kbit/s, there are cases where 24 units of 6tKtrit/s x ICh are allocated as a unit burst, and cases where 64Kbit x 2ACh is allocated with variable burst length, but depending on the equipment. The former is often used because of the ease of configuration ρ.

On the other hand, the signal multiplexing circuit for PCM generally changes to a higher order group by performing bi-node multiplexing after adjusting the signal speed using the Val:Susta-Nov technique.
To multiplex in units, it is necessary to separate the bits of the bit multiplexed data and then rearrange the bits.

Therefore, there is a need for a signal multiplexing circuit that can easily multiplex audio channels.

[Conventional technology]

FIG. 3 is a block diagram of a conventional example, and FIG. 4 is an explanatory diagram of the operation of FIG. 3. Note that the numbers on the left side of FIG. 4 indicate the signal formats of the portions with the same numbers in FIG. Therefore, the fourth
The operation shown in FIG. 3 will be explained with reference to the drawings.

In FIG. 3, for example, the asynchronous PCM signals #1 to IN (the number of channels is 24) are added to the stuffing control unit 1, read out at a clock slightly earlier than the clock of this PCM signal, and stuffed at the necessary locations. As shown in Figure 4-■, by inserting multiple bits, the I
A PCM signal of I l-I N is obtained. Therefore, this is further added to the bit multiplexing section 2, and only the bo bits of the #l-ffN PCM signals are collected and multiplexed, as shown in FIG.

However, when the satellite line is allocated in units of audio channels as described above, this must be converted accordingly, so the output of the bit multiplexer 2 is added to the bit separator 3,
For example, only the Ch 1 bits of the #I PCM signal are separated and rearranged by the bit rearrangement unit 4. Next, Ch 2
After rearranging the signals from #2 to #24, this is repeated from #2 to IN to obtain a multiplexed PCM signal rearranged in units of audio channels as shown in FIG. 4--.

[Problem that the invention seeks to solve]

As explained above, the bit multiplexed data is separated into bits, bits are rearranged, and converted into audio channels.
There is a problem that the circuit configuration becomes complicated.

[Means for solving problems]

The above problem is caused by N-series asynchronous PCs, as shown in Figure 1.
A stuff control section 1 synchronizes the M signal, and writes the output of the stuff control section into a first memory according to a control signal from the ° control section 5, and also writes the output of the stuff control section already written into the second memory. a duplex memory section 6 for reading out the output of the duplex memory section; an output selection switching section 7 for multiplexing and outputting the PCM signal read from the duplex memory section; the stuff control section, the duplex memory, and the output. This problem is solved by the signal multiplexing circuit of the present invention, which includes a control section 5 that controls the operation of the selection switching section.

(Function) The present invention provides N-series PCM synchronized by the stuff control unit l.
By writing the signals into the duplexing memory 6 and reading them out at high speed, multiplexing can be performed in units of audio channels. That is, after writing the synchronized PCM signals of #1 to flN into the duplex memory, the PCM signals for each audio channel written to the address specified in the line allocation table 53 are written on the time axis. The circuit configuration is simplified because the data is read out at an arbitrary position above at high speed and multiplexed by the output selection switching unit 7.

〔Example〕

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is an explanatory diagram of the operation of FIG. 1. The same symbols indicate the same objects throughout the figures, and the numbers on the left side of Figure 2 indicate the signal formats of the parts with the same numbers in Figure 1. Explain the operation.

First, the PCM signals #1 to #N1 are synchronized by the stuff control unit 1 using read pulses and clocks from the memory write control unit 51 as shown in FIG. Added. This memory is a large-capacity speed converting memory composed of a plurality of IC-based random access memories, for example, and when one is in a write operation, the other is in a read operation.

On the other hand, since the address is applied from the memory write control section 51 to, for example, the memories 611 to 61N via the switching control section 54, the PCM signals #1 to #N are written to the corresponding memories at low speed. Then, when a prescribed number of writes (for example, one frame of a PCM signal) is completed, the switching control unit 54 switches the memories 621 to 62N on the opposite side to the write side in response to a command from the memory write control unit 51.
11 to 61N are switched to the read side, and the output selection switching section 7 is also connected to the memories 611 to 61N.

Therefore, the next input PCM signals #1 to tlN are written to the memories 621 to 62N, but the memories 611 to 61
The PCM signal already written to N is sent to the memory write control unit 5.
The address in the line allocation table 53 (the address that you want to read is set in the table based on the line allocation information from the reference station) scanned by the scan signal from the memory read control unit 52, which is driven at the read timing from 1. is connected to the memories 611 to 61 via the switching control unit 54.
The corresponding portions are sequentially added to N and read out.

At this time, if the read timing signal is determined in advance for each memory, the necessary PCM signal can be obtained for each audio channel at any position on the time axis, as shown in FIG. Therefore,
When extracted through the output selection switching section 7, a PCM signal multiplexed in units of audio channels is obtained as shown in FIG. 2--.

This eliminates the need for a bit multiplexing section, a bit separating section, and a bit rearranging section, thereby simplifying the circuit configuration.

〔Effect of the invention〕

As described above, since the PCM signal multiplexed in audio units is obtained using the duplex memory, the circuit configuration is simplified.

[Brief explanation of drawings]

1 is a block diagram of an embodiment of the present invention, FIG. 2 is an explanatory diagram of the operation of FIG. 1, FIG. 3 is a block diagram of a conventional example, and FIG. 4 is an explanatory diagram of the operation of FIG. 3. In the figure, 1 is a stuff control unit, 5 is a control unit, 6 is a duplex memory,

Claims (1)

[Claims] A TDMA satellite communication device includes: a stuffing control unit (1) that synchronizes N sequences of asynchronous PCM signals; an output of the stuffing control unit is written to a first memory; A duplex memory unit (6) that reads the output of the stuff control unit written in the memory, and an output selection switching unit (7) that multiplexes and outputs the PCM signal read from the duplex memory unit. and a control section (5) for controlling operations of the stuff control section, the duplex memory section, and the output selection switching section.