JPH11239112A - Multiplexed signal separator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multiplexed signal separator which performs separation and speed conversion on multiplexed digital signals by utilizing the bit configuration of a line memory and has a simplified circuit configuration. SOLUTION: A multiple signal separating circuit 30 is constituted in such a circuit configuration that, when a line memory delay circuit 31 in the preceding stage separates multiplexed digital signals, the separated and delayed digital signals in time slots #1-#4 are fed back and collectively and simultaneously written in a line memory speed converting circuit 32 in the succeeding stage and the circuit 32 can collectively and simultaneously output the low speed-side separated outputs #1-#4 through speed conversion. Therefore, the circuit 30 can perform separation/speed conversion on (n) pieces of multiplexed digital signals with a smaller number of parts.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a multiplexed signal separation apparatus equipped with a speed conversion device such as a line memory for separating a plurality of multiplexed digital signals and performing speed conversion accompanying the separation.

[0002]

2. Description of the Related Art Recently, as data communication speeds up and capacity increases, as a data transmission method for transmitting data at a high speed and a large capacity, for example, a plurality of data are digitized and multiplexed in time and transmitted. A time division multiplex transmission system is used. In this time-division multiplexing transmission system, a transmitting communication device temporally multiplexes a plurality of different data, converts the data into a high-speed digital signal, and transmits it. The receiving communication device separates the multiplexed digital signal. Then restore the original data.

[0003] Temporal multiplexing means that a plurality of different digital signals (data) are rearranged by a high-speed clock signal while being slightly shifted in time and multiplexed into a series of digital signals. Is the reverse of multiplexing, which is to extract a series of digital signals at timing shifted in time and separate them into a plurality of original different digital signals.

[0004] The receiving-side communication device for performing the separation is connected to the transmitting-side communication device via a communication line or wirelessly. Side is the low speed side. That is, since bit information is assigned to the high-speed side and low-speed side digital signals at different intervals within the same frame time, when separating the multiplexed digital signal in the receiving communication device, A speed conversion circuit for converting the speed difference between the frame timings on the high-speed side and the low-speed side is required.

FIG. 3 shows a conventional example of this speed conversion circuit using a dual port RAM (hereinafter referred to as DPRAM). In the speed conversion circuit shown in FIG.
The address counter 2 for generating a write address for writing the separated digital signal at high speed is disposed as "sideA" on the left side of the figure in FIG.
The right side in the figure of AM1 is the low-speed side, and an address counter 3 for generating a read address for reading out the separated digital signal at a low speed is disposed as "sideB".

[0006] The DPRAM 1 writes the separated digital signal DataIn0 at a high speed to the write address generated from the address counter 2 at the write timing of the write enable control signals WEL and WER input from a control circuit (not shown). , Read enable control signals OEL, O
At the read timing of ER, the digital signal DataOut0 is read from the read address generated by the address counter 3.
Is read at low speed.

As a conventional example of a speed conversion circuit, an FIF
FIG. 4 shows an example in which an O (First In First Out) memory 11 is used. In the speed conversion circuit shown in FIG. 4, in the FIFO memory 11, the controller 12 instructs the write pointer 13 to indicate the write area at the write timing of the write enable control signal WE input from the control circuit (not shown).
The separated digital signal DataIn0 is written into the memory area 15 at a high speed, and at the read timing of the read enable control signal OE, the controller 12 instructs the read pointer 14 on the read area, and reads the digital signal DataOut from the read area at a low speed.

FIG. 5 shows a conventional example of a speed conversion circuit using line memory speed conversion circuits 21 to 24.
Shown in In the speed conversion circuit shown in FIG. 5, the line memory speed conversion circuits 21 to 24 operate at the timing of the timing chart shown in FIG. In FIG. 5, the separated digital signals (see FIG. 6A) input to the line memory speed conversion circuits 21 to 24 are high-speed write enable control signals # 1 to # 4 (FIG. 6B). To (e))
Is written to each line memory in each line memory speed conversion circuit 21 to 24 at the write timing, and then read from each line memory in each line memory speed conversion circuit 21 to 24 at a low-speed read timing. Thus, four low-speed side separated outputs # 1 to # 4 (see FIGS. 6F to 6I) are output.

[0009]

However, each of the conventional speed conversion circuits shown in FIGS. 3 to 5 has the following problems. First, in the case of the speed conversion circuit using the DPRAM 1 shown in FIG.
One DPRAM 1 can perform only the speed conversion of one separated digital signal, and when n separation circuits are configured, n DPRAMs are required, thus increasing the circuit scale. was there. Further, in practice, a double buffer configuration requiring two DPRAMs for each digital signal is often used so that the bit information in the frame period can be speed-converted without error, and the circuit scale is further increased. Further, each DPRAM needs an address control signal, and there is a problem that the circuit configuration is complicated by wiring and the like for this purpose.

In the case of the speed conversion circuit using the FIFO memory 11 shown in FIG. 4, the speed of one separated digital signal in one FIFO memory 11 is the same as in the case of the speed conversion circuit of FIG. Only conversion can be performed,
When n separation circuits are configured, n FIFO memories are required, so that there is a problem that the circuit scale becomes large. Also, as in the case of the DPRAM, a double buffer configuration is often used, and the circuit scale is further increased.

Further, in the case of the speed conversion circuit using the line memory speed conversion circuits 21 to 24 shown in FIG. 5, each line memory corresponding to the delay circuit uses only one bit by a digital signal. In addition, since the remaining 7 bits of the line memory that processes data in the commonly used 8-bit configuration are not used, there is a problem that the utilization efficiency of the line memory is reduced. Also, the write enable control signals # 1 to # 4 having different timing
This necessity complicates the circuit configuration. Furthermore, n
In the case of constructing the separation circuits for the number of lines, since n line memories and the write enable control signals for the number of n lines are required, there is also a problem that the circuit scale becomes large.

An object of the present invention has been made in view of the above-mentioned problem, and utilizes a bit configuration of a line memory.
It is an object of the present invention to provide a multiplexed signal demultiplexing apparatus that simplifies a circuit configuration for separating a multiplexed digital signal and performing speed conversion.

[0013]

According to the first aspect of the present invention,
In a multiplex signal separating apparatus for converting an upstream signal input speed into a downstream signal output speed by using a line memory when separating a multiplexed digital signal, Separation delay means for separating the input multiplexed digital signal by the bit configuration of the first line memory, returning each separated digital signal to the input side of the first line memory, delaying and outputting the separated digital signal, Speed converting means for inputting each of the separated digital signals output from the separating and delaying means to a second line memory, converting the digital signal into the downstream signal output speed, and outputting the converted signal. .

Therefore, it is possible to separate / speed convert n multiplexed digital signals with a small number of component parts, to reduce the circuit size of the multiplexed signal separating apparatus, to reduce the cost, and to realize the separation / speed. Reliability at the time of conversion can be improved.

In this case, the above object is achieved, for example, by claim 2
In the multiplexed signal separating apparatus according to claim 1, the separating and delaying means comprises only the first line memory provided with a feedback line for returning each of the separated digital signals to an input side. And separating the multiplexed digital signal, and delay output of each of the separated digital signals,
It is effective to control by the signal feedback operation in the first line memory.

Accordingly, a separation circuit for separating n multiplexed digital signals can be easily configured with a small number of components, the circuit scale can be further reduced, and the n multiplexed digital signals can be reduced. They can be separated at once and the bit configuration of the line memory can be used effectively.

Further, according to the invention described in claim 3,
The multiplex signal separation device according to claim 1 or 2,
The speed conversion means inputs each of the separated digital signals output from the separation delay means to each bit line of the second line memory, thereby converting each of the separated digital signals to the signal output speed on the downstream side. It is effective to convert and output.

Therefore, it is possible to easily configure a speed conversion circuit for speed-converting n separated digital signals with a small number of components, to further reduce the circuit scale, and to convert the n separated digital signals. Speed conversion can be performed collectively, and the bit configuration of the line memory can be used effectively.

Also, as in the invention described in claim 4,
4. The multiplex signal separation device according to claim 1, wherein a timing control signal for controlling each operation timing of the separation delay operation in the separation delay unit and the speed conversion operation in the speed conversion unit is controlled by a common control line. It is effective to input to the separation delay means and the speed conversion means.

Therefore, it is possible to simplify the configuration of the control line connected to the separation delay means and the speed conversion means, further reduce the circuit scale, and further reduce the cost of the multiplex signal separation device.

[0021]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIGS. 1 and 2 are diagrams showing an embodiment of a multiplexed signal separation circuit to which the present invention is applied.
First, the configuration will be described. FIG. 1 is a block diagram showing a main circuit configuration of a multiplexed signal separation circuit 30 in the present embodiment. In FIG. 1, a multiplexed signal separation circuit 30
It is composed of a line memory delay circuit 31 and a line memory speed conversion circuit 32. The left side in the figure is the high-speed side, and the right side in the figure is the low-speed side.

The line memory delay circuit 31 inputs the multiplexed digital signal input from the high-speed side to the input line corresponding to the first bit of the built-in line memory, and starts from the first bit of the line memory. The delay output # 1 output is fed back to the input line corresponding to the second bit of the line memory, and is also output to the first bit input line of the line memory incorporated in the line memory speed conversion circuit 32. .

The line memory delay circuit 31 feeds back the delay output # 2 output from the second bit of the built-in line memory to the input line corresponding to the third bit of the line memory, and The signal is also output to the second bit input line of the line memory built in the speed conversion circuit 32. Further, the line memory delay circuit 3
Reference numeral 1 designates a feedback output of the delay output # 3 output from the third bit of the built-in line memory to an input line corresponding to the fourth bit of the line memory, and a line built in the line memory speed conversion circuit 32. It is also output to the third bit input line of the memory. Then, the line memory delay circuit 31 outputs the delay output # 4 output from the fourth bit of the built-in line memory to the fourth bit input line of the line memory built in the line memory speed conversion circuit 32.

The output timing (feedback input timing) of the delay outputs # 1 to # 4 to each input line in the line memory delay circuit 31 is such that a write enable control signal input from a control circuit (not shown) is active. The operation timing of the write enable control signal is set based on the clock timing of a high-speed clock signal input from a clock circuit (not shown).

Therefore, the line memory delay circuit 31 sets the time slots # 1 to # 4 multiplexed with the digital signal input to the first bit of the built-in line memory based on the high-speed clock signal. On the basis of the operation timing at which the write enable control signal becomes active, each of the time slots # 1 to # 4 is separated and delayed, and four delays corresponding to each of the time slots # 1 to # 4 are separated. The outputs # 1 to # 4 are collectively output to the own feedback input line and each input line of the line memory speed conversion circuit 32.

The line memory speed conversion circuit 32 includes delay outputs # 1 to # 1 input from the line memory delay circuit 31.
4 is collectively written into an internal line memory according to the operation timing of a write enable control signal input from a control circuit (not shown), and the clock timing of a low-speed clock signal input from a clock circuit (not shown) Based on the operation timing of the read enable control signal set by the control circuit based on the timing, the delay outputs # 1 to # 4 written in the internal line memory are collectively output as low-speed side separated outputs # 1 to # 4.

Next, the operation of this embodiment will be described. The operation of each circuit section in the multiplexed signal separation circuit 30 of FIG. 1 will be described with reference to the timing chart shown in FIG.

In FIG. 1, a digital signal (see FIG. 2A) in which time slots # 1 to # 4 input from the high-speed side are multiplexed is transmitted to one of the line memories built in the line memory delay circuit 31. It is input to the input line of the bit. In the line memory delay circuit 31, the write enable for the time width of the time slot # 1 is set to active ("Hi") in the write enable control signal shown in FIG. As a result, the time slot # 1 of the input multiplexed digital signal is written to the first bit of the line memory.

At this time, the time slots # 2, # 3, and # 4 that have been delayed and input in advance are stored in the internal line memory 2
Since the write enable signal is present in each of the input lines of the third, fourth, and fourth bits, the write enable is set to be active for the time width of time slot # 1 in FIG.
As shown in (d) to (g), the delay outputs # 1 to # 4 delayed by the built-in line memory simultaneously collectively output the first, second, third, and fourth bits of the built-in line memory. Written.

The delay period of each of the time slots # 1 to # 4 written in the line memory in the line memory delay circuit 31 has no delay in the time slot # 1 and one write enable time in the time slot # 2. Time slot # 3 has a delay of 2 write enable times, and time slot # 3 has a delay of 3 write enable times. 4 is separated into four digital signals. That is, the delay outputs # 1 to # 4 output from the line memory delay circuit 31 correspond to the time slots # 1 to # 4 separated from the multiplexed digital signal.

The delay outputs # 1 to # 4 written to the line memories in the line memory delay circuit 31 are incorporated in the line memory speed conversion circuit 32 at the timing when the next write enable control signal becomes active. The first, second, third, and fourth bits of the line memory are collectively output and written. Next, in the line memory speed conversion circuit 32, a low-speed clock signal (FIG.
(H)), the delay outputs # 1 to # 1 written in the internal line memory by the operation timing at which the read enable control signal (see FIG. 2 (i)) set by the control circuit based on the clock timing becomes active. # 4 are collectively read and simultaneously output as low-speed side separated outputs # 1 to # 4 as shown in FIGS. 2 (j) to 2 (m).

As described above, in the multiplexed signal separation circuit 30 in the present embodiment, the line memory delay circuit 3
1, when the multiplexed digital signal is separated, the separated and delayed digital signals of the time slots # 1 to # 4 are fed back to the line memory speed conversion circuit 32 at the subsequent stage.
The delay outputs # 1 to # 4 of the main line are written simultaneously and collectively at the same time, and the line memory speed conversion circuit 32 in the subsequent stage collectively and simultaneously outputs the low speed side separated outputs # 1 to # by speed conversion.
4 is a circuit configuration capable of outputting the output signal of FIG.
Can be separated / speed-converted for n multiplexed digital signals with a smaller number of parts compared to the circuit structure of each speed conversion circuit shown in FIG.

In the multiplexed signal separation circuit 30, the line input / output of each line memory incorporated in the line memory delay circuit 31 and the line memory speed conversion circuit 32 can be used for 8 bits, which is the memory configuration. Therefore, the speed conversion for eight lines can be performed simultaneously, and the use efficiency of the line memory can be improved.

Further, in the multiplexed signal separating circuit 30,
The number of lines for transmitting the write enable control signal for controlling the timing of cutting out the time slot from the multiplexed digital signal can be reduced from the conventional four to one, and four multiplexing / demultiplexing for multiplexing / demultiplexing four digital signals. In the circuit, when the conventional speed conversion circuit is used, a total of 16 line memories are required. However, when the speed conversion circuit of the present embodiment is used, a total of 4 line memories are required. Become. Therefore, the circuit configuration of the multiplexing / demultiplexing circuit can be simplified, the circuit scale can be significantly reduced, and the cost can be reduced.

In the above embodiment, the example of the multiplexed signal separating circuit 30 for separating the multiplexed digital signal into four is shown, but the number of time slots set in the digital signal to be multiplexed / separated is set. Of course, it is easy to appropriately change the circuit configuration of the multiplexed signal separation circuit 30 in accordance with the above.

[0036]

According to the multiplex signal demultiplexer of the first aspect of the present invention, n multiplexed digital signals can be separated / speed-converted with a small number of components, and the circuit scale of the multiplex signal demultiplexer can be reduced. The cost can be reduced by reducing the size, and the reliability at the time of separation / speed conversion can be improved.

According to the multiplexed signal demultiplexing device of the second aspect, a demultiplexing circuit for demultiplexing n multiplexed digital signals with a small number of components can be easily configured, and the circuit scale can be further reduced. Multiplexed digital signals for n lines can be collectively separated, and the bit configuration of the line memory can be effectively used.

According to the multiplex signal demultiplexer of the third aspect of the present invention, it is possible to easily configure a speed conversion circuit for converting the speed of n separated digital signals with a small number of components, thereby further reducing the circuit scale. The speed conversion of the n separated digital signals can be performed at a time, and the bit configuration of the line memory can be effectively used.

According to the multiplex signal separating apparatus of the fourth aspect, the configuration of the control line connected to the separation delay means and the speed conversion means can be simplified, and the circuit scale can be further reduced to achieve the multiplexed signal. The cost of the separation device can be further reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main configuration of a multiplexed signal separation circuit 30 according to an embodiment of the present invention.

FIG. 2 is a timing chart showing an operation of a signal in each unit in the multiplexed signal separation circuit 30 of FIG.

FIG. 3 is a block diagram showing a main circuit configuration of a speed conversion circuit using a conventional DPRAM 1;

FIG. 4 is a block diagram illustrating a main circuit configuration of a speed conversion circuit using a conventional FIFO memory 11;

FIG. 5 is a block diagram showing a main circuit configuration of a speed conversion circuit using conventional line memories 21 to 24;

6 is a timing chart showing an operation of a signal in each unit in the speed conversion circuit of FIG. 5;

[Explanation of symbols]

 Reference Signs List 30 Multiplex signal separation circuit 31 Line memory delay circuit 32 Line memory speed conversion circuit

Claims (4)

[Claims] 1. A multiplex signal separating apparatus for converting an upstream signal input speed into a downstream signal output speed using a line memory when separating a multiplexed digital signal, comprising: The multiplexed digital signal input to the first line memory is separated by the bit configuration of the first line memory, and each separated digital signal is fed back to the input side of the first line memory to be delayed and output. Separation delay means, and speed conversion means for inputting each separated digital signal output from the separation delay means to a second line memory, converting the separated digital signal into the signal output speed on the downstream side, and outputting the converted signal. A multiplex signal demultiplexer characterized by the above-mentioned. 2. The method according to claim 1, wherein the separation delay means includes a feedback line for feeding back each of the separated digital signals to an input side.
Wherein the separation of the multiplexed digital signal and the delayed output of each of the separated digital signals are controlled by a signal feedback operation in the first line memory. Item 2. The multiplex signal separation device according to Item 1. 3. The speed conversion means inputs the separated digital signals output from the separation delay means to each bit line of the second line memory, thereby converting the separated digital signals to the downstream side. 3. The multiplexed signal demultiplexing apparatus according to claim 1, wherein the multiplexed signal is output after being converted into a signal output speed. 4. A separation delay operation in said separation delay means,
And a timing control signal for controlling each operation timing of the speed conversion operation in the speed conversion unit is input to the separation delay unit and the speed conversion unit by a common control line. 4. The multiplex signal separation device according to 2 or 3.