JP3065250B2 - Multiplexer circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time-division multiplexing multiplexer circuit for converting low-speed parallel data of a plurality of channels into serial data of a high bit rate, and more particularly, to input data of each channel in an optical communication system or the like. The present invention relates to a multiplexer circuit capable of realizing high-speed operation and low power consumption when multiplexing and outputting in byte units.

[0002]

2. Description of the Related Art Hitherto, in this type of multiplexer circuit, a bit multiplexing system having a relatively simple circuit configuration has been used from the viewpoint of high-speed operation.

Here, the operation timing of a conventional bit multiplexing multiplexer circuit will be described with reference to FIG.

In the illustrated system, eight data D10, D20,..., And D80 transmitted from eight channels CH1 to CH8 are converted into serial data having an eight-fold bit rate. Output to one channel. Therefore, as shown in the figure, the data D10, D11,..., D17 sequentially input at low speed from the channel CH1 have the simultaneous input data of the channels CH2 to CH8 inserted between them, and the high-speed data on the output side is used. Appears at every eighth data position.

[0005] This means that SONET (Synchronous Optical Network) in which input data has information in byte units.
: Optical Synchronous Communication Network)
Since the circuit on the data receiving side obtains information by reorganizing the data of each channel in byte units, there is a problem that the circuit becomes complicated and power consumption increases.

In order to solve this problem, recently, a byte multiplexing type multiplexer circuit as shown in FIG. 4 has been proposed.

[0007] The system shown in FIG.
Byte input data D1 input from each of H8
0 to D17,..., And D80 to D87 are converted into serial data having an eight-fold bit rate and output to one channel. Therefore, as shown in the figure, eight data to be input to each of the eight channels at a low speed are first data D10 to D17 of channel CH1,
Next, data D20 to D27 of channel CH2 follow.
The data D80 to D87 of the last channel CH8 appear serially as high-speed data on the output side in the order of channel numbers with the same time width as the input time width.

As a result, on the receiving side in a system having information in byte units, the object of simplifying the circuit for frame synchronization and reducing power consumption is achieved.

This type of technology is disclosed in, for example, Japanese Patent Application Laid-Open No. 2-246.
No. 536.

Next, the basic configuration of this circuit will be described with reference to FIG.

The circuit shown in FIG. 3 includes shift registers R101 to R108 for inputting channel CH1 and channel C1.
Shift register R801 to R808 for H8 input 6
Four input registers and the shift register R10
It is composed of 64 registers for serial output of shift registers R901 to R964 corresponding to 1 to shift register R808, respectively.

First, input data is simultaneously taken into eight registers from the shift register R101 of the channel CH1 to the shift register R801 of the channel CH8.
Similarly, data is taken from the eighth shift register R108 to the shift register R808. After the data is fetched and stored in all of the 64 input registers, the stored data is transferred to the output shift register R90.
1 to the shift register R964 are collectively loaded.

Next, these loaded data are sequentially read out in synchronization with a high-speed clock having a speed eight times the low-speed clock, and as shown in FIG. 4, data of each channel is multiplexed in byte units. A serialized output is obtained.

[0014]

In the conventional multiplexer circuit described above, eight parallel data of eight channels are stored in all 64 input registers and then 64 output data corresponding to the input registers are stored. And then read out in synchronism with the high-speed clock.

In this configuration, there is a problem that it is difficult to adjust the timing at each time when data is loaded and read by the high-speed clock, and high-speed operation is difficult. Further, the output register for loading data has 64 registers.
Since the power consumption is required for all data, the power consumption increases in proportion to the increase of the clock frequency.
There is also a problem that it is difficult to reduce the power consumption when using a mplementory metal oxide semiconductor (circuit) technology.

An object of the present invention is to solve the above problems,
An object of the present invention is to provide a multiplexer circuit capable of achieving high-speed operation and low power consumption when multiplexing and outputting input data of each channel in byte units.

[0017]

Multiplexer circuit according to the invention To achieve the above object, according to, N converts the parallel data of N channels to the serial data of N times the bit rate: In 1 multiplexer circuit, et al. Provided to each of the N-channel
Data in the n-th channel according to the low-speed clock.
N input / output and (n-1) inputs that sequentially store
Constituting the shift register by the use, [N + (n-
1) ] registers and the N inputs / outputs for each channel
Following data shared registers the N of the next channel
Wherein each channel on the basis of the select signal N number of input-output for sequentially selecting the data of number of the input-output register
Of N retrieve the data from the register of N: and one of the selectors, N outputs multiplexes the output of the N selectors as serial data to the one channel by the high speed clock: and a first multiplexer.

In the above configuration, N ² registers are used for input and output, and at least [N × (N−1) / 2] registers less than N ² are used for subsequent input. With the [N × (N−1) / 2] registers, the next input data of each channel can be written at the timing next to the serial output of N data of one channel.

Further, another multiplexer circuit according to the present invention is provided for each of the N channels, and is provided for the n-th channel.
In the channel, N input / outputs and (n-1) inputs for sequentially storing data according to a low-speed clock are used.
Divide the [ N + (n-1) ] registers constituting the shift register and the N channels into 2 ^k (k is a positive integer) system
The select that is provided in each of N / 2 ^k Ji Yaneru, following the data of the N input-output register of one channel sequentially selecting data of the N input-output register of the next channel N [N / 2 ^k ]: 1 selectors for sequentially taking out data from the N input / output registers of each channel based on signals, and a total of 2 ^k selectors
Of the N lines [N / 2 ^k]: 1 and N OR circuit for logical Washo sense the output of the selector Taso respectively, the output of the N logical OR circuit by the high-speed clock An N: 1 multiplexer that multiplexes and outputs serial data to one channel is provided.

In this configuration, in addition to the above operation, the layout can be minimized by dividing the registers and symmetrically arranging the registers.

[0021]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a functional block diagram showing an embodiment of the present invention. The multiplexer circuit shown in FIG. 1 is for the case of N = 8. The selectors SEL1 to SEL8, the timing generation circuit 9, the multiplexer 10, and the registers R11 to R18 for the input side channel CH1, and the registers R21 to R21 for the channel CH2. It is assumed that R29, similarly, registers from channel CH3 to channel CH7, and channel CH8 include registers R81 to R815. The number of registers for each channel is
“Channel number−1 + N”, for example, channel C
In H8, it is (8-1 + 8 =) 15.

The difference from the prior art is that registers R29 and R3 are used as input registers instead of 64 output registers.
9, R310 to R815 (7 × 8/2 =), and eight selectors SEL1 to SEL8 are provided.

The selector SEL1 is connected to each of the channels CH1 to CH1.
Register R11 for storing first data in each of CH8
~R81 shall incorporate Thus the select signal from the timing generating circuit 9 respectively. The selector SEL2 is
The registers R12 to R82 for storing the second data in the respective channels CH1 to CH8 are taken in according to the select signal of the timing generation circuit 9. Similarly, the selector SELn controls each of the channels CH1 to CH8.
Registers R1n to R8 each storing n-th data
n are taken in according to the select signal of the timing generation circuit 9.

The timing generation circuit 9 includes a select signal,
It is assumed that a low-speed clock for writing and a high-speed clock for reading having a speed eight times the low-speed clock are output. The select signal is supplied to the selectors SEL1 to SEL8.
In response to this, the selection instruction from channel CH1 to channel CH8 is sequentially repeated according to the read time. The low-speed clock instructs writing to all the registers R11 to R815. The high-speed clock is output to the multiplexer 10 and controls the serial output of input data.

The multiplexer 10 includes a selector SEL1
To SEL8 are output serially in synchronization with the high-speed clock received from the timing generation circuit 9.

Registers R11 to R815 are shift registers for sequentially writing input data in each channel in synchronization with the low-speed clock received from the timing generation circuit 9. As described above, the number of registers of each channel is set to the channel CH1.
In the following channel CHn, CH [n−
1] is added to the number of registers. Thus, N:
One multiplexer circuit requires N ² registers R for N data for N input channels and at least [N × (N−1) / 2] registers R.

Next, the operation function will be described with reference to FIG.

First, in each input channel CH, the input data is written from the last numbered register R in synchronization with the low-speed clock output from the timing generation circuit 9, and is sequentially shifted to the lower numbered register. Therefore, the input data of each channel is stored in the register R in the channel CH1.
18, the data is written to the register R29 in the channel CH2, and similarly to the register R815 in the channel CH8. That is, each time the channel number is incremented by one, it is written to the register of the number one behind.

When data is written to the register R11, the register R11 of the channel CH1 is set based on the selector signal.
The eight data written to R18 are the selector SEL.
1 through SEL8, and are serially output from the multiplexer 10 in synchronism with the eight times high-speed clock during one low-speed clock.

At this time, the eight data at the same timing are stored in the registers R22 to R29 in the channel CH2, and similarly in the channel CHn.
nn to the register Rn [n + 7], and in the channel CH8, from the register R88 to the register R815.

The next input data is also written into the register R18 in the channel CH1, the register R29 in the channel CH2, and similarly to the register R815 in the channel CH8. As a result, in the channel CH2, eight data at the same timing as that taken out from the channel CH1 at the previous timing are shifted to the registers R21 to R28, and are taken in at the next timing via the selectors SEL1 to SEL8, and are read from the multiplexer 10 at the low speed clock. 1
It is serially output in synchronism with the eight times high-speed clock during each time.

As described above, when eight data are taken out from one channel, the next data is input and written into the register, and when the accumulated data is shifted to the next register, the next numbered channel is used. Eight data at the same timing as that taken out from the previous channel are accumulated in eight registers connected to the eight selectors, taken in at the next timing via the selectors SEL1 to SEL8, and output from the multiplexer 10 during one low-speed clock. To 8
Serial output is performed in synchronization with the double high-speed clock.

As described above, since data in byte units of each channel is selected and then multiplexed by the 8: 1 multiplexer, switching timing design is easy and high-speed operation is possible.

Next, a multiplexer circuit from another viewpoint will be described with reference to FIG. The multiplexer circuit shown in FIG. 2 is for the case of “N = 8”, and instead of the 8: 1 selectors SEL1 to SEL8 in FIG. 1, 4: 1 selectors SEL1A to SEL8A, SEL1B are used.
To SEL8B and a new OR circuit OR1C to OR
8C. The other components have the same functions as in FIG.

As shown, the selector SEL1A
Is a register R11 for each of the channels CH1 to CH4.
To R41 to select one, and OR circuit O
Output to R1C. The selector SEL2A is
Registers R12 to R for each of channels CH1 to CH4
42 connected to each other to select one and an OR circuit OR2
Output to C. Hereinafter, similarly, the selector SE
Until L8A, the selector SELnA is connected to the channels CH1
It is assumed that the registers R1n to R4n of each CH4 are connected to each other to select one and output it to the OR circuit ORnC.

On the other hand, the selector SEL1B
Assume that the registers R51 to R81 of H5 to CH8 are connected to each other to select one and output it to the OR circuit OR1C. Hereinafter, similarly, up to the selector SEL8B, the selector SELnB connects registers R5n to R8n of the channels CH5 to CH8, selects one, and outputs the selected one to the OR circuit ORnC.

The OR circuit OR1c is connected to the selector SEL1.
The outputs of A and SEL1B are connected to the multiplexer 10 by wired OR. Similarly, up to the OR circuit OR8C, the OR circuit ORnC selects the selector SE
The outputs of LnA and SELnB are connected to the multiplexer 10 by wired OR.

In this circuit, 16 4: 1 selectors SEL1A to SEL8A and SEL1B to SEL8B select data of a desired channel in byte units by a select signal of the timing generation circuit 9, and each of the OR circuits OR1C to The signal is output to the multiplexer 10 via the OR8C. The eight data fetched via the OR circuits OR1C to OR8C are serially output from the multiplexer 10 in synchronism with the eight times high-speed clock during one low-speed clock.

The operations of the register and the selector are the same as those described above with reference to FIG.

In this configuration, registers are divided into two systems for every four channels, and data of a desired channel is selected in units of bytes by taking a logical OR of 4: 1 selector outputs, so that the data is integrated on a semiconductor chip. In this case, since the registers can be symmetrically arranged on both sides of the 8: 1 multiplexer for bit-multiplexing, the maximum wiring length can be minimized.

In the above description, the two systems are divided into young and old channel numbers, but other division methods may be used. Further, it is apparent that the same effect can be obtained by dividing the two systems into four systems.

In the block diagram referred to in the above description, the circuit configuration is clear, and the positions of the functional blocks are irrelevant to the arrangement on the semiconductor chip.

[0044]

As described above, according to the present invention, N
A register for shared into N total N ² pieces of writing and reading for sequentially storing accordance slow clock input data channels, respectively, the N taken out from these registers corresponding N data sequentially selects and each channel A selector, an N: 1 multiplexer that outputs the output of the selector as serial data to one channel by a high-speed clock, and one to [N-1] pieces for writing the next data corresponding to each channel. N × (N−
1) / 2] registers, and a multiplexer circuit which collectively multiplexes and outputs data of the same channel is obtained.

According to this configuration, the circuit that operates in synchronization with the high-speed clock is limited to an N: 1 multiplexer that performs bit multiplexing because the switching timing is easy to design and high-speed operation is possible. Even when a CMOS circuit technology whose power consumption increases in proportion to the increase in the power consumption is used, the effect that the operation can be performed with lower power consumption can be obtained.

When the registers are divided into a plurality of systems and the output of the selector is wired-ORed to select data of a desired channel in byte units, the registers are arranged symmetrically on both sides of the multiplexer when integrated on a semiconductor chip. Therefore, it is possible to obtain an effect that the maximum wiring length becomes extremely small and a high-density layout design becomes possible.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing another embodiment of the present invention.

FIG. 3 is a timing chart illustrating an operation by a bit multiplexing method.

FIG. 4 is a timing chart illustrating an operation according to a byte multiplexing method.

FIG. 5 is a circuit configuration diagram showing an example of the related art.

[Explanation of symbols]

1, 1A, 1B, 2, 2A, 2B, 8, 8A, 8B
Selector (SEL) 1C, 2C, 8C OR circuit (OR) 9 Timing generation circuit 10 Multiplexer 11-18, 81-815 Register (R)

Continuation of the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H04J 3/00 H03K 17/00

Claims (2)

(57) [Claims] 1. A converts parallel data of N channels to the serial data of N times the bit rate N: In 1 multiplexer circuit, provided in each of the N-channel
Data in the n-th channel according to the low-speed clock.
N number of input-output for sequentially storing the data and (n-1) pieces of input
A shift register is composed of [ N + (n−
1 )] registers and the N inputs / outputs for each channel
Following data shared registers the N of the next channel
Wherein each channel on the basis of the select signal N number of input-output for sequentially selecting the data of number of the input-output register
Of N retrieve the data from the register of N: characterized in that it comprises a first multiplexer: the first selector, N for outputting multiplexing the output of the N selectors as serial data to the one channel by high-speed clock Multiplexer circuit. 2. An N: 1 multiplexer circuit for converting N-channel parallel data into N-times serial data at a bit rate , provided for each of said N channels.
Data in the n-th channel according to the low-speed clock.
N number of input-output for sequentially storing the data and (n-1) pieces of input
A shift register is composed of [ N + (n−
1) ] registers and N channels are stored as 2 ^k (k is a positive integer)
Number) divided into lines, et al provided for each N / 2 ^k Chi Yaneru
Is one of the N input-output following the data of the shared register next channel the N input-output Les <br/> each channel based on the select signal sequentially selects data register of the channel the N successively taking out <br/> data from input-output register of N [N / 2 ^k]: the first selector, the N [N / 2 ^k] total 2 ^k lines: 1 and N OR circuit for logical Washo sense the output of the selector <br/> click Taso respectively, multiplexing the output of the N logical OR circuit as serial data to the one channel by high-speed clock And a N: 1 multiplexer for converting and outputting the data.