JP2548709B2 - Multiple frame aligner - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a multiple frame aligner for aligning received frames of a plurality of lines into a fixed frame.

[Prior Art] A circuit for converting a phase of a received frame into a frame phase unique to a receiving station for a line that constitutes one frame with M bits (M is a natural number) is called a frame aligner. The one that performs the same processing as is called a multi-frame aligner. That is, when the received frame phase is independent as shown in FIG. 4 (a), this multiplex frame aligner aligns the frame phases of a plurality of lines to provide a constant frame phase as shown in FIG. 4 (k). Can be output with.

FIG. 3 is a block diagram showing a conventional multiplex frame aligner, and the number of lines to be multiplexed is n (n is a natural number). In FIG. 3, reference numeral 30 is a selector for multiplexing the data from lines 1 to n applied to the input terminals 11, 12, ..., 1n, and 51, 52, ..., 5n are input terminals 21, 22 ,,. ......, 2n
Is a M-ary counter that is reset by the respective signals of and is incremented by the clock T. Here, M is a natural number. 41 is M
A selector 90 for inputting and multiplexing the state outputs of the binary counters 51, 52, ..., 5n, 90 is an n-ary counter that is reset by a signal from the input terminal 80 and advances by the clock T3, 110 is
It is reset by the signal from the input terminal 100, and the n-ary counter 9
The M-adic counter 120 that advances by a carry pulse of 0 receives the output of the selector 41 at the write address terminal W, receives the state of the M-adic counter 110 at the read address terminal R, and receives the common write / read address terminal W. / R is a memory that receives the state of the n-ary counter 90 and uses the output of the selector 30 as write data and outputs the read data to the output terminal 130. The status output of the n-ary counter 90 is also input to the selectors 30 and 41.

Next, the operation will be described. FIG. 4 is a schematic waveform diagram for explaining the signal conversion procedure by the multiplex frame aligner when the number of lines n = 3. FIG. 4 (a) shows input data of each line, FIG. b) shows the output multiplexed by the selector 30 according to the n-ary counter 90, FIG. 4 (c) shows the frame pulse of the line B, and FIG. 4 (d) shows M.
The states of the binary counters 51, 52 and 53 are shown. FIG. 4 (e) is an output in which the selector 41 multiplexes the state outputs of the M-ary counters 51, 52, 53 according to the n-ary counter 90, and uses the data string shown in FIG. 4 (e) as the write address, and The state output of the n-ary counter 90 shown in FIG. 4 (h) is written in the memory 120 in a combination with the line address. On the other hand, reading from the memory 120 is performed by the M-ary counter 1 shown in FIG.
When the state output of 10 is used as a read address and the state output of the n-ary counter 90 shown in FIG. 4 (h) is used as a line address, the output terminal 130 outputs a frame as shown in FIG. 4 (k). The phase is output in synchronization with each line.
4 (g) shows a waveform diagram of the read frame pulse of the memory 120, and FIGS. 4 (i) and (j) show waveform diagrams of the clocks T and T3, respectively.

[Problems to be Solved by the Invention] Since the conventional multiplex frame aligner is configured as described above, it is necessary to provide the same number of counters as the number of lines, and the data of the selector that selects the output of these counters. Since the width needs to be log ₂ M or more, there is a problem that the hardware scale increases remarkably as the number of lines increases.

The present invention has been made in order to solve the above problems, and it is possible to obtain a multiple frame aligner in which it is not necessary to increase the counter with an increase in the number of lines and the selector has a data width of 1. With the goal.

[Means for Solving Problems] The multi-frame aligner according to the present invention has n (n
Is a natural number) and multiplexes the data of the line into a single line,
In a multiplex frame aligner that matches the order of the frame numbers of the respective lines, an n-ary number that counts a clock T3 that is generated in synchronization with a clock T that represents the line speed before multiplexing and that has a cycle of 1 / n of the clock T A counter, a first selector for selecting data of one line out of n pieces of data input in parallel according to the count value of the n-ary counter, and parallel input according to the count value of the n-ary counter. The second selector that selects the frame pulse of one line out of the frame pulses of the n lines to be reset, and is reset by the output of this second selector, and its phase is delayed from T3 in the same cycle as T3 above. And a first M-ary counter (where M is the number of data in one frame) that counts the clock T4 having a different phase and presets the state of the shift register described later at the T3 clock. The above T3 and T4 same period and the next period of the T3
The clock M2 generated in the phase between
Of the first M-ary counter and a second M-ary counter for counting carry pulses of the n-ary counter; A memory in which the output of the first selector is written with the output and the output of the n-ary counter as write addresses, and the data is read with the output of the second M-ary counter and the output of the n-ary counter as read addresses. With.

[Operation] In the multiplex frame aligner according to the present invention, the first counter as the write address counter sets the output of the shift register to the initial state, and the state after the count-up is written to the shift register again, so that the number of lines is equal. Realize multiple operations.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 30 is a first selector that multiplexes data from lines 1 to n applied to input terminals 11, 12, ..., 1n, and 31 is an output of the first selector 30 with a clock T1. The first latch 40 to be taken in, 40 is a second selector for multiplexing the frame pulse indicating the beginning of the data on the lines 1 to n applied to the input terminals 21, 22, ..., 2n, and 50 is a clock
An M-ary counter (first counter) that advances at T4, is reset by the output of the second selector 40, and advances at the speed after multiplexing, and 60 is a second counter that captures the state of the M-ary counter 50 at the clock T1. The latch 70 of the second latch 60 receives the output of the second latch 60, shifts at the clock T2, and outputs again to the initial value input terminal of the M-adic counter 50. The data width is log ₂ M or more and the length is the same as the number of lines n. Shift register. 90 is an n-ary counter (third counter) which is reset by the signal from the input terminal 80 and advances by the clock T3, and 110 is reset by the signal of the input terminal 100 and is a carry pulse of the n-ary counter 90. The M-ary counter (second counter), which advances in the frame phase peculiar to the receiving station and in the line speed before multiplexing, 120 receives the output of the second latch 60 at the write address terminal W, The M-ary counter 110 is connected to the read address terminal R.
The write / read common address terminal W / R receives the state of the n-ary counter 90, the output of the first latch 31 is used as write data, and the read data is output to the output terminal 130.

Here, T1, T2, T3 and T4 are shown in FIG. 2 (i), (k),
As shown in (g) and (f) respectively, clocks having the same cycle (cycle of 1 / n of the cycle of the clock T shown in FIG. 4 (i) showing the line speed before multiplexing) and having different phases from each other are used. is there. These clocks represent the line speed after multiplexing. The clocks having different phases are used because it is necessary to shift the operation timing. The phase of the clock T3 is synchronized with the phase of the clock T as shown in FIGS.

The state output of the n-ary counter 90 is also supplied to the first and second selectors 30 and 40. As a result, the n-ary counter 90 causes the first and second selectors 30, 40 and It functions as a counter that outputs a signal for imposing identification of a plurality of multiplexed lines on the write / read common address terminal W / R of the memory 120.

Next, the multiplex frame aligner of the present embodiment having the above configuration will be described with reference to FIG. 2 showing a time chart showing signals of main parts in FIG. The case of FIG. 2 shows the case where the number of lines n is 3,
2 (a) is the input data of each line, FIG. 2 (b) is the output multiplexed by the first selector 30, and FIG. 2 (c) is the second.
Input frame pulse multiplexed by the selector 40 of
FIG. 2 (d) shows the output of the first latch 31 which takes in the data string of FIG. 2 (b) at the clock T1 shown in FIG. 2 (i).

Now, in FIG. 2, when a frame pulse is input to the line B, the M-adic counter 50 is reset to the state "0", and the second latch 60 receives the clock shown in FIG. 2 (i). Write at T1 and apply the data string (write address data string) shown in FIG.
Write the data shown in FIG. In addition, M-base counter
The state of 50 is shown in FIG. 2 (e).

By the way, the data from the second latch 60 is simultaneously transferred to the shift register 70 having a length of 3 by the clock shown in FIG.
It is stored in T2, read out at the second clock of the clock T2 as shown in FIG. 2 (j), preset in the M-adic counter 50 at the clock T3 shown in FIG. The frame phase is reproduced and the M-ary counter 50 advances at the clock T4 shown in FIG. 2 (f) to generate the write address data of the memory 120 for the next data on the line B. In this way, the M-adic counter 50 becomes a shift register.
The output of 70 is set to the initial state, and the state after counting up is written in the shift register 70 through the second latch, whereby the multiplexing operation of the line portion is performed.

In addition, for the other lines A and C, similarly, the counter 50
Operates as a multiplex counter by temporarily storing the frame phase of each line in the shift register 70, and reading and presetting again.

On the other hand, the M-ary counter 110 writes each line A to the memory 120 in which the frame phase and the address are matched.
By reading the data of C, the data of each line having the same frame phase is read from the output terminal 130 of the memory 120.

In this way, the M-ary counter 50 as the first counter can be time-division-multiplexed and used by using the shift register. Therefore, even if the number of lines increases, it is not necessary to increase the number of counters. Therefore, even if the number of lines increases, the hardware scale does not increase.

In the above embodiment, the second latch 60 is provided in order to prevent the write address of the memory 120 from changing within the clock T1. However, when the memory 120 is only required to hold the write address during the time from clock T4 to T3, The second latch 60 can be omitted.

[Effects of the Invention] As described above, according to the present invention, by skillfully using the shift register, the line-corresponding frame counters can be used in a time-division multiplex manner, and even if the number of lines increases. There is an advantage that the scale of hardware is not increased and the effect of deleting parts is greater as the number of lines increases.

[Brief description of drawings]

FIG. 1 is a block diagram showing a multiple frame aligner according to an embodiment of the present invention, FIG. 2 is a schematic waveform diagram for explaining the operation of the present invention, and FIG. 3 shows a conventional multiple frame aligner. A block diagram and FIG. 4 are schematic waveform diagrams for explaining the operation of a conventional multiple frame aligner. In the figure, 11, 12, ..., 1n ... Data input terminals, 21,
22 to 2n frame pulse input terminal, 30 first selector, 31 first latch, 40 second selector, 50 M-ary counter (first counter), 60 ...... Second latch, 70 ...... Shift register, 80 …… Multiple phase designation input terminal, 90 …… n-ary counter (third counter), 100 …… Frame pulse input terminal, 110 …… M-ary Counter (second counter), 120 ... Memory, 130 ... Data output terminal. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (2)

(57) [Claims] 1. A multiplex frame aligner for multiplexing data of n (n is a natural number) lines into a single line and matching the frame number order of each line, and a clock representing the line speed before multiplexing. An n-ary counter that is generated in synchronization with T and counts a clock T3 having a cycle of 1 / n of the clock T. n input in parallel according to the count value of this n-ary counter
A first selector for selecting data of one line of the data, and n input in parallel according to the count value of the n-ary counter
A second selector for selecting a frame pulse of one line among the frame pulses of the plurality of lines, reset by the output of this second selector, and
The first M-ary counter (however, M) which counts the clock T4 whose phase is delayed from T3 in the same cycle as the above and presets the state of the shift register described later at the T3 clock
Is the number of data in one frame), and the parallel output of the first M-ary counter is parallelized by the clock T2 generated in the same cycle as T3 and in the phase between T4 and T3 in the next cycle. A shift register having n shift stages that are input and shifted; a second M-ary counter that counts carry pulses of the n-ary counter; an output of the first M-ary counter and an output of the n-ary counter. The output of the first selector is written as a write address, and the output of the second M-ary counter and n
A multi-frame aligner, comprising: a memory from which data is read by using the output of the binary counter as a read address. 2. A first latch is provided between the first selector and the memory, and the output of the first selector is the above-mentioned.
T1 generated in the same cycle as T3 and in the phase between T4 and T2
It is latched in the first latch by a clock and
Output to the memory, and a second latch is provided between the first M-ary counter and the shift register to output the output of the first M-ary counter to the T1.
This clock is latched in the second latch by the clock
The output of the second latch is input to the shift register at the T2 clock, and the output of the second latch is used as a write address of the memory.
A multi-frame aligner as described in paragraph.