WO1995010897A1 - A buffering method and a buffer - Google Patents

A buffering method and a buffer Download PDF

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Publication number
WO1995010897A1
WO1995010897A1 PCT/FI1994/000462 FI9400462W WO9510897A1 WO 1995010897 A1 WO1995010897 A1 WO 1995010897A1 FI 9400462 W FI9400462 W FI 9400462W WO 9510897 A1 WO9510897 A1 WO 9510897A1
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WO
WIPO (PCT)
Prior art keywords
data
buffer
bit
memory
synchronization
Prior art date
Application number
PCT/FI1994/000462
Other languages
French (fr)
Inventor
Toni Oksanen
Jari Patana
Esa Viitanen
Original Assignee
Nokia Telecommunications Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Telecommunications Oy filed Critical Nokia Telecommunications Oy
Priority to AU78153/94A priority Critical patent/AU7815394A/en
Priority to GB9607820A priority patent/GB2297464B/en
Priority to DE4497707A priority patent/DE4497707B4/en
Priority to DE4497707T priority patent/DE4497707T1/en
Publication of WO1995010897A1 publication Critical patent/WO1995010897A1/en

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/16Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04JMULTIPLEX COMMUNICATION
    • H04J3/00Time-division multiplex systems
    • H04J3/02Details
    • H04J3/06Synchronising arrangements
    • H04J3/062Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0626Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators

Definitions

  • CCITT (recommendation G.709) defines several different mapping modes (asynchronous, bit synchronous and byte synchronous) for a 2048 bit/s signal in the frame structure of the SDH system, depending on the type of the incoming 2048 kbit/s signal [i.e.
  • bits arrive for instance asynchronously, or is there, in addition to the clock signal, for instance byte synchronization data (indicating which 8 bits are included in the same byte), frame synchronization data or multiframe synchronization data included] .
  • Asynchronous, bit synchronous and byte synchronous signals are defined in CCITT recommendations G.703 and G.704.
  • the synchronization is passed through a buffer typically so that together with every data bit, a separate synchronization bit is transferred.
  • the object of the present invention is to pro ** **: de a solution which allows a combined bit and byte buf:....r to be implemented in the simplest possible manner.
  • This object is achieved with the method and the buffer of the invention, the method being characterized by what is described in the characterizing part of the appended claim 1, and the buffer being characterized by what is described in the characterizing part of the appended claim 2.
  • the idea of the invention is to implement the buffer in a certain length with respect to the frame and byte lengths of the data to be transferred and to utilize this length in passing through a synchronization signal by forming a memory location for the synchronization signal bit adjacent to only one data bit. This allows the synchronization signal to be passed in the simplest possible manner through the buffer correctly, i.e.
  • Figure 1A illustrates the principal features of the bit buffer of the invention
  • Figure IB illustrates the interdependence between the frame structure of the data coming into the buffer and the buffer
  • FIG. 2 shows a more detailed structural alternative of the bit buffer of the invention.
  • Figure 1 shows the principle of the elastic bit buffer of the invention in simplified form.
  • the core of the buffer consists of a buffer memory 13 which functions as a temporary data storage and with which is associated in a manner known per se (a) a write counter 11, which controls the writing into the buffer memory by giving write addresses to the write input of the buffer memory and (b) a read counter 12, which controls the reading from the buffer memory by giving read addresses to the read input of the buffer memory.
  • the write counter steps in synchronism with a write clock WR_CLK and the read counter in synchronism with a read clock RD_CLK.
  • the buffer memory consists of M pieces of one-bit data memory locations 14, which are numbered from zero to (M-l), and of one memory location 15 which is arranged for the synchronization bit and which is adjacent to one data memory location 14.
  • the buffer memory length M is connected with a frame 16 ( Figure IB) of an incoming signal in such a way that the frame length in bits corresponds to the multiple of the buffer memory length.
  • the buffer memory length M must be divisible by the byte length (which is typically eight).
  • the frame length F and the buffer memory length M correlate thus with each other in the following way:
  • the synchronization is passed through the buffer by writing a synchronization bit SB to said adjacent memory location 15.
  • the synchronization bit is written to the memory location adjacent to the data memory location in address zero, but the synchronization memory location can in principle be situated in any address 0...(M-1) (adjacent to the data memory location situated in said address).
  • FIG. 2 shows a more detailed embodiment of the buffer of the invention.
  • Data memory locations consist in this case of M pieces of D-flip-flops 21, to data inputs D of which is connected incoming data R_DATA.
  • the data memory locations are separated from each other by references M(0)...M(M-l) referring to their respective addresses.
  • the write clock signal WR_CLK is connected to the clock inputs of D-flip-flops 24 and 25 and to the clock inputs of the data memory locations 21.
  • a signal WR_EN enabling writing is connected to enable inputs EN of the write counter 22, of the D-flip-flop 25 and of a decoder 23.
  • the synchronization signal WR_S which is passed through the buffer, is connected to the synchronization input LD of the write counter and to the data input D of the D-flip-flop 25.
  • the pulse of the synchronization signal constitutes a synchronization bit, which appears in the output of the D-flip-flop 25 at the same time as the write counter output has the value zero.
  • the output Q of the write counter 22 is connected to the decoder 23, which codes from the counter value an enable signal for each data memory location, this signal enabling writing to said memory location if the enable signal coming to the decoder is active.
  • the enable signal acquired from the decoder output zero is connected to the enable input EN of a separate synchronization memory location 24 implemented by one D-flip-flop. In this case, the data memory location 21/M(0) and the synchronization memory location 24 are thus adjacent to each other in the address zero.
  • each data memory location 21 is connected to a corresponding input of a data multiplexer 26, i.e. the output of the memory location zero (M(0)) is connected to the input zero of the data multiplexer, the input of the memory location one (M(l)) is connected to the input one of the multiplexer, etc. , and the output of the data memory location (M(M-l)) in the address M-l is connected to the input (M-l) of the multiplexer.
  • the output Q of the synchronization memory location 24 is connected to the first data input (input zero) of the multiplexer 26.
  • a fixed value F zero, for instance
  • F zero, for instance
  • SEL selection input
  • a synchronization signal RD_S is thus acquired from the output of the multiplexer 27.
  • the write counter 22 steps in synchronism with the write clock signal R_CLK continuously from zero to value (M-l), thus counting incoming bits.
  • the data bits are written into the data memory locations 21 in succession in such a way that the first bit is written in the address zero, the second bit in the address one etc., and after M bits, the whole procedure is restarted by writing again in the address zero (from which the previous value has by then been read out).
  • the read counter steps in a similar manner in synchronism with the read clock signal RD_CLK.
  • the read counter has the value zero, the synchronization bit is selected to the output of the multiplexer 27, and with the other values of the counter, a predetermined fixed value F is selected to the output.
  • each data memory 0...(M-l) is selected one after another to the output of the data multiplexer 26, whereby a data signal passed through the buffer is acquired from the output of the data multiplexer (this signal being indicated by reference RD_DATA), and the synchronization signal RD_S passed through the buffer is acquired from the output of the multiplexer 27.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)

Abstract

The present invention relates to a method for carrying out buffering in a digital telecommunication system, wherein data is transferred in frames the length of which is F bits. According to the method, data is written into the buffer memory in synchronism with a write clock signal (WR-CLK), and data is read from the buffer memory in synchronism with a read clock signal (RD-CLK). In order to implement the combined bit and byte buffer in the simplest possible manner, the buffer memory is composed of M pieces of one-bit data memory locations (14; 21), the figure M being selected so that the frame length F is divisible by the figure M and the figure M is divisible by the byte length, and that the synchronization data passed through the buffer is stored in a one-bit synchronization memory location (15; 24) adjacent to one data memory location (14; 21).

Description

A buffering method and a buffer
The present invention relates to a method according to the preamble of the appended claim 1 for carrying out buffering in a digital telecommunication system, and a buffer according to the preamble of the appended claim 2.
It is often desirable that the buffering of both asynchronous signals and bit and byte synchronous signals should be carried out by the same circuit. This is especially true in a case where data is transferred from earlier plesiochronous systems to more recent synchronous systems such as the SDH system. For instance, CCITT (recommendation G.709) defines several different mapping modes (asynchronous, bit synchronous and byte synchronous) for a 2048 bit/s signal in the frame structure of the SDH system, depending on the type of the incoming 2048 kbit/s signal [i.e. do the bits arrive for instance asynchronously, or is there, in addition to the clock signal, for instance byte synchronization data (indicating which 8 bits are included in the same byte), frame synchronization data or multiframe synchronization data included] . Asynchronous, bit synchronous and byte synchronous signals are defined in CCITT recommendations G.703 and G.704.
As regards bit and byte synchronous signals, the synchronization is passed through a buffer typically so that together with every data bit, a separate synchronization bit is transferred.
The object of the present invention is to pro** **:de a solution which allows a combined bit and byte buf:....r to be implemented in the simplest possible manner. This object is achieved with the method and the buffer of the invention, the method being characterized by what is described in the characterizing part of the appended claim 1, and the buffer being characterized by what is described in the characterizing part of the appended claim 2. The idea of the invention is to implement the buffer in a certain length with respect to the frame and byte lengths of the data to be transferred and to utilize this length in passing through a synchronization signal by forming a memory location for the synchronization signal bit adjacent to only one data bit. This allows the synchronization signal to be passed in the simplest possible manner through the buffer correctly, i.e. in such a way that the synchronization bit remains in its proper place all the time that the buffer is being read. It is thus possible to pass through the same buffer both an asynchronous signal bit by bit (no separate synchronization signal) or for instance a byte synchronous signal, it being thus possible to pass the synchronization through the buffer by means of an auxiliary memory location that is only one bit in breadth.
Due to the solution of the invention, the number of components decreases or silicon area is saved in those ASICs (Application Specific Integrated Circuit) where bufferings are implemented, because separate bit- and byte-based buffers are no longer needed but can be combined to form a single bit-format buffer.
In the following, the invention and its preferred embodiments are described in more detail with reference to the illustrative examples according to the appended drawings, in which
Figure 1A illustrates the principal features of the bit buffer of the invention, Figure IB illustrates the interdependence between the frame structure of the data coming into the buffer and the buffer, and
Figure 2 shows a more detailed structural alternative of the bit buffer of the invention.
Figure 1 shows the principle of the elastic bit buffer of the invention in simplified form. The core of the buffer consists of a buffer memory 13 which functions as a temporary data storage and with which is associated in a manner known per se (a) a write counter 11, which controls the writing into the buffer memory by giving write addresses to the write input of the buffer memory and (b) a read counter 12, which controls the reading from the buffer memory by giving read addresses to the read input of the buffer memory. The write counter steps in synchronism with a write clock WR_CLK and the read counter in synchronism with a read clock RD_CLK.
In accordance with the invention, the buffer memory consists of M pieces of one-bit data memory locations 14, which are numbered from zero to (M-l), and of one memory location 15 which is arranged for the synchronization bit and which is adjacent to one data memory location 14. The buffer memory length M is connected with a frame 16 (Figure IB) of an incoming signal in such a way that the frame length in bits corresponds to the multiple of the buffer memory length.
In addition, the buffer memory length M must be divisible by the byte length (which is typically eight). The frame length F and the buffer memory length M correlate thus with each other in the following way:
F=KxM=LxB, in which B is the byte length (=8), K is an integer number (K=l,2,3... ), L is also an integer number (the number of time slots in the frame) and L/K is an integer number.
For instance, in the case of 2048 kbit/s basic multiplex system, F=256 (32 8-bit time slots), in which case the buffer length M can be for instance M=64, i.e. a quarter of the frame length.
In accordance with the invention, adjacent to one data memory location 14 (in the same address as the data memory location) there is a similar memory location 15 for the synchronization bit. The synchronization is passed through the buffer by writing a synchronization bit SB to said adjacent memory location 15. In this exemplary case, the synchronization bit is written to the memory location adjacent to the data memory location in address zero, but the synchronization memory location can in principle be situated in any address 0...(M-1) (adjacent to the data memory location situated in said address).
Figure 2 shows a more detailed embodiment of the buffer of the invention. Data memory locations consist in this case of M pieces of D-flip-flops 21, to data inputs D of which is connected incoming data R_DATA. In the figure, the data memory locations are separated from each other by references M(0)...M(M-l) referring to their respective addresses. Besides being connected to the clock input of a write counter 22, the write clock signal WR_CLK is connected to the clock inputs of D-flip-flops 24 and 25 and to the clock inputs of the data memory locations 21. A signal WR_EN enabling writing is connected to enable inputs EN of the write counter 22, of the D-flip-flop 25 and of a decoder 23. The synchronization signal WR_S, which is passed through the buffer, is connected to the synchronization input LD of the write counter and to the data input D of the D-flip-flop 25. The pulse of the synchronization signal constitutes a synchronization bit, which appears in the output of the D-flip-flop 25 at the same time as the write counter output has the value zero.
The output Q of the write counter 22 is connected to the decoder 23, which codes from the counter value an enable signal for each data memory location, this signal enabling writing to said memory location if the enable signal coming to the decoder is active. Besides being connected to the enable input EN of a data memory location 21/M(0) in the address zero, the enable signal acquired from the decoder output zero is connected to the enable input EN of a separate synchronization memory location 24 implemented by one D-flip-flop. In this case, the data memory location 21/M(0) and the synchronization memory location 24 are thus adjacent to each other in the address zero.
The output Q of each data memory location 21 is connected to a corresponding input of a data multiplexer 26, i.e. the output of the memory location zero (M(0)) is connected to the input zero of the data multiplexer, the input of the memory location one (M(l)) is connected to the input one of the multiplexer, etc. , and the output of the data memory location (M(M-l)) in the address M-l is connected to the input (M-l) of the multiplexer.
As regards the output Q of the synchronization memory location 24, it is connected to the first data input (input zero) of the multiplexer 26. To the other data inputs (inputs l-(M-l)) of the multiplexer is connected a fixed value F (zero, for instance), and to the selection input SEL of the multiplexer is connected the output Q of a read counter 28. A synchronization signal RD_S is thus acquired from the output of the multiplexer 27. The write counter 22 steps in synchronism with the write clock signal R_CLK continuously from zero to value (M-l), thus counting incoming bits. Controlled by the decoder, the data bits are written into the data memory locations 21 in succession in such a way that the first bit is written in the address zero, the second bit in the address one etc., and after M bits, the whole procedure is restarted by writing again in the address zero (from which the previous value has by then been read out). During one frame of the incoming signal, the write counter rotates K (for instance 4) revolutions (K=F/M), the synchronization bit SB being thus written into the associated memory location 24 in every K:th revolution when it is assumed that the synchronization bit appears once in the frame.
The read counter steps in a similar manner in synchronism with the read clock signal RD_CLK. When the read counter has the value zero, the synchronization bit is selected to the output of the multiplexer 27, and with the other values of the counter, a predetermined fixed value F is selected to the output.
The output signal of each data memory 0...(M-l) is selected one after another to the output of the data multiplexer 26, whereby a data signal passed through the buffer is acquired from the output of the data multiplexer (this signal being indicated by reference RD_DATA), and the synchronization signal RD_S passed through the buffer is acquired from the output of the multiplexer 27. Even though the invention has been described above with reference to the examples of the accompanying drawings, it will be apparent that the invention is not so restricted but can be varied within the scope of the inventive concept presented above and in the appended claims. The more detailed embodiment of the buffer can be modified for instance with respect to the memory locations by implementing them for instance by either RAM blocks or latches instead of D-flip-flops. Also the form of the synchronization data passed through the buffer can vary: it is possible to use for instance a frame sync signal as the syncronization signal coming into the buffer and to equip the stages following the buffer with counters that count to B (to eight), whereby the byte sync can be determined.

Claims

Claims
1. A method for carrying out buffering in a digital telecommunication system, wherein data is transferred in frames the length of which is F bits, and according to which method data is written into a buffer memory in synchronism with a write clock signal (WR_CLK), and data is read from the buffer memory in synchronism with a read clock signal (RD_CLK), c h a r a c t e r i z e d in that the buffer memory is composed of M pieces of one-bit data memory locations (14; 21), the figure M being selected so that the frame length F is divisible by the figure M, and the figure M is divisible by the byte length, and that the synchronization data passed through the buffer is stored into one-bit synchronization memory location (15; 24) adjacent to one data memory location (14; 21).
2. A buffer used in a digital tele¬ communication system, comprising - a buffer memory (14; 21) for storing data temporarily
- writing and reading means (11, 12; 22, 28) for writing data into the buffer memory (14; 21) and for reading data from the buffer memory, the writing and reading means comprising write and read counters (23, 24) for generating write and read addresses, c h a r ¬ a c t e r i z e d in that the buffer memory (14; 21) comprises M pieces of one-bit data memory locations (14), the figure M being selected so that the frame length F is divisible by the figure M and the figure M is divisible by the byte length, and in that one-bit synchronization memory location (15; 24) is arranged adjacent to one data memory location (14; 21) for storing the synchronization data passed through the buffer.
PCT/FI1994/000462 1993-10-14 1994-10-13 A buffering method and a buffer WO1995010897A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
AU78153/94A AU7815394A (en) 1993-10-14 1994-10-13 A buffering method and a buffer
GB9607820A GB2297464B (en) 1993-10-14 1994-10-13 A buffering method and a buffer
DE4497707A DE4497707B4 (en) 1993-10-14 1994-10-13 Buffering procedures and buffers
DE4497707T DE4497707T1 (en) 1993-10-14 1994-10-13 Buffering procedures and buffers

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FI934544A FI94697C (en) 1993-10-14 1993-10-14 Method for realizing buffering in a digital data communication system as well as a buffer
FI934544 1993-10-14

Publications (1)

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WO1995010897A1 true WO1995010897A1 (en) 1995-04-20

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DE (2) DE4497707B4 (en)
FI (1) FI94697C (en)
GB (1) GB2297464B (en)
WO (1) WO1995010897A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996021897A1 (en) * 1995-01-11 1996-07-18 Telefonaktiebolaget Lm Ericsson (Publ) A data transmission system
EP0758770A1 (en) * 1995-08-14 1997-02-19 Deutsche Thomson-Brandt Gmbh Method and circuit for memory control resynchronization
EP0798863A1 (en) * 1996-03-29 1997-10-01 Koninklijke Philips Electronics N.V. Analogue/digital converter having a high sampling rate

Citations (1)

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Publication number Priority date Publication date Assignee Title
EP0251588A2 (en) * 1986-06-19 1988-01-07 General Datacomm, Inc. Bit interleaved multiplexer system providing byte synchronization for communicating apparatuses

Family Cites Families (1)

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Publication number Priority date Publication date Assignee Title
FI94812C (en) * 1993-05-18 1995-10-25 Nokia Telecommunications Oy Method and apparatus for effecting equalization decisions at a node in a synchronous digital data communication system

Patent Citations (1)

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Publication number Priority date Publication date Assignee Title
EP0251588A2 (en) * 1986-06-19 1988-01-07 General Datacomm, Inc. Bit interleaved multiplexer system providing byte synchronization for communicating apparatuses

Non-Patent Citations (2)

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Title
PATENT ABSTRACTS OF JAPAN, Vol. 10, No. 248, E-431; & JP,A,61 075 649 (HITACHI LTD), 18 April 1986. *
PATENT ABSTRACTS OF JAPAN, Vol. 7, No 288, E-218; & JP,A,58 164 350 (YOKOGAWA DENKI SEISAKUSHO K.K.), 29 Sept. 1983. *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996021897A1 (en) * 1995-01-11 1996-07-18 Telefonaktiebolaget Lm Ericsson (Publ) A data transmission system
US6009107A (en) * 1995-01-11 1999-12-28 Telefonaktiebolaget Lm Ericsson Data transmission system
EP0758770A1 (en) * 1995-08-14 1997-02-19 Deutsche Thomson-Brandt Gmbh Method and circuit for memory control resynchronization
EP0798863A1 (en) * 1996-03-29 1997-10-01 Koninklijke Philips Electronics N.V. Analogue/digital converter having a high sampling rate
FR2746987A1 (en) * 1996-03-29 1997-10-03 Philips Electronics Nv ANALOGUE / DIGITAL CONVERTER WITH HIGH SAMPLING FREQUENCY

Also Published As

Publication number Publication date
FI94697B (en) 1995-06-30
FI934544A0 (en) 1993-10-14
GB2297464B (en) 1997-12-10
DE4497707B4 (en) 2004-12-23
DE4497707T1 (en) 1996-10-31
FI94697C (en) 1995-10-10
GB9607820D0 (en) 1996-06-19
AU7815394A (en) 1995-05-04
FI934544A (en) 1995-04-15
GB2297464A (en) 1996-07-31

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