FI94697C - Method for realizing buffering in a digital data communication system as well as a buffer - Google Patents

Description

94697

The invention relates to a method for implementing buffering in a digital communication system according to the preamble of appended claim 1 and to a buffer according to the preamble of appended claim 2.

10 It would often be desirable to be able to handle buffering of both asynchronous and bit- and byte-synchronous signals on the same circuit. This is especially true in a situation where data is transferred from older plesiochronous systems to newer synchronous systems, such as an SDH system. For example, for a 2048 kbit / s signal, CCITT defines (Recommendation G.709) several different mapping modes (asynchronous, bit synchronous, and byte-synchronous) for the SDH system frame structure, depending on the incoming 2048 kbit / s signal (i.e., whether 20 bits come asynchronously, e.g. , or in addition to the clock signal, for example, byte synchronization information (indicating which 8 bits belong to the same byte), frame synchronization information, or overframe synchronization information). The asynchronous, bit-synchronous, and byte-synchronous signal are defined in CCITT Recommendations G.703 and G.704.

In the case of bit and byte synchronous signals, synchronization is typically passed through a buffer such that a separate synchronization bit is shifted alongside each data bit.

The object of the present invention is to provide a solution which makes it possible to implement a combined bit and byte buffer in the simplest possible way. This object is achieved by a method according to the invention and a buffer according to the invention, 35 methods of which are characterized by what is described in the characterizing part of appended claim 2 94697 and the buffer in turn by what is described in the characterizing part of appended claim 2.

The idea of the invention is to implement a buffer of a certain length with respect to the frame length and the byte length of the data to be transmitted and to use such a length in passing the synchronization signal by creating a memory location for a bit of the synchronization signal alongside only one data bit. In this way, the synchronization signal can be transmitted through the buffer correctly in the simplest possible way, i.e. in such a way that the synchronization bit remains in the correct position at all times when the buffer is read.

Thus, both an asynchronous signal can be transmitted bit by bit (no separate synchronization signal) or e.g. a byte synchronous signal, whereby synchronization is thus made to pass through the buffer by means of an additional memory location with a width of only one bit.

Thanks to the solution according to the invention, the number of components is reduced or the area of silicon is reduced in those ASIC-20 (Application Specific Integrated Circuit) circuits in which buffers are implemented, since separate bit- and byte-based buffers are no longer needed but can be combined into one bit-shaped as a buffer.

The invention and its preferred embodiments will now be described in more detail by way of example with reference to the accompanying drawings, in which Figure 1A shows the basic structure of a bit buffer according to the invention, Figure 1B illustrates the frame structure and buffer .

Figure 1 shows the principle of a flexible 35 bit buffer according to the invention in a simplified manner. The core of the buffer n 3 94697 consists of a buffer memory 13 acting as a temporary storage of data, which is known per se by (a) a write counter 11 which controls writing to the buffer memory by assigning write addresses to the write input of the buffer memory 5; . The write counter steps in step with the write clock WR_CLK and the read counter correspondingly in step with the read clock RD_CLK.

According to the invention, a buffer memory M is formed

a one-bit wide data memory location 14 numbered from zero to (M-1) and a memory location 15 arranged for the synchronization bit adjacent to one data memory location 14. The length M of the buffer memory 15 is bound to the frame 16 of the incoming signal (Fig. 1B) so that the length of the frame in bits corresponds to a multiple of the length of the buffer memory. In addition, the length M of the buffer memory must be divisible by the length of the byte (which is typically eight). Thus, there is the following relationship between the length F of the frame and the length M of the buffer-20 memory: F = KXM = LXB, where B is the length of the byte (= 8), K is an integer (K = 1, 2,3 ...), L is also an integer (the number of time slots in a frame) and L / K is an integer.

For example, in the case of a 2048 kbit / s basic channelization system, F = 256 (32 8-bit time slots), in which case the buffer length M can be e.g. M = 64, i.e. a quarter of the frame length.

According to the invention, in addition to one data memory location 14 (at the same address as the data memory location), there is a similar memory location 15 for the synchronization bit. Synchronization is performed from the buffer by writing the synchronization bit SB to the parallel memory location 35 15. In this example case, the synchronization bit is written to the memory location adjacent to the data memory location at address zero, but the synchronization memory location can in principle be where at any address 0 ... (M-1) (next to the data memory location at that address).

Figure 2 shows a more detailed embodiment of the buffer according to the invention. The data memory locations in this case consist of M pieces D-flip-flops 21, to the data inputs D of which the incoming data WR_DATA is connected. In the figure, the data memory locations are separated by a reference character M (0) ... M (M-1) referring to their address. The label WR_CLK clock signal is connected, not only the write counter 22 to the clock input of the D flip-flops clock inputs 24 and 25 and a data memory locations 21 at the inputs. The write signal WR_EN of the write sal-15 Liva is connected to the enable inputs EN of the write counter 22, the D-flip-flop 25 and the decoder 23. The synchronization signal WR_S, which is passed through the buffer, is connected to the synchronization input LD of the write counter and to the data input D of the D-flip-flop 25. The pulse of the synchronization signal 20 forms a synchronization bit present at

The output Q of the write counter 22 is connected to a decoder 23 which encodes an enable signal from the value of the counter for each memory location 25, which allows writing to that memory location if the enable signal to the decoder is active. The zero enable signal from the decoder output is connected not only to the enable input EN of the data memory location 21 / M (0) at address zero, but also to the enable input EN of the separate synchronization memory location 24 implemented by the D-flip-flop. Thus, in this case, the address zero has a parallel data memory location 21 / M (0) and a synchronization memory location 24.

The output Q of each data memory location 21 is connected to the corresponding input of the data multiplexer 26, i.e., the output of the memory location zero (M (0)) is connected to the input of the data multiplexer zero, the input of the memory location one (M (1)) is connected to the input of the multiplexer one, and so on. , and the output of the data memory location 5 (M (M1)) at the address M1 is connected to the input (M1) of the multiplexer.

The output Q of the synchronization memory location 24 is in turn connected to the first data input of the multiplexer 26 (input zero). A fixed value F (e.g. zero) is connected to the other data inputs 10 of the multiplexer (inputs 1- (M-1)), and the output Q of the read counter 28 is connected to the selection input SEL of the multiplexer. The output of the multiplexer 27 thus provides a synchronization signal RD_S.

The label counter 22 increments the write-side clock signal 15 WR_CLK pace continuously from zero to (M-L), thereby reducing the incoming bits. Under the control of the decoder, the data bits are written to the data memory locations 21 in order so that the first bit is written to address zero, the second bit to address one, etc. During one frame of the incoming signal, the write counter has time to rotate K (e.g. 4) rounds (K = F / M), so the synchronization bit SB 25 is written to the corresponding memory location 24 every K rounds, assuming that the synchronization bit occurs once in the frame.

The counter increments the number corresponding to the number-side clock signal RD_CLK rate. When the read counter has a value of 30 zero, a synchronization bit is selected at the output of the multiplexer 27, the other values of the counter select a predetermined • fixed value F at the output.

The output signal of each data memory 0 ... (M-1) is successively selected at the output of the data multiplexer 26, so that the output of the data multiplexer 35 is transferred through the buffer. · «6 94697 the received data signal (denoted by the reference symbol RD_DA-TA) and the output of the multiplexer 27 results in a synchronization signal RD_S transmitted through the buffer.

Although the invention has been described above with reference to the examples according to the accompanying drawings, it is clear that the invention is not limited thereto, but can be modified within the scope of the inventive idea set forth above and in the appended claims. The more detailed implementation of the buffer can be varied, for example, for muis-10 drops by implementing them instead of D-flip-flops, e.g. with either RAM blocks or latches. The format of the synchronization information transmitted through the buffer can also vary: for example, a frame clock signal can be used as a synchronization signal to the buffer and the degrees after the buffer 15 can be provided with counters that count to B (eight) to determine the byte rate.

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Claims (2)

7 94697 1. A method of buffering to implement a digital telecommunications system in which data transfer 5 unloaded from the frames of length F bits, which method in accordance with the data written to the buffer memory KIR-joituspuolen in synchronization and data clock signal (WR_CLK) consists of a reading-side buffer memory in synchronization with a clock signal (RD_CLK), characterized silo that the buffer memory is formed from M pieces of one-bit wide data memory locations (14; 21), the number M being selected such that the frame length F is divisible by the number M and the number M is divisible by the length of the byte, and that along one data memory location (14; 21) a synchronization information to be transferred through the buffer is stored in a single 15-bit wide synchronization memory location (15; 24). A buffer for use in a digital communication system, comprising - a buffer memory (14; 21) for temporarily storing data 20, - writing and reading means (11, 12; 22, 28) for writing data to the buffer memory (14; 21) and reading data from the buffer memory, which - and the read means comprise write and read counters (23, 24) for generating write and read addresses, characterized in that the buffer memory (14; 21) comprises M data memory locations (14) of one bit width, the number M being selected such that the frame length F is divisible by M and the number M is divisible by the length of the byte, and that a one-bit-wide synchronization memory location (15; 24) is arranged alongside one of the 30 data memory locations (14; 21) to store synchronization information to be transferred through the buffer. 94697 8