GB2297464A - A buffering method and a buffer - Google Patents

A buffering method and a buffer

Info

Publication number
GB2297464A
GB2297464A GB9607820A GB9607820A GB2297464A GB 2297464 A GB2297464 A GB 2297464A GB 9607820 A GB9607820 A GB 9607820A GB 9607820 A GB9607820 A GB 9607820A GB 2297464 A GB2297464 A GB 2297464A
Authority
GB
United Kingdom
Prior art keywords
data
buffer
memory
bit
length
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
GB9607820A
Other versions
GB2297464B (en
GB9607820D0 (en
Inventor
Toni Oksanen
Jari Patana
Esa Viitanen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nokia Oyj
Original Assignee
Nokia Telecommunications Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Telecommunications Oy filed Critical Nokia Telecommunications Oy
Publication of GB9607820D0 publication Critical patent/GB9607820D0/en
Publication of GB2297464A publication Critical patent/GB2297464A/en
Application granted granted Critical
Publication of GB2297464B publication Critical patent/GB2297464B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/16—Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0626—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers plesiochronous multiplexing systems, e.g. plesiochronous digital hierarchy [PDH], jitter attenuators

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Information Transfer Systems (AREA)
  • Communication Control (AREA)

Abstract

The present invention relates to a method for carrying out buffering in a digital telecommunication system, wherein data is transferred in frames the length of which is F bits. According to the method, data is written into the buffer memory in synchronism with a write clock signal (WR.CLK), and data is read from the buffer memory in synchronism with a read clock signal (RD.CLK). In order to implement the combined bit and byte buffer in the simplest possible manner, the buffer memory is composed of M pieces of one-bit data memory locations (14; 21), the figure M being selected so that the frame length f is divisible by the figure M and the figure M is divisible by the byte length, and that the synchronization data passed through the buffer is stored in a one-bit synchronization memory location (15; 24) adjacent to one data memory location (14; 21). <IMAGE>
GB9607820A 1993-10-14 1994-10-13 A buffering method and a buffer Expired - Fee Related GB2297464B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FI934544A FI94697C (en) 1993-10-14 1993-10-14 Method for realizing buffering in a digital data communication system as well as a buffer
PCT/FI1994/000462 WO1995010897A1 (en) 1993-10-14 1994-10-13 A buffering method and a buffer

Publications (3)

Publication Number Publication Date
GB9607820D0 GB9607820D0 (en) 1996-06-19
GB2297464A true GB2297464A (en) 1996-07-31
GB2297464B GB2297464B (en) 1997-12-10

Family

ID=8538782

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9607820A Expired - Fee Related GB2297464B (en) 1993-10-14 1994-10-13 A buffering method and a buffer

Country Status (5)

Country Link
AU (1) AU7815394A (en)
DE (2) DE4497707T1 (en)
FI (1) FI94697C (en)
GB (1) GB2297464B (en)
WO (1) WO1995010897A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE515563C2 (en) * 1995-01-11 2001-08-27 Ericsson Telefon Ab L M data transmission system
DE19529966A1 (en) * 1995-08-14 1997-02-20 Thomson Brandt Gmbh Method and circuit arrangement for resynchronizing a memory management
FR2746987A1 (en) * 1996-03-29 1997-10-03 Philips Electronics Nv ANALOGUE / DIGITAL CONVERTER WITH HIGH SAMPLING FREQUENCY

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0251588A2 (en) * 1986-06-19 1988-01-07 General Datacomm, Inc. Bit interleaved multiplexer system providing byte synchronization for communicating apparatuses

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FI94812C (en) * 1993-05-18 1995-10-25 Nokia Telecommunications Oy Method and apparatus for effecting equalization decisions at a node in a synchronous digital data communication system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0251588A2 (en) * 1986-06-19 1988-01-07 General Datacomm, Inc. Bit interleaved multiplexer system providing byte synchronization for communicating apparatuses

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Patent Abstracts of Japan, Vol 10, No 248,E-431,abstract of JP,A,610075649 (HITACHI LTD) 18.4.86. *
Patent Abstracts of Japan, Vol 7 No 288 E-218,abstract of JP,A,5800164350 VOKOGAWA DENKI. *

Also Published As

Publication number Publication date
FI94697C (en) 1995-10-10
AU7815394A (en) 1995-05-04
FI94697B (en) 1995-06-30
DE4497707B4 (en) 2004-12-23
DE4497707T1 (en) 1996-10-31
GB2297464B (en) 1997-12-10
GB9607820D0 (en) 1996-06-19
FI934544A0 (en) 1993-10-14
WO1995010897A1 (en) 1995-04-20
FI934544A (en) 1995-04-15

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Legal Events

Date Code Title Description
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)
732E Amendments to the register in respect of changes of name or changes affecting rights (sect. 32/1977)
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20111013