KR0153688B1 - A tu aligning apparatus using dram in synchornous transmission system - Google Patents

Abstract

According to the present invention, a TU signal alignment device using DRAM in a synchronous transmission device processes a pointer of received TU1 data to generate a received TU1 clock (Rx TU1 clk) and a received V5 clock (Rx V5 clk), and determines the TU type. A TU1 pointer processing unit (50) for outputting a TU discrimination signal for transmitting; A light clock generator that receives a received TU1 clock (Rx TU1 clk) and a received V5 position clock (Rx V5 clk) from the pointer processor 50 and generates a write clock according to a TU discrimination signal (TU type). 52; Receive arbitrary TU1 clock (Tx TU1 clk) and receive V5 clock (Rx V5 clk) to transmit TU1 data within a predetermined TUG2 clock, and transmit with lead clock (rdad clk) according to TU discrimination signal (TU-type) A lead clock generator 54 generating a V5 position clock Tx V5 clk; And a DRAM 56 storing the VC1 data from which the pointer of the received TU1 data is removed according to the write clock, and outputting the VC1 data according to the read clock and realigning the TU1 data within about 3 TUG2 clocks. .

Description

A TU signal alignment device using DRAM in a synchronous transmission device.

(A) of FIG. 1 is a structural diagram mapping NAS DS1 to VC-11.

(B) of FIG. 1 is a format diagram of V5 which is a low path overhead.

2 is a structural diagram of mapping CEPT DSIE to VC-12.

FIG. 3A is a diagram illustrating the concept of forming TU1 from VC-1.

(B) of FIG. 3 is a format diagram showing the structure of a general pointer.

4 is a schematic view showing a conventional alignment device.

5 is a block diagram showing an alignment device according to the present invention.

(A) to (i) of FIG. 6 are timing diagrams showing rearrangement of VC12 data.

* Explanation of symbols for main parts of the drawings

40: pointer analysis section 42: FIFO buffer

50: TU1 pointer processing unit 52: write clock generator

54: read clock generation unit 56: DRAM

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a synchronous transmission apparatus having a time slot exchange function, and more particularly, to a TU signal alignment apparatus using DRAM that rearranges TU1 signals in order to switch time slots in units of VC1.

In general, a synchronous optical transmission device is an asynchronous multiplexed signal (eg, DS1, DS1E).

) Synchronously multiplexes and converts an optical signal from an optical transmitter to an optical station through an optical cable. As a result, the process of synchronous multiplexing the asynchronous multiplexed signal to form an STM-1 frame of 155.520 Mbps is as follows.

For example, a DS-1 frame is mapped to a box (C: Container) to be C-11, and when a path overhead (POH: Path OverHead) is added thereto, it is a virtual container VC-11. When the pointer PTR is added, it becomes a tributary unit (TU) TU-11. In addition, the TU-11 is grouped into four groups and multiplexed into VC-3 and VC-4 in the form of a hierarchical signal unit group (TUG-2), and three VC-3s are managed through an Admistrative Unit (AU) AU-3. It is multiplexed to become a management unit group (AUG), and SOH is added to it and finally STM-1. At this time, the European DS1E is mapped to C-12, and a path overhead (POH) is added to form the virtual box VC-12.

Here, the box (C) is a basic unit constituting the synchronous multiplexing structure, and the existing asynchronous digital hierarchical signals are synchronously multiplexed by being mapped into the corresponding box, and correspond to C-1, C-2, C-3, There is C-4, and C-1 is again divided into C-11 to map North American DS1 and C-12 to map European DS1E. The virtual box VC is a signal unit for supporting the connection between path layers in synchronous transmission, and the level signal unit TU is a lower path layer VC-1 and VC-2 and the path layer VC-. 3, VC-4) is used to adapt the pointer, and the hierarchy signal unit group (TUG) combines one or more hierarchy unit signals (TU) to align in a fixed position in the upper VC payload space, management The unit (AU) is an AU pointer as a signal unit for providing an adaptation function between the upper path layer and the multiplexer section layer. The management unit group (AUG) combines one or more management unit (AU) signals in the STM pay space. It means that it is aligned at a fixed position.

On the other hand, the structure of the VC-11 formed by mapping the North American DS1 is as shown in (a) of FIG. 1, and the format of the low path overhead is as shown in (b) of FIG.

In Fig. 1A, the structure of VC-11 is formed by 26 bytes in one frame of 125 mu s, and four frames are gathered to form a multi frame of 500 mu s. Therefore, the entire VC-11 consists of 104 bytes, and the first byte of the first frame is called V5, which is the lower path overhead (POH), and has a format as shown in FIG. V5 is followed by one byte with a fixed bit, followed by 24 bytes of information data in which DS1 is mapped. The second frame consists of J2 bytes, Y1 bytes having C1, C2, 0, 0, 0, 0, I, R format, and 24 bytes of information data, and the third frame is Z6 bytes and C1, C2, 0, 0 , Y2 byte having 0,0, I, R format, and 24 bytes of information data, and the fourth frame is Z7 byte and Y3 byte having C1, C2, R, R, R, S1, S2, R format. , And 24 bytes of information data.

Where R denotes a fixed stuffing bit, I denotes an information bit, C denotes a justification control bit, S denotes a justification opportunity bit, and eight zero bits and Z6 are used as preliminary overhead. .

The lower path overhead, V5, consists of BIP-2, FEBE (REI), RFI, signal levels (L1, L2, L3) and remote information (RDI), as shown in FIG. 'BIP-2' indicates the result of the even parity for the odd bit in 1 for all the bytes of the immediately preceding VC11 and inserts the result of the even parity for the even bit in the second bit. 'REI' is 1 when the number of error blocks of BIP-2 is greater than 1 for the signal received from the power, and is sent to the transmitter. 'RFI' inputs the FAIL signal for the FAIL signal for the signal received from the power. If the FAIL signal is not released until after the transfer is completed, it is set to '1' and 'RDI' is set to '1' in case of TU-1 / TU-2 AIS or FAIL. Signal levels L1, L2, and L3 are 0 for non-set, 1 non-specified method, 10 for Asynchronous floation, 11 for bit synchronous, and 100 for byte synchronous.

FIG. 2 is a diagram showing the structure of the VC12 mapped to the European-style DS1E. The structure of the VC-12 is formed by 35 bytes in one frame of 125 μs, and four frames are combined to form a multi frame of 500 μs. Therefore, the entire VC-12 consists of 140 bytes, and the first byte of the first frame is called V5, which is a low path overhead (POH), and has a format as shown in FIG. V5 is followed by R * bytes with fixed bits, followed by 32 bytes of information data mapped with DS1E. The second frame is composed of J2 bytes, Y1 bytes and 32 bytes of information data having C1, C20, 0, 0, 0, R, and R formats, and the third frame is Z6 bytes, C1, C2, 0, 0, 0, It consists of Y2 bytes and 32 bytes of information data in 0, R, R format, and the fourth frame is K4 bytes and Y3 bytes and 32 bytes in C1, C2, R, R, R, R, S1, S2 format. It consists of information data.

Where R denotes a fixed stuffing bit, I denotes an information bit, C denotes a justification control bit, S denotes a justification opportunity bit, and eight zero bits, Z6, and K4 represent preliminary overhead. Used. In addition, V5, which is the low path overhead overhead, is the same as that of VC11.

(A) of FIG. 3 shows the formation of the TU1 signal by adding the low-point pointers V1, V2, V3, and V4 to the format of VC1, and VC11 becomes TU11 by adding V1, V2, V3, and V4. VC12 becomes TU12 with V1, V2, V3, and V4 added. When four TU11s are aligned, the result is TUG2, and when three TU12s are aligned, the result is TUG2.

Where V1, V2, and V3 are used as the lower pointers, the structure is as shown in Fig. 3B, and V4 is reserved for use. At this time, the high-level pointers H1, H2, and H3 used in the AU-4, AU3, and TU-3 are configured in a similar structure.

In (b) of FIG. 3, the first four bits (NNNN) of V1 (H1) are New Data Flag bits, which are 110 in the normal operation state and 1001 when the pointer value is changed to the new value. Is reversed. Next, ss is a signal magnitude bit, and is set to 10 for the high pointers H1, H2, and H3, 0 for TU2, 11 for TU11, and 10 for TU12 in the low pointers V1, V2, and V3. In addition, 10 bits represent the pointer value by adding 2 bits of V1 and V2, and the address of the pointer means the deviation from the pointer H3 to the start point of the VC for the high pointer and the VC from the pointer V2 for the low pointer. It indicates the degree of deviation to the starting point. Also, a 10-bit pointer consists of 5 bits of I bits and 5 bits of D bits so that I bits are inverted when the alignment is performed, and D bits are inverted when the alignment is performed. The address ranges of these pointers are summarized in Table 1 below.

The general description of such a synchronous transmission method is described in detail in pages 101 to 234 of the book Broadband Information Communication, co-authored by Lee Byung-ki and two others.

However, in such a synchronous transmission method, when a synchronous transmission device having a timeslot switching function such as FLC-B is switched in units of VC1, it is necessary to rearrange the TU1 signal received from the power station for switching.

The conventional apparatus for realigning the TU1 signal as described above includes a pointer analyzer configured to extract and interpret a pointer from the received TU1 data as shown in FIG. 4; The pointer is interpreted and configured as a first-in first-out (FIFO) buffer that stores TU1 data according to the light clock generated and outputs TU1 data according to the read clock.

However, the conventional alignment device as described above requires a large number of gates for this because 16x9 registers are used, and there is a problem in that a clock delay occurs in processing.

Accordingly, the present invention has been made to solve the above problems, to provide a TU signal alignment device using a DRAM of a synchronous transmission device that can exchange the time slot in VC1 unit while reducing the gate using the DRAM. The purpose is.

The present invention to achieve the above object

After mapping service data such as DS1 or DS1E signal to VC1, pointer processing is performed to form TU1 signal, TU1 signals are multiplexed to form STM-n synchronous digital level signal, or demultiplexing received STM-n signal to TU1 signal In the synchronous transmission device that can be divided into the time slots, the time slot exchange in VC1 unit,

A TU1 pointer unit configured to generate a received TU1 clock (Rx TU1 clk) and a received V5 clock (Rx V5 clk) by processing a pointer of the received TU1 data, and output a TU discrimination signal for determining a TU type;

A light clock generator which receives a received TU1 clock (Rx TU1 clk) and a received V5 position clock (Rx V5 clk) from the pointer processor and generates a write clock according to a TU discrimination signal;

Receive arbitrary TU1 clock (Tx TU1 clk) and receive V5 clock (Rx V5 clk) for transmitting TU1 data, and within the predetermined TUG2 clock, read clock (clk) and transmit V5 position clock (Tx V5) according to the TU discrimination signal. a lead clock generation unit generating clk); And

The VC1 data from which the pointer is removed from the received TU1 data is stored in accordance with the write clock, and output according to the read clock to realign the TU1 data.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

First, in order for the TU1 signal rearrangement apparatus of the present invention to rearrange the TU1 data, the receiver of the multiplexing apparatus (not shown) receives the STM-1 format data of a large station, and then analyzes the high-level pointers H1 and H2 to locate V1 and V2. We need to be able to find the location of V5 by resolving V1 and V2, and to separate the corresponding TU1 data.

As described above, since the process of demultiplexing from the STM-1 format to a plurality of TU1s is a reverse process of multiplexing as described above, detailed description will not be necessary. Thus, the structure of the pointers used in the demultiplexing process is also described in FIG. Omit it as it is.

As described above, the apparatus of the present invention for rearranging TU1 data received through the demultiplexing process for time slot exchange processes a pointer of the received TU1 data to receive a TU1 clock (Rx TU1 clk). And a TU1 pointer processor (50) for generating a received V5 clock (Rx V5 clk) and outputting a TU discrimination signal for determining the TU type; A light clock generator 52 which receives a received TU1 clock (Rx TU1 clk) and a received V5 position clock (Rx V5 clk) from the pointer processor 50 and generates a light clock (write_clk) according to a TU discrimination signal (TU_type). ); Receive arbitrary TU1 clock (Tx TU1 clk) and receive V5 clock (Rx V5 clk) for transmitting TU1 data, within the specified TUG2 clock, and according to TU discrimination signal (TU_type), read clock (clk) and transmit V5 position clock A lead clock generator 54 generating (Tx V5 clk); And a DRAM 56 storing VC1 data from which the pointer of the received TU1 data is removed in accordance with the write clock, and outputting the VC1 data according to the read clock to rearrange the TU1 data.

Next, the operation of the present invention configured as described above will be described.

The TU1 pointer processing unit 50 according to the present invention extracts the V1, V2, V3, and V4 pointers from the received TU1 data, and the signal size bits of V1 and V2 having the format as shown in (b) of FIG. (ss) is discriminated to generate a TU discrimination signal (TU_type) for identifying whether it is TU11 or TU12. For example, if the signal size bit (ss) is 11, the TU'type is outputted as '1' because the DS1 is mapped TU11, and if the signal size bit (ss) is the 10, the TU'type is outputted as 0 since the DS1E is mapped TU12. A TU1 reception clock for receiving TU1 data is output, and a 10-bit pointer is interpreted to generate a position clock of V5.

The light clock generator 52 receives the received TU1 clock (Rx TU1 clk) and the received V5 position clock (Rx V5 clk) from the pointer processor 50 to generate a light clock (write_clk) according to the TU discrimination signal (TU_type). The lead clock generator 54 receives an arbitrary TU1 clock (Tx TU1 clk) and a received V5 clock (Rx V5 clk) for transmitting TU1 data within a predetermined TUG2 clock (typically 3 clocks), and the TU discrimination signal. A read clock (clk) and a transmit V5 position clock (Tx V5 clk) are generated according to the TU_type, and the DPRAM 56 stores the VC1 data in which the pointer is removed from the received TU1 data according to the light clock. Output according to the read clock to rearrange the TU1 data.

(A) to (i) of FIG. 6 are timing diagrams showing reordering of VC12 data, and show that the VC12 data is rearranged according to the present invention when the TU'type is 0 and TU12 (VC12).

That is, (b) of FIG. 6 is a TU discrimination signal (TU_type) output by the clock generator 50, 0 is (b) represents a receive TUG2 clock (rtug2clk), and (c) represents a receive VC12 clock (rx_vc12ck). (D) represents the received VC1 data (rxvcl_dat). In addition, (e) shows a reception V5 clock (rxv5ck), (f) shows a transmission VC12 clock (tx_vc12ck) for reading TU data stored in DRAM, and (g) shows VC1 data (align_vcl) aligned by DRAM. (G) is a transmission V5 clock (txv5ck) indicating the V5 position of the aligned VC1 data, and (h) and (i) are transmission / reception clocks (tx_vcllck, rx_vcllck) of VC11, in the embodiment of the present invention. If so, there is no output.

In FIG. 6, according to the present invention, the reception V5 position clock (rxv5ck) and the transmission V5 position clock (txv5ck) are aligned within three of the TUG2 clock (rxtug2clk), and in the timings (b) to (e) of FIG. It can be seen that the received VC12 data is rearranged at the same timing as (f) to (g) at the time of transmission.

As described above, according to the present invention, by realigning TU1 data using DRAM to enable time slot exchange in units of VC1, the number of gates required can be reduced, thereby reducing the cost, and in particular, within about 3 TUG2 clocks. This can reduce the delay.

Claims (1)

After mapping service data such as DS1 or DS1E signal to VC1, pointer processing is performed to form TU1 signal, TU1 signals are multiplexed to form STM-n synchronous digital level signal, or demultiplexing received STM-n signal to TU1 signal In the synchronous transmission device capable of time slot exchange in units of VC1 after the separation of the signals, the received TU1 clock (Rx TU1 clk) and the received V5 clock (Rx V5 clk) are generated by processing a pointer of the received TU1 data. A TU1 pointer unit 50 for outputting a TU discrimination signal for determining a TU type; A light clock generator 52 which receives a received TU1 clock (Rx TU1 clk) and a received V5 position clock (Rx V5 clk) from the pointer processor and generates a write clock according to a TU discrimination signal; Receive arbitrary TU1 clock (Tx TU1 clk) and receive V5 clock (Rx V5 clk) for transmitting TU1 data, and within the predetermined TUG2 clock, read clock (clk) and transmit V5 position clock (Tx V5) according to the TU discrimination signal. a lead clock generator 54 generating clk); And a DRAM (56) storing VC1 data from which the pointer is removed from the received TU1 data according to the write clock, and outputting the VC1 data according to the read clock and realigning the TU1 data. Signal aligner.