KR100201331B1 - A remote loop-back circuit using a v4 byte in a synchronous multiplexer - Google Patents

Abstract

The present invention receives the DS1-class signal to form a VC1 transmitter VC1 41; A TU1 transmitter (42) for adding a pointer to the output of the VC1 transmitter to form a TU1 and outputting the result to the TUG2 transmitter; A TU1 receiver 44 which extracts a pointer from the received TUG2 and outputs a VC1 payload; A VC1 receiver 43 which receives a VC1 payload from the TU1 receiver and outputs a DS1 level signal; A power station loopback processor (45) for looping back the DS1 signal output from the VC2 receiver in accordance with the power loopback control signal to the power station; A player loopback request unit 47 for requesting a player loopback to the player using a V4 byte of the TU1 of the corresponding channel when a player loopback request command is input from the terminal; If the V4 byte of the received TU1 is interpreted and a loop loop of a specific channel is requested, a V4 interpreter 46 for outputting a loop loop control signal to the loop loop processing unit is provided to request a loop loop back using the V4 byte. It is possible to loop back to the other station without cooperation of the operator in the system, so the maintenance is easy.

Description

A remote loop-back circuit using a V4 byte in a synchronous multiplexer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous multiplexer, and more particularly, to a remote loopback circuit using V4 bytes in a synchronous multiplexer that enables loopback using V4 bytes.

In general, a synchronous optical transmission device converts an optical signal multiplexed (eg, DS1, DS1E) into a synchronous multiplex, converts it into an optical signal in an optical transmitter, and then transmits the optical signal received from the other station to an optical station. It converts into an electrical signal and then synchronously demultiplexes and outputs a synchronously multiplexed signal. In this synchronous optical transmission device, a process of synchronously multiplexing a synchronously multiplexed signal to form an STM-1 frame of 155.520 Mbps is as follows.

DS1 frame input from the user side is mapped to box (C: Container) and becomes C-11, and when path overhead (POH: Path OverHead) is added, it becomes virtual container VC-11. When the pointer PTR is added, it becomes a tributary unit (TU) TU-11. In addition, the TU-11 is grouped into four groups of TUG-2, and then multiplexed into VC-3 and VC-4, and VC-3 is passed through the management unit (AU) AU-3. The three are multiplexed to form a management unit group (AUG), and a section overhead (SOH) is added thereto to finally become STM-1. At this time, the European DS1E is mapped to C-12, and a path overhead (POH) is added to form the virtual box VC-12. Here, the box (C: Container) is a basic unit constituting the synchronous multiplexing structure (that is, the payload of the VC), and the existing asynchronous digital threshold signals are synchronously multiplexed by being mapped into the corresponding boxes. There are C-1, C-2, C-3, C-4, and C-1 is again divided into C-11 for mapping North American DS1E and C-12 for mapping European DS1EE. In addition, the virtual box (VC) is a signal unit for supporting connection between path layers in synchronous transmission, and a path overhead (POH) is added to the virtual box, and the hierarchy signal unit (TU) is a lower path. It is formed by adding a pointer to the virtual box, and is used to adapt between the layers VC-1 and VC-2 and the upper path layers VC-3 and VC-4. Combine one or more (TU) to align to a fixed position in the upper VC payload space, the management unit (AU) is used as a signal unit to provide the adaptive function between the upper path layer and the multiplexer interval layer, A management unit group (AUG) means that one or more management unit (AU) signals are combined and arranged at a predetermined position in the STM pay space.

On the other hand, the structure of the VC11 formed by mapping the North American DS1 is as shown in Figure 1a, the format of the low path overhead (referred to as V5) is shown in Figure 1b.

In Fig. 1A, the structure of VC11 is formed by 26 bytes in one frame of 125 | Ls, and four frames are gathered to form a multiframe of 500 | Ls. Therefore, the entire VC-11 consists of 104 bytes, and the first byte of the first frame is referred to as V5 as the low path overhead (POH), and has a format as shown in FIG. 1B. V5 is followed by one byte with fixed bits (R, R, R, R, R, R, I, R), followed by 24 bytes of information data with DS1 mapped. The second frame consists of J2 bytes, Y1 bytes having C1, C2, O, O, O, O, I, R formats, and 24 bytes of information data, and the third frame is Z6 bytes and C1, C2, O, O. , Y2 byte having O, O, I, R format, and 24 bytes of information data, and the fourth frame is Z7 byte and Y3 byte having C1, C2, R, R, R, S1, S2, R format. , And 24 bytes of information data.

Where R denotes a fixed stuffing bit, I denotes an information bit, C1, C2 denotes a justification control bit, S1, S2 denotes a alignment enforcement bit, and eight O bits and Z6 indicate a preliminary over. Used as a head

The lower path overhead, V5, consists of BIP-2, FEBE (REI), RFI, signal levels (L1, L2, L3) and remote alarm (RDI), as shown in FIG. 1B. 'Denotes the result of the even parity for the odd-numbered bits at once for all the bytes of the previous VC11 and inserts the result of the even parity for the even-numbered bits into the second bit. 'REI' is 1 when the number of error blocks of BIP-2 is more than 1 for the signal received from the power station, and is sent to the transmitter. 'RFI' after the transfer is completed when the FAIL signal is input to the signal received from the power station. If FAIL signal is not released until then, it is set to 1 and 'RDI' is set to 1 when it is TU-1 / TU-2 AIS or FAIL from the power. Signal level (L1, L2, L3) is 0 is set not set, 1 is set in a non-specific manner, 10 is asynchronous floating (Asynchronous floating), 11 is bit synchronous, 100 is byte synchronous.

FIG. 2 is a diagram showing the structure of the VC12 mapped to the European-style DS1E. The structure of the VC-12 is formed by 35 bytes in one frame of 125 Ls, and four frames are gathered to form a multi frame of 500 Ls. Form. Therefore, the entire VC-12 consists of 140 bytes, and the first byte of the first frame is called V5, which is a low path overhead (POH). V5 is followed by R * bytes with fixed bits, followed by 32 bytes of information data mapped with DS1E. The second frame is composed of J2 bytes, Y1 bytes and 32 bytes of information data having C1, C2, O, O, O, O, R, and R formats, and the third frame is Z6 bytes, C1, C2, O, O, It consists of Y2 bytes and 32 bytes of information data in O, O, R, R format, and the fourth frame is K4 bytes and Y3 bytes and C1, C2, R, R, R, R, S1, S2 format and 32 It consists of bytes of information data.

Where R is a fixed stuffing bit, I is an information bit, C1, C2 is a alignment control bit, S1, S2 is a alignment opportunity bit, and eight O bits and Z6, K4 are Used as preliminary overhead.

FIG. 3A is a diagram illustrating the formation of a TU1 signal by adding the lower pointers V1, V2, V3, and V4 to the format of VC1, wherein VC11 is a pointer TU1, V2, V3, and V4 to be TU11, and VC12 is a pointer. V1, V2, V3, and V4 are added to make TU12. When four TU11s are aligned, the result is TUG2, and when three TU12s are aligned, the result is TUG2.

Here, V1, V2, and V3 are used as the lower pointers, the structure is as shown in Fig. 2B, and V4 is reserved for use. At this time, the high-level pointers H1, H2, and H3 used in the AU-4, AU3, and TU-3, etc., also have a structure similar to the pointers V1, V2, and V3 of the low path.

In FIG. 3B, the first four bits (NNNN) of V1 (H1) are new data flag bits, which are inverted to 1001 when the pointer is 110 in a normal operating state and the pointer value is changed to a new value. Ss is a signal magnitude bit, and is set to 10 for the high pointers H1, H2, and H3, 0 for TU2, 11 for TU11, and 10 for TU12 in the low pointers V1, V2, and V3. In addition, 2 bits of V1 and V2 are added and 10 bits represent a pointer value. The address of the pointer means a deviation from the pointer H3 to the start point of VC in the case of the high pointer, and from the pointer V2 in the case of the low pointer. The degree of deviation from the VC start point. Also, a 10-bit pointer consists of 5 bits of increment (I) bit and 5 bits of decrease (D) bit. When positive justification proceeds, I bit is inverted and negative justification proceeds. The D bit is inverted. Table 1 shows the address range of these pointers.

Address range by pointer Pointer Size (ss) Address range Pointer Size (ss) Address range AU-4 10 0 to 782 TU-2 00 0-427 AU-3 10 0 to 782 TU-12 10 0 to 139 TU-3 10 0 to 764 TU-11 11 0 to 103

As shown in Table 1, in the case of TU12, the size ss is 10, and the address range is 0 to 139. V3 is used as a byte (sub-Justicement Opportunity Byte) for delivering valid data at the positional alignment, and the first byte after V3 is a byte for transmitting invalid data at the right position (justjust). Opportunity bytes).

As described above, after the lower level signals are mapped to VC using the synchronous transmission method, the sub-signal signals are freely floated in the payload space of the corresponding TU. In this case, the positional relationship is stored in the pointers V1, V2, and V3 as described above. Is indicated by. In this way, when the VC is aligned with the TU, its position is not fixed and is changed by the pointer. The floating mode is referred to as floating mode. In contrast, when the TU is synchronized with the VC, the starting point is fixed. It is called locked mode.

On the other hand, when operating a synchronous transmission system, it is necessary to loop back the signal sent from the home station at various stages for maintenance to track a broken path or check the state of a transmission channel. For example, in the synchronous transmission device, it can loop back to the slave station in the low speed multiplexing step or the high speed multiplexing step of the local station to form a transmission path, and then receive the DS1 signal sent from the transmitting station of the local station again at the receiving end of the local station to check the state of the transmission path. In addition, by looping back from the slow multiplexer and the fast multiplexer of the other station, it is possible to check for an error on a relatively long transmission path. At this time, looping back the DS1 level signal to the own station is called local DS1 loopback, and looping back to the station is called DS1 remote loop-back.

However, in the prior art, when processing DS1-class loopback, the multiplexing device required the operator of the local station to handle the loopback of the large-scale loopback through the CIT (Craft Interface Terminal) of the main control unit (MCU) on the terminal. Therefore, there is a problem in that maintenance is difficult because loop back to the other station is impossible without the cooperation of the operator in the other station.

Accordingly, an object of the present invention is to provide a loopback circuit using a V4 byte in a synchronous multiplexing apparatus that enables loopback using a V4 byte used when forming a TU1 to solve the above problems.

In order to achieve the above object, the present invention provides a terminal of a mobile station in a synchronous transmission system in which a mobile station and at least one large station are connected to a transmission path so that data of DS1 level can be exchanged through the same synchronous multiplexing device. A system for enabling the user to loop back the corresponding DS1 in the multiplexing apparatus of the large-sized apparatus when the terminal loopback is requested to the large-sized side, the multiplexing apparatus receiving a DS1 level signal to form a VC1; A TU1 transmitter which adds a pointer to the output of the VC1 transmitter and forms a TU1 and outputs the result to a TUG2 transmitter; A TU1 receiver extracting a pointer from the received TUG2 and outputting a VC1 payload; A VC1 receiver configured to receive a VC1 payload from the TU1 receiver and output a DS1 level signal; A power station loopback processor for looping back the DS1 signal output from the VC1 receiver to the power station according to the power loopback control signal; A player loopback request unit for requesting a player loopback to the player using a V4 byte of the TU1 to which the corresponding DS1 class channel is inputted when a player loopback request command is input from the terminal; And a V4 interpreter for interpreting the received V4 byte of the TU1 and outputting a station loopback control signal to the power loopback processor when the power loopback of the corresponding channel is requested.

As described above, according to the present invention, it is possible to request the loopback using the V4 byte, so that the loopback can be performed at the counterpart without the operator's cooperation in the counterpart.

1A is a schematic diagram of mapping NAS DS1 to VC-11;

1B is a format diagram of V5, which is a low path overhead

2 is a structural diagram mapping a DS1E to VC12;

3A is a diagram illustrating the concept of forming TU1 from VC-1,

3B is a format diagram showing the structure of a general pointer;

4 is a block diagram showing a power loopback circuit using V4 bytes according to the present invention;

5 is an example of a data format of V4 bytes according to the present invention.

* Explanation of symbols for main parts of the drawings

41: VC12 transmitter 42: TU12 transmitter

43: VC12 receiver 44: TU12 receiver

45: power loopback processing section 46: V4 analysis section

47: loopback request unit 48: interface unit

49: Terminal

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 4 is a block diagram showing a part of a multiplexing device capable of processing a large loopback using V4 bytes according to the present invention when using a European DS1E signal as a DS1 class signal. The synchronous multiplexing apparatus to which the present invention is applied includes a terminal 49 for transmitting a control command to the system and monitoring the state of the system, a VC12 transmitter 41 for receiving a DS1E signal to form a VC12, and an output of the VC12 transmitter. After the TU12 is formed by adding a pointer to the TU12 transmitter, the TU12 transmitter 42 outputs to the TUG2 transmitter, the TU12 receiver 44 extracts the pointer from the received TUG2, and outputs the VC12 paid load, and inputs the VC12 payload from the TU12 receiver. A VC12 receiver 43 which receives and outputs a DS1E signal; A power station loopback processor (45) for looping back the DS1E signal output from the VC12 receiver to the power station according to the power loopback control signal; A player loopback request unit 47 for requesting a player loopback to the player using a V4 byte of the TU12 of the corresponding channel when a player loopback request command is input from the terminal; A V4 interpreter 46 is provided for interpreting the received V4 bytes of the TU12 to output the station loopback control signal to the station loop back processor 45 when a station loopback of a specific channel is requested.

That is, in FIG. 4, the case of multiplexing DS1E (European style) according to the present invention is shown as an example, but the technical idea of the same invention may be applied to the case of multiplexing DS1 (North American style). The VC12 transmitter 41 is a block that forms a VC12 signal by adding a low path overhead (POH: V5) after mapping a DS1E signal. In the case of asynchronous mapping, a bit stuffing technique is applied to eliminate the difference between two clocks. do. The FIFO buffer is also used for mapping. The DS1E clock is divided to generate a write clock, and the gapped VC12 clock is divided to generate a read clock. The TU12 transmitter 42 adds the lower TU pointers V1, V2, V3, and V4 to the VC12 signal to form a TU12 signal, and transmits the signal to the TUG2 stage (not shown). In this case, V1 and V2 have information about the address that starts when the VC12 payload is aligned with TU12 as described above, and the difference in transmission speed is set to positive / zero / negative justificastion. To solve it.

The TU12 receiver 44 generates a TU12 pointer clock and a VC12 clock from the received TUG2, extracts the VC12 payload from the TUG2 data, and outputs the VC12 receiver 43 to the VC12 receiver 43, and the VC12 receiver 43 overwrites the received VC12 payload. The head is analyzed and the DS1E signal is sent to the user.

When the loopback control signal is received from the V4 analyzing section 46, the power loopback processing section 45 loops back the DS1E signal output from the VC12 receiving section 43 to the VC12 transmitting section 41 and transmits it to the counterpart. Therefore, the other side can check the condition of the transmission path by receiving the DS1E signal sent back.

The loopback request unit 47, if the user requests a loopback of the power through the operating terminal 49, displays it on the V4 byte and transmits it to the other station through the TU12 transmitter 42, and the V4 analyzer 46 transmits the TU12 receiver ( When the loopback is requested from the counterpart by analyzing the V4 byte received through 44), the loopback control signal is output to the loopback processing unit 45 to control the loopback. At this time, in the preferred embodiment of the present invention, the data format of V4 bytes is used to indicate a loopback command with C7 to C0 bits, as shown in FIG. For example, if the bits C7 to C0 are 0,1,0,1,0,1,0,1, it indicates a loopback request command, and if 1,0,1,0,1,0,1,0 indicates a loopback release command. In normal state, C7 ~ C0 are all 0.

Therefore, in order to request the loopback, the pointer V4 byte is set to 0,1,0,1,0,1,0,1 three times in TU12 data transmitted to the other party, and if the received V4 byte is If 0, 1, 0, 1, 0, 1, 0, 1 is the state that the partner station has requested the loopback, the corresponding loopback processing unit 45 is controlled to perform the loopback. In order to cancel the loopback of the station, the pointer V4 byte is set to 1,0,1,0,1,0,1,0 three times in the TU12 data sent to the other party, and the V4 byte received to the local station is transmitted. If 1,0,1,0,1,0,1,0, the counterpart station has requested the loopback cancellation from the counterpart, and the corresponding loopback processing unit 45 is controlled to release the loopback. In the normal state, V4 byte is transmitted as 0.

As described above, according to the present invention, it is possible to request a loop loop using a V4 byte, so that the loop can be looped back from the counterpart without maintenance of the operator in the counterpart, thereby making maintenance easy.

Claims (2)

In a synchronous transmission system in which a local station and at least one large station are connected to a transmission line to exchange data of DS1 level through the same synchronous multiplexing device, if the operator of the own station requests the loop back to the large station through the terminal, the multiplexing of the large station is performed. In a system that allows the device to loop back the corresponding DS1 signal, The multiplexing device A VC1 transmitter 41 for receiving a DS1 level signal to form VC1; A TU1 transmitter (42) for adding a pointer to the output of the VC1 transmitter to form a TU1 and outputting the result to the TUG2 transmitter; A TU1 receiver 44 which extracts a pointer from the received TUG2 and outputs a VC1 payload; A VC1 receiver 43 which receives the VC1 payload from the TU1 receiver and outputs a DS1 level signal; A power station loopback processor (45) for looping back the DS1 signal output from the VC1 receiver in accordance with the power station loopback control signal to the power station (VC1); A player loopback request unit 47 for requesting a player loopback to the player using a V4 byte of the TU1 of the corresponding channel when a player loopback request command is input from the terminal; When the loopback of the specific channel is requested by analyzing the received V4 byte of the TU1, the synchronous multiplexer provided with the V4 interpreter 46 for outputting the loopback control signal to the power loopback processor 45 is equipped with a V4 byte. Loopback circuit. The synchronous multiplexing apparatus according to claim 1, wherein the loopback request unit transmits 1010101 to V4 bytes as a loopback request command, 10101010 to V4 bytes as a loopback release request command, and transmits 0 in normal operation. Power loopback circuit using bytes.