KR100201332B1 - A local loop back circuit of vc1 in synchronous multiplexer - Google Patents

Abstract

The present invention receives the DS1-class signal to form a VC1 signal VC1 transmitter (41); A TU1 transmitter (42) for adding a pointer to the output of the VC1 transmitter to form a TU1 and outputting the result to the TUG2 transmitter; A TUG2 transmitter 43 for grouping outputs of the TU1 transmitter to form TUG2; A TUG2 receiver 46 for extracting TUG2 data and a clock from the received multiplexed data; A TU1 receiver 45 which extracts a pointer from the output of the TUG2 and outputs a VC1 payload; A VC1 receiver 44 which receives the VC1 payload from the TU1 receiver and outputs a DS1 level signal; A DS1 loopback processor 51 for processing a loopback of the DS1 level according to the loopback control signal; A VC1 loopback processor 52 for processing a loopback of the VC1 level according to the loopback control signal; A TUG2 loopback processing unit 53 for processing the TUG2 loopback according to the loopback control signal; And a loopback control unit 54 for generating a loopback control signal for processing the loopback according to the loopback control command received from the terminal, so that the loopback control of the VC1 class can be processed, so that fault detection can be performed in more detailed steps. Easy to maintain

Description

A local loop-back circuit of VC1 in a synchronous multiplexer

The present invention relates to a synchronous multiplexer, and more particularly, to a VC1 local loopback circuit in a synchronous multiplexer that enables local loopback at the VC1 level in a multiplexing step.

In general, a synchronous optical transmission device converts an optical signal multiplexed (eg, DS1, DS1E) into a synchronous multiplex, converts it into an optical signal in an optical transmitter, and then transmits the optical signal received from the other station to an optical station. It converts into an electrical signal and then synchronously demultiplexes and outputs a synchronously multiplexed signal. In this synchronous optical transmission device, a process of synchronously multiplexing a synchronously multiplexed signal to form an STM-1 frame of 155.520 Mbps is as follows.

DS1 frame input from the user side is mapped to box (C: Container) and becomes C-11, and when path overhead (POH: Path OverHead) is added, it becomes virtual container VC-11. When the pointer PTR is added, it becomes a tributary unit (TU) TU-11. In addition, the TU-11 is grouped into four groups of TUG-2, and then multiplexed into VC-3 and VC-4, and VC-3 is passed through the management unit (AU) AU-3. The three are multiplexed to form a management unit group (AUG), and a section overhead (SOH) is added thereto to finally become STM-1. At this time, the European DS1E is mapped to C-12, and a path overhead (POH) is added to form the virtual box VC-12. Here, the box (C: Container) is a basic unit constituting the synchronous multiplexing structure (that is, the payload of the VC), and the existing asynchronous digital threshold signals are synchronously multiplexed by being mapped into the corresponding boxes. There are C-1, C-2, C-3, C-4, and C-1 is again divided into C-11 for mapping North American DS1E and C-12 for mapping European DS1EE. In addition, the virtual box (VC) is a signal unit for supporting connection between path layers in synchronous transmission, and a path overhead (POH) is added to the virtual box, and the hierarchy signal unit (TU) is a lower path. It is formed by adding a pointer to the virtual box, and is used to adapt between the layers VC-1 and VC-2 and the upper path layers VC-3 and VC-4. Combine one or more (TU) to align to a fixed position in the upper VC payload space, the management unit (AU) is used as a signal unit to provide the adaptive function between the upper path layer and the multiplexer interval layer, A management unit group (AUG) means that one or more management unit (AU) signals are combined and arranged at a predetermined position in the STM pay space.

On the other hand, the structure of the VC11 formed by mapping the DS1 of the North American method is as shown in Figure 1a, the format of the low path overhead (referred to as V5) is shown in Figure 1b.

In FIG. 1A, the structure of VC11 is formed by 26 bytes in one frame of 125 | Ls, and four frames are gathered to form a multiframe of 500 | Ls. Accordingly, the entire VC-11 consists of 104 bytes, and the first byte of the first frame is referred to as V5 as the low path overhead (POH), and has a format as shown in FIG. 1B. V5 is followed by one byte with fixed bits (R, R, R, R, R, R, I, R), followed by 24 bytes of information data with DS1 mapped. The second frame consists of J2 bytes, Y1 bytes having C1, C2, O, O, O, O, I, R formats, and 24 bytes of information data, and the third frame is Z6 bytes and C1, C2, O, O. , Y2 byte having O, O, I, R format, and 24 bytes of information data, and the fourth frame is Z7 byte and Y3 byte having C1, C2, R, R, R, S1, S2, R format. , And 24 bytes of information data.

Where R denotes a fixed stuffing bit, I denotes an information bit, C1, C2 denotes a justification control bit, S1, S2 denotes a alignment enforcement bit, and eight O bits and Z6 indicate a preliminary over. Used as a head

The lower path overhead, V5, consists of BIP-2, FEBE (REI), RFI, signal levels (L1, L2, L3) and remote alarm (RDI), as shown in FIG. 2 'indicates the result of the even parity for the odd-numbered bits at once for all the bytes of the previous VC11 and inserts the result of the even parity for the even-numbered bits into the second bit. 'REI' is 1 when the number of error blocks of BIP-2 is more than 1 for the signal received from the power station, and is sent to the transmitter. 'RFI' after the transfer is completed when the FAIL signal is input to the signal received from the power station. If FAIL signal is not released until then, it is set to 1 and 'RDI' is set to 1 when it is TU-1 / TU-2 AIS or FAIL from the power. Signal level (L1, L2, L3) is 0 is set not set, 1 is set in a non-specific manner, 10 is asynchronous floating (Asynchronous floating), 11 is bit synchronous, 100 is byte synchronous.

2 is a diagram showing the structure of the VC12 mapped to the European-style DS1E. The structure of the VC-12 is formed by 35 bytes in one frame of 125 Ls, and four frames are gathered to form a multi frame of 500 Ls. Form. Therefore, the entire VC-12 consists of 140 bytes, and the first byte of the first frame is called V5, which is a low path overhead (POH). V5 is followed by R * bytes with fixed bits, followed by 32 bytes of information data mapped with DS1E. The second frame is composed of J2 bytes, Y1 bytes and 32 bytes of information data having C1, C2, O, O, O, O, R, and R formats, and the third frame is Z6 bytes, C1, C2, O, O, It consists of Y2 bytes and 32 bytes of information data in O, O, R, R format, and the fourth frame is K4 bytes and Y3 bytes and C1, C2, R, R, R, R, S1, S2 format and 32 It consists of bytes of information data.

Where R is a fixed stuffing bit, I is an information bit, C1, C2 is a alignment control bit, S1, S2 is a alignment opportunity bit, and eight O bits and Z6, K4 are Used as preliminary overhead.

FIG. 3A is a diagram illustrating the formation of the TU1 signal by adding the lower pointers V1, V2, V3, and V4 to the format of VC1. V1, V2, V3, and V4 are added to make TU12. When four TU11s are aligned, the result is TUG2, and when three TU12s are aligned, the result is TUG2.

Here, V1, V2, and V3 are used as lower pointers, the structure is as shown in FIG. 2B, and V4 is reserved for use. At this time, the high-level pointers H1, H2, and H3 used in the AU-4, AU3, and TU-3, etc., also have a structure similar to the pointers V1, V2, and V3 of the low path.

In FIG. 3B, the first 4 bits NNNN of V1 (H1) are New Data Flag bits, which are reversed to 1001 when the pointer is 110 in a normal operating state and the pointer value is changed to a new value. Ss is a signal magnitude bit, and is set to 10 for the high pointers H1, H2, and H3, 0 for TU2, 11 for TU11, and 10 for TU12 in the low pointers V1, V2, and V3. In addition, 2 bits of V1 and V2 are added and 10 bits represent a pointer value. The address of the pointer means a deviation from the pointer H3 to the start point of VC in the case of the high pointer, and from the pointer V2 in the case of the low pointer. The degree of deviation from the VC start point. Also, a 10-bit pointer consists of 5 bits of increment (I) bit and 5 bits of decrease (D) bit. When positive justification proceeds, I bit is inverted and negative justification proceeds. The D bit is inverted. Table 1 shows the address range of these pointers.

Address range by pointer Pointer Size (ss) Address range Pointer Size (ss) Address range AU-4 10 0 to 782 TU-2 00 0-427 AU-3 10 0 to 782 TU-12 10 0 to 139 TU-3 10 0 to 764 TU-11 11 0 to 103

As shown in Table 1, in the case of TU12, the size ss is 10, and the address range is 0 to 139. V3 is used as a byte (sub-Justicement Opportunity Byte) for delivering valid data at the positional alignment, and the first byte after V3 is a byte for transmitting invalid data at the right position (justjust). Opportunity bytes).

As described above, after the lower level signals are mapped to VC using the synchronous transmission method, the sub-signal signals are freely floated in the payload space of the corresponding TU. In this case, the positional relationship is stored in the pointers V1, V2, and V3 as described above. Is indicated by. In this way, when the VC is aligned with the TU, its position is not fixed but is changed by the pointer. This is called floating mode. In contrast, when the TU is synchronized with the VC, the fixed position of the starting point is used. It is called a locked mode.

On the other hand, when operating a synchronous transmission system, it is necessary to loop back the signal sent from the home station at various stages for maintenance to track a broken path or check the state of the transmission channel. For example, in the synchronous transmission device, it can loop back to the slave station in the low speed multiplexing step or the high speed multiplexing step of the local station to form a transmission path, and then receive the DS1 signal sent from the transmitting station of the local station again at the receiving end of the local station to check the state of the transmission path. In addition, by looping back from the slow multiplexer and the fast multiplexer of the other station, it is possible to check for an error on a relatively long transmission path. At this time, looping back the DS1 level signal to the own station is called local DS1 loopback, and looping back to the station is called DS1 remote loop-back.

However, in the conventional loopback circuit, loopback is possible in the DS1 and TUG2 classes, but loopback is not possible in the VC1 class, and thus, when an error occurs in the transmission path between the DS1 and the TUG2, it is difficult to detect a failure.

Accordingly, an object of the present invention is to provide a VC1 local loopback circuit in a synchronous multiplexing apparatus capable of local loopback in VC1 class to solve the above problems.

In order to achieve the above object, the present invention provides a multiplexing device through a terminal in a synchronous transmission system in which a local station and at least one large station are connected to a transmission path to transmit data through the same synchronous multiplexing device. A system for allowing a multiplexer to process a corresponding loopback upon requesting a loopback, the multiplexer receiving a DS1 level signal to form a VC1; A TU1 transmitter which adds a pointer to the output of the VC1 transmitter and forms a TU1 and outputs the result to a TUG2 transmitter; A TUG2 transmitter configured to group the outputs of the TU1 transmitter to form TUG2; A TUG2 receiver for extracting TUG2 data and a clock from the received multiplexed data; A TU1 receiver extracting a pointer from the output of the TUG2 and outputting a VC1 payload; A VC1 receiver configured to receive a VC1 payload from the TU1 receiver and output a DS1 level signal; A DS1 loopback processing unit for processing a DS1 loopback according to a loopback control signal; A VC1 loopback processor for processing a loopback of the VC1 level according to the loopback control signal; A TUG2 loopback processing unit for processing the TUG2 loopback according to the loopback control signal; And a loopback control unit for generating a loopback control signal for processing the loopback according to the loopback control command received from the terminal.

As described above, according to the present invention, the loopback of the VC1 level can be processed, so that fault detection can be performed at a more detailed level, thereby making maintenance easier.

1A is a schematic diagram of mapping NAS DS1 to VC-11;

1B is a format diagram of V5, which is a low path overhead

2 is a structural diagram mapping a DS1E to VC12;

3A is a diagram illustrating the concept of forming TU1 from VC-1,

3B is a format diagram showing the structure of a general pointer;

4 is a block diagram illustrating a VC1 local loopback circuit according to the present invention.

* Explanation of symbols for main parts of the drawings

41: VC12 transmitter 42: TU12 transmitter

43: TUG2 transmitter 44: VC12 receiver

45: TU12 receiver 46: TUG2 receiver

51: DS1 loopback processing unit 52: VC loopback processing unit

53: TUG2 loopback processing section 54: loopback control section

55: terminal

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a block diagram showing a part of a multiplexing device that can handle power loopback using V4 bytes according to the present invention. According to the present invention, a synchronous multiplexing apparatus for multiplexing a DS1E signal includes a terminal 55 for an operator to transmit a control command to a system and monitor a state of the system, and a VC12 transmitter 41 receiving a DS1E signal to form a VC12 signal; A TU12 transmitter (42) for adding a pointer to the output of the VC12 transmitter (42) to form a TU12 and outputting the result to the TUG2 transmitter; A TUG2 transmitter (43) for grouping outputs of the TU12 transmitter to form TUG2; A TUG2 receiver 46 for extracting TUG2 data and a clock from the received multiplexed data; A TU12 receiver 45 for extracting a pointer from the output of the TUG2 and outputting a VC12 paid load; A VC12 receiver 44 which receives the VC12 payload from the TU12 receiver and outputs a DS1E signal; A DS1 loopback processor 51 for processing a loopback of the DS1 level according to the loopback control signal; A VC1 loopback processing unit 52 for processing a loopback of the VC1 level according to the loopback control signal; A TUG2 loopback processing unit 53 for processing the TUG2 loopback according to the loopback control signal; And a loopback control unit 54 for generating a loopback control signal for processing the loopback according to the loopback control command received from the terminal.

In FIG. 4, the VC12 transmitter 41 adds a low path overhead (POH: V5) after mapping the DS1E signal to form a VC12 signal. In the case of asynchronous mapping, in order to eliminate the difference between the two clocks. Bit stuffing technique is applied. The FIFO buffer is also used for mapping. The DS1E clock is divided to generate a write clock, and the gapped VC12 clock is divided to generate a read clock. The TU12 transmitter 42 adds the lower TU pointers V1, V2, V3, and V4 to the VC12 signal to form a TU12 signal, and then transmits the signal to the TUG2 transmitter 43. At this time, V1 and V2, as described above, have information on the address that starts when the VC12 payload is aligned with TU12, and solve the difference in transmission speed by positive / zero / zero alignment. In the case of DS1, the TUG2 transmitter 43 multiplexes four channels to form TUG2. In the case of DS1E, the TUG2 transmitter 43 multiplexes three channels to form TUG2. In a preferred embodiment of the present invention shows a case of DS1E, but the technical spirit of the present invention can be applied as it is to the case of using DS1.

The TUG2 receiver 46 extracts the TUG2 data and the clock from the received multiplexed bitstream and outputs them to the TU12 receiver 45, and the TU12 receiver 45 generates a TU12 pointer clock and a VC12 clock from the received TUG2 from the TUG2 data. The VC12 payload is extracted and output to the VC12 receiver 44, and the VC12 receiver 44 analyzes the overhead of the received VC12 payload and transmits the DS1E signal to the user.

The DS1 loopback processing unit 51 performs loopback control of the DS1 station or station according to the loopback control signal, the VC1 loopback processing unit 52 performs loopback of the local control of the VC12 signal according to the loopback control signal, and the TUG2 loopback processing unit 53. Processes the local or large loopback in TUG2 according to the loopback control signal.

The loopback control unit 54 analyzes the loopback command input through the terminal 55 and performs loopback control with the DS1 loopback processing unit 51, the VC1 loopback processing unit 52, and the TUG2 loopback processing unit 53 to perform a loopback required by an operator. Output the signal.

As described above, according to the present invention, the loopback of the VC1 level can be processed, and thus fault detection can be performed at a more detailed level, thereby maintaining easy maintenance.

Claims (1)

In a synchronous transmission system in which a local station and at least one large station are connected to a transmission line to transmit data through the same synchronous multiplexer, if the operator of the own station requests loopback to the multiplexer through the terminal, the multiplexer processes the loopback. In a system that is able to The multiplexing device A VC1 transmitter 41 which receives a DS1 level signal and forms a VC1 signal; A TU1 transmitter (42) for adding a pointer to the output of the VC1 transmitter to form a TU1 and outputting the result to the TUG2 transmitter; A TUG2 transmitter 43 for grouping outputs of the TU1 transmitter to form TUG2; A TUG2 receiver 46 for extracting TUG2 data and a clock from the received multiplexed data; A TU1 receiver 45 which extracts a pointer from the output of the TUG2 and outputs a VC1 payload; A VC1 receiver 44 which receives the VC1 payload from the TU1 receiver and outputs a DS1 level signal; A DS1 loopback processor 51 for processing a loopback of the DS1 level according to the loopback control signal; A VC1 loopback processing unit 52 for processing a loopback of the VC1 level according to the loopback control signal; A TUG2 loopback processing unit 53 for processing the TUG2 loopback according to the loopback control signal; And a loopback control unit (54) for generating a loopback control signal for processing the loopback according to a loopback control command received from the terminal.