KR100263382B1 - Unit of arranging tributary unit pointer and administration unit pointer for time slot interchange function in fiber loop carrier system - Google Patents

Abstract

PURPOSE: An apparatus of arranging a TU(Tributary Unit) pointer and an AU(Administration Unit) pointer for a TSI(Time Slot Interchange) function in an optical subscriber transmitting device is provided to arrange the TU pointer and the AU pointer, when an inputted TU signal or an AU signal exists in a different position, so as to easily perform the TSI function. CONSTITUTION: An AU(Administration Unit)-32 signal interpreter(210) inputs a 51.84Mhz serial AU-32 signal to convert the signal into a parallel signal, and interprets the AU-32 signal to separate a VC(Virtual Container)-3 signal. A 25Mbps signal output unit(250) outputs an inputted signal as a signal having a 25Mbps transmission rate. An AU-32 signal output unit(280) serially converts an inputted signal, and outputs the serial signal as a signal having a 51.84Mbps transmission rate. A TU(Tributary Unit) signal interpreter/pointer arranger(230) interprets a TU signal, and rearranges pointers of the TU signal to the same position. A VC-3 signal interpreter(220) extracts a path overhead from the VC-3 signal, and transmits the VC-3 signal to the 25Mbps signal output unit(250) or the TU signal interpreter/pointer arranger(230), or to the AU-32 signal output unit(280), according to a C2 byte value of the path overhead. A VC-3 signal shaper(240) adds a path overhead to the pointer-rearranged TU signal, and reshapes a VC-3 signal. An input signal selector(260) selects one of 25Mbps VC-3 signals from other devices, and outputs the selected VC-3 signal. A VC-3 POH inserter(270) inserts a VC-3 path overhead into the outputted VC-3 signal.

Description

Unit of arranging Tributary Unit pointer and Administration Unit pointer for Time Slot Interchange function in Fiber Loop Carrier system

The present invention relates to a TU pointer and an AU pointer alignment device for a TSI function in an optical subscriber transmitter, and in particular, a time slot exchange in an optical subscriber carrier (hereinafter referred to as a fiber loop carrier system). To perform the function, Time Slot Interchange (hereinafter referred to as TSI) may be referred to as a Tributary Unit (hereinafter referred to as a TU) or a Management Unit Signal (hereinafter referred to as an AU) having different pointer positions. The present invention relates to an apparatus for receiving input and rearranging the positions of pointers in the same manner.

In the current FLC system, the synchronous transport module (hereinafter referred to as STM) based on the Synchronous Digital Hierarchy communicates with each other, and the STM signal is a TU signal or an AU. It consists of several signals. In addition, since a plurality of devices generating and transmitting a management unit (hereinafter referred to as AU) signal can generate an AU signal or a TU signal using a clock signal having a different transmission rate, the AU-32 signal exists in the AU-32 signal. Tributary Unit (hereinafter referred to as TU) The location of the signal or the location of the AU signal itself may be different for each device. Therefore, in order to be able to exchange the AU signal or the TU signal on a time slot basis, it is necessary to align the position of the pointer included to inform the position of the data in the AU signal or the TU signal.

Accordingly, the present invention has been made to meet the above needs, and when the input TU signal or the AU signal exists in different positions, the FLC system is a device that facilitates TSI by aligning the pointers. An object of the present invention is to provide a TU pointer and an AU pointer alignment device for a TSI function in the present invention.

In order to achieve the above object, the TU pointer and AU pointer aligner for the TSI function in the FLC system according to the present invention receives a serial AU-32 signal of 51.84Mhz and converts it into a parallel signal, AU-32 An AU-32 signal analysis unit for analyzing the signal and separating the corresponding VC-3 signal; A 25 Mbps signal output unit for outputting the received signal as a signal having a transmission rate of 25 Mbps; An AU-32 signal output unit converting the input signal into a serial signal and outputting the signal as a signal having a transmission rate of 51.84 Mbps; A TU signal analysis and pointer alignment unit for interpreting the TU signal and rearranging the pointers of the TU signal to the same position; Receives the VC-3 signal from the AU-32 signal analyzer and extracts the path overhead added to the VC-3 signal, and according to the value of the C2 byte of the extracted path overhead, the 25 Mbps signal output unit ( 250 or the TU signal analysis and pointer alignment unit 230, or VC-3 signal analysis unit to the AU-32 signal output unit 280; A VC-3 signal forming unit configured to reconstruct a VC-3 signal by adding a corresponding path overhead to the TU signal in which the pointer is rearranged in the TU signal analysis and pointer alignment unit; An input signal selector configured to select one of 25 Mbps VC-3 signals transmitted from other devices and output the selected VC-3 signal; And a VC-3 POH inserter for inserting a corresponding VC-3 path overhead into the VC-3 signal output from the input signal selector.

1 is a structural diagram of mapping to a STM-1 signal for a DS1 level signal;

2 is a block diagram of a TU pointer and AU pointer alignment device for the TSI function in the FLC system according to the present invention;

3 is a configuration diagram of a TU signal analysis and pointer alignment unit;

4 is a configuration diagram of a TU pointer.

* Explanation of symbols for main parts of the drawings

210: AU-32 signal analysis unit 220: VC-3 signal analysis unit

230: TU signal analysis and pointer alignment unit 240: VC-3 signal forming unit,

250: 25 Mbps signal output unit 260: input signal selection unit,

270: VC-3 POH insertion unit 280: AU-32 signal output unit

FIG. 1 is a mapping structure mapping diagram of a DS1-class signal to an STM-1 signal. The DS1 signal 110 is mapped to a C-11 (120), which is a container structure, and a path overhead to the C-11 (120). If is added, the virtual box 130 becomes a virtual container. If a pointer indicating the position of the VC-11 is added to the VC-11 130, the TU-11 140 becomes a TU-11. Four TU-11 (140) are gathered together to generate the subordinate unit signal 150 (TUG-2). The four TUG-11 (140) pointers are located in front of the TUG-2 (150). When seven TUG-2 (150) are collected and a path overhead is added to the forefront, a VC-3 (160) is created. When a pointer 171 is added to the VC-3 (160), an AU-32 (170) is added. ), Three AU-32 (170) are gathered together, and a management unit group (180: AUG) is created, and finally, when section overhead is added to the AUG 180, the STM-1 frame 190 is added. Is generated.

The above-mentioned pointer is used for synchronization processing required for the synchronous multiplexing process. When the virtual box is aligned with the AU or TU, the pointer indicates the starting address of the virtual box within the AU or TU frame, and the starting point may change. Is used to indicate that change relationship.

Hereinafter, each component of the TU pointer and AU pointer alignment device in the FLC system according to the present invention will be described in detail.

2 is a block diagram of a TU pointer and an AU pointer aligning device for the TSI function in the FLC system according to the present invention, AU-32 signal analysis unit 210, VC-3 signal analysis unit 220, TU Signal analysis and pointer alignment unit 230, VC-3 signal forming unit 240, 25Mbps signal output unit 250, input signal selector 260, VC-3 POH insertion unit 270, and AU-32 The signal output unit 280 is formed.

The AU-32 signal analysis unit 210 receives the 51.84Mhz serial AU-32 signal 170 and converts it into a parallel signal, and then the AU-32 indicating the position of the virtual box VC-3 in the AU-32 signal. The AU-32 signal 170 is interpreted with reference to the pointer 171, and the VC-3 signal 160 is separated.

The VC-3 signal analyzer 220 receives the VC-3 signal converted in parallel from the AU-32 signal analyzer 210, extracts the path overhead 161 added to the VC-3 signal, and extracts the extracted VC-3 signal. After analyzing the C2 byte 310 of the path overhead 261, if the C2 byte has a logical value of 04H, it is regarded as a DS3-class signal and sent directly to the 25 Mbps signal output unit 250, and the C2 byte is 02H. If it is a case, it is identified as a TU signal, and sent to the TU signal analysis unit 230, and in other cases, it is sent to the AU-32 signal output unit 280 for use of other devices.

The TU signal analysis and pointer alignment unit 230 refers to the pointer 151 included in the TU signal, interprets the TU signal, and aligns the corresponding pointer.

3 is a configuration diagram of the TU signal analysis and pointer alignment unit 230 for compensating clock differences to synchronize data, and includes a pointer buffer unit 231, a pointer analysis unit 232, and a V5 extraction unit 233. , The reception TU clock generator 234, and the transmission TU clock generator 235.

The pointer buffer section 231 includes VC-3 data from the VC-3 signal analyzer 220, V5 data from the V5 extractor 233, a write clock from the receive TU clock generator 234, and a transmit TU. After receiving the read clock from the clock generator 235, the received VC data and the V5 clock are output using the read clock generated by the transmit TU clock generator 235. In addition, in order to prevent data collision between the transmitter and receiver of the pointer buffer, address difference of four addresses is made, and when the pointer is adjusted, the pointer buffer absorbs the clock phase difference between transmission and reception.

4 is a configuration diagram of a TU pointer, which is composed of V1 data and V2 data, and four bits from N1 to N4 are new data flags, which are fixed to "110" in a normal pointer operation state. If the pointer needs to be changed, it is reversed to "1001". The next two bits (S1, S2) are used to size the data. The last 10 bits consist of 5 Increment and 5 Decrement bits, and if 3 or more bit values of the 5 I bits are inverted, the alignment is assumed to occur. If three or more bit values of the five D bits are inverted, it is assumed that sub-alignment has occurred.

If the input signal rate is less than the system data rate, the pointer analysis unit 232 assumes that an Increment has occurred if inversion occurs in at least three bits of the D bits of the pointer, and processes the dance data of V3 and the next byte. If the signal rate is larger than the system data rate, and if inversion occurs in three or more bits of the I bits of the pointer, a deprement occurs and the pointer analysis is performed by processing the V3 byte as valid data.

The V5 extractor 233 interprets the V1 and V2 bytes of the TU pointer, detects the state of the NDF, SS, pointer value, and the like, and extracts the V5 position clock by TU pointer analysis, and then transmits the data using the same. Create a pointer value.

That is, by using the V1 and V2 data of the TU pointer extracted from the reception pointer analyzer 232, the address of V5 and the VC payload can be known, and by the pointer analysis, it is possible to know whether alignment is generated. Using this, only payload part is input into memory. Data input to the memory are V5 byte position clock and VC data, and the input VC data is extracted using the 208Khz or 288Khz clock according to the TU type.

The reception TU clock generation unit 234 may input data to be written to the pointer buffer unit 231 according to the alignment information detected by the pointer analysis unit 232. That is, when the alignment information is detected, it is determined whether V3 bytes and the next byte have data processing.

The VC-3 signal forming unit 240 adds the path overhead 161 to the TU signal in which the pointer is rearranged in the TU signal analyzing unit 230 to form the VC-3 signal again.

The 25 Mbps signal output unit 250 combines the VC-3 signal reconstructed from the VC-3 signal forming unit 240 or the DS3 signal directly input from the VC-3 signal analysis unit 220 into a signal having a transmission rate of 25 Mbps. Output to perform branch switching.

The input signal selector 260 selects one of 25 Mbps VC-3 signals from other devices and sends the selected signal to the VC-3 POH inserter 270.

The VC-3 POH inserter 270 inserts a corresponding VC-3 path overhead 161 into the VC-3 signal selected and input from the input signal selector 260.

The AU-32 signal output unit 280 converts the signal sent from the VC-3 signal analyzer 220 or the parallel AU-32 signal sent from the VC-3 POH insertion unit 270 into a serial transmission rate of 51.84 Mbps. Output as a signal with

When the TU pointer and the AU pointer aligning device in the FLC system according to the present invention are used, the AU signal is different for each AU-32 signal transmitted by each device, or the AU signal itself is different from each other. Since the position of the pointer included in the signal or the TU signal to indicate the position of the data can be aligned, the AU signal or the TU signal can be exchanged in units of time slots.

Claims (1)

An AU-32 signal analyzer 210 for receiving a 51.84Mhz serial AU-32 signal, converting the signal into a parallel signal, analyzing the AU-32 signal, and separating the VC-3 signal; A 25 Mbps signal output unit 250 for outputting an input signal as a signal having a transmission rate of 25 Mbps; An AU-32 signal output unit 280 converting the input signal into a serial signal and outputting the signal as a signal having a data rate of 51.84 Mbps; A TU signal analysis and pointer alignment unit 230 for interpreting the TU signal and rearranging the pointers of the TU signal to the same position; Receives the VC-3 signal from the AU-32 signal analyzer 210, extracts the path overhead added to the VC-3 signal, and according to the value of the C2 byte of the extracted path overhead, the 25 Mbps signal. A VC-3 signal interpreter 220 which is sent to the output unit 250, the TU signal analysis and pointer alignment unit 230, or the AU-32 signal output unit 280; A VC-3 signal forming unit 240 for reconfiguring the VC-3 signal by adding a corresponding path overhead to the TU signal in which the pointer is rearranged in the TU signal analysis and pointer alignment unit 230; An input signal selector 260 which performs an operation of selecting one of the 25 Mbps VC-3 signals transmitted from other devices and outputs the selected VC-3 signal; And And a VC-3 POH inserter 270 for inserting a corresponding VC-3 path overhead into the VC-3 signal output from the input signal selector 260. TU Pointer and AU Pointer Alignment Unit for TSI Function

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