KR100271311B1 - Pointer processing method of administrative unit and tributary unit - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a management unit pointer and a hierarchy unit pointer processing apparatus for a management unit signal in an optical subscriber transmission apparatus, including a clock unit, an AU-3 signal processing unit, a VC-3 signal processing unit, a TUG-2 signal processing unit, and an external device. It consists of a connection part and a register processing part.

The AU-3 signal processing unit outputs the input AU-3 serial signal as AU-3 parallel data by using a predetermined main clock signal provided by the clock unit, and interprets the AU-3 pointer to convert the VC-3 data. Extraction or receiving VC-3 data and AU-3 pointer information to form an AU-3 signal.

The VC-3 signal processor separates and outputs the received VC-3 data into TUG-2 data, outputs information on a corresponding path overhead, and inputs a predetermined number of transmission TUG-2 data and a predetermined path overhead. Receive and transmit VC-3 data.

The TUG-2 signal processor aligns and outputs the TU pointers of the received TUG-2 data according to a predetermined TU type signal. The external device connection unit selects one of the AU-3 parallel data and the VC-3 data to be transmitted, adjusts the phase to match a predetermined clock, and outputs the register processor. It functions as an interface with the main control unit which is in charge of overall control of

Description

A unit of handling Administrative Unit pointers and Tributary Unit pointers for Administrative Unit-3 signals in a Fiber Loop Carrier system

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a management unit pointer and a hierarchy unit pointer processing device for a management unit signal in an optical subscriber transmission device. In particular, the optical subscriber transmission device uses a management unit signal after receiving a predetermined AU-3 signal. The present invention relates to an apparatus for processing an AU pointer and a TU pointer to perform an insertion and deletion function for each AU) or a hierarchy unit signal (TU).

1 is a basic network configuration diagram of an optical subscriber transmission apparatus, and includes a COT (10: Central Office Terminal) and an RT (11: Remote Terminal). At this time, the COT 10 is connected to each subscriber through a general switching line, a leased line, a local area network (LAN), etc., and these subscribers are connected to a general telephone subscriber or a dedicated line subscriber through the RT 11. .

The COT 10 and the RT 11 constituting the optical subscriber transmission device are connected by the optical cable 12 to perform communication with each other by light. At this time, communication by light between the COT 10 and the RT 11 is performed using a synchronous transmission method. In the synchronous transmission method, signals are multiplexed according to a synchronous multiplexing procedure and then transmitted and received.

FIG. 2 is a diagram illustrating a mapping structure of a DS-1 signal to an STM-1 signal, which is an example of a synchronous multiplexing procedure. The DS-1 signal 110 is mapped to a C-11 120 which is a container structure. When the path overhead 131 is added to the C-11 120, the virtual box 130 becomes a virtual container.

Further, when the pointer 141 indicating the position of the VC-11 is added to the VC-11 130, the unit signal 140 (TU-11) becomes a unit. Signal 150: TUG-2 is generated, with four TU-11 pointers 151 located at the front of TUG-2 150.

When seven TUG-2 (150) are collected and a path overhead is added to the foremost part, a VC-3 (160) is created. When a pointer (171) is added to the VC-3 (160), a management unit signal ( 170: AU-32 is created, three AU-32 (170) are gathered together to form a management unit group signal (180: AUG), and finally, when a section overhead is added to the AUG 180, STM -1 frame 190 is generated.

That is, the DS-1 signal input to the optical subscriber transmission apparatus is transmitted through the optical line 12 after being made into the STM-1 signal through each multiplexing process. In addition, the STM-1 signal input to the optical subscriber transmission apparatus is demultiplexed along the reverse path of the multiplexing path described above to become a DS-1 signal and then transmitted to each subscriber.

On the other hand, as described above, the AU-3 signal appears in the multiplexing procedure or demultiplexing procedure in the optical subscriber transmission apparatus using the synchronous transmission method.

In addition, in order to link with other optical subscriber transmitters constituting the optical subscriber network, an Add / Drop function of an AU-3 signal unit or a TU signal unit is required. It is necessary to align the AU-3 pointer and the hierarchy unit pointer (TU-11 pointer, TU-12 pointer).

Accordingly, the present invention has been made in order to meet the necessity as described above, and is used in the optical subscriber transmission apparatus to receive a predetermined AU-3 signal, and then inserts and inserts each management unit signal (AU) or hierarchy unit signal (TU). In order to perform the deletion function, an object of the present invention is to provide an apparatus for processing an AU pointer and a TU pointer, that is, a management unit pointer and a hierarchy unit pointer processing device for a management unit signal in an optical subscriber transmission device.

In order to achieve the above object, in the optical subscriber transmission device according to the present invention, a management unit pointer and a hierarchy unit pointer processing apparatus for a management unit signal include a clock unit for supplying a predetermined main clock signal; Receives a predetermined AU-3 serial signal, outputs the AU-3 parallel data using the main clock signal, interprets the AU-3 pointer, and outputs the VC-3 data and the predetermined alarm signal, and also the predetermined VC-3. An AU-3 signal processor configured to receive data and predetermined AU-3 pointer information to form and output an AU-3 signal; Analyzes the path overhead of the VC-3 data output from the AU-3 signal processor, separates it into TUG-2 data, outputs the predetermined data and the alarm signal related to the path overhead, and A VC-3 signal processor configured to receive TUG-2 data and a predetermined path overhead, form VC-3 data, and output the UG-3 data to the AU-3 signal processor; According to a predetermined TU type signal, the TU-11 pointer or the TU-12 pointer of the TUG-2 data output from the VC-3 signal processor is aligned, and the aligned TUG-2 data is output to the VC-3 signal processor. A TUG-2 signal processor; An external device connection unit for selecting one of the AU-3 parallel data and the VC-3 data output from the VC-3 signal processor, and adjusting and outputting a phase according to a predetermined clock; And a register processing unit for performing an interface function between the AU-3 signal processing unit, the VC-3 signal processing unit, the TUG-2 signal processing unit, and the external device connection unit and the predetermined main control unit.

At this time, the AU-3 signal processor receives a predetermined AU-3 serial signal using the main clock signal, converts the AU-3 signal into AU-3 parallel data, and outputs the VC-3 signal. An AU-3 signal connection unit configured to receive data and predetermined AU-3 pointer information to form and output an AU-3 signal; One AU-3 data is selected from among the AU-3 parallel data output from the AU-3 signal connection unit and the AU-3 parallel data output from the external device connection unit, the corresponding AU-3 pointer is interpreted, and VC-3 is interpreted. An AU-3 pointer analyzer which extracts and outputs data and a predetermined alarm signal; AU-3 which selects any one of VC-3 data output from the AU-3 pointer analyzer and VC-3 data output from the VC-3 signal processor, and then outputs VC-3 data aligned to a predetermined clock. A pointer buffer unit; And an AU-3 pointer generator which generates predetermined AU-3 pointer information on the sorted VC-3 data output from the AU-3 pointer buffer unit and sends the AU-3 pointer information as an input signal of the AU-3 signal connection unit. Can be.

The VC-3 signal processor may include: a VC-3 signal analyzer configured to extract and output each TUG-2 data and a corresponding VC-3 path overhead from the VC-3 data output from the AU-3 signal processor; An VC-3 alarm processing unit for inspecting C2 bytes, G1 bytes, and H4 bytes among the VC-3 path overheads extracted by the VC-3 signal analysis unit and outputting an alarm signal according to a predetermined rule; A VC-3 overhead connection unit for receiving the VC-3 path overhead extracted from the VC-3 signal analyzer or predetermined VC-3 path overhead data sent from the register processing unit and outputting the predetermined VC-3 path overhead data in a predetermined order; And a plurality of TUG-2 data output from the TUG-2 signal processing unit and a VC-3 path overhead output from the VC-3 overhead connection unit to form VC-3 data and output the VC-3 data. 3 may include a signal generator.

1 is a basic network configuration of an optical subscriber transmission device,

2 is a structural diagram of mapping a DS-1 signal to an STM-1 signal;

3 is a block diagram of an apparatus according to the invention,

4 is a detailed block diagram of an AU-3 signal processor;

5 is a detailed block diagram of a VC-3 signal processor;

6 is a detailed block diagram of a TUG-2 signal processor.

* Explanation of symbols for main parts of the drawings

300: apparatus 310 of the present invention: clock unit

320: AU-3 signal processing unit 321: AU-3 signal connection unit

322: AU-3 pointer analysis unit 323: AU-3 pointer buffer unit

324: AU-3 pointer generation unit 330: VC-3 signal processing unit

331: VC-3 signal analysis unit 332: VC-3 alarm processing unit

333: VC-3 overhead connection unit 334: VC-3 signal generation unit

340: TUG-2 signal processing unit 341: TU signal analysis unit

342: TU type determination unit 343: TU pointer buffer unit

344: TU pointer generator 345: TU signal multiplexer

350: external device connection unit 360: register processing unit

400: main control unit (MCU)

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

3 is a block diagram of an apparatus 300 according to the present invention, which includes a clock unit 310, an AU-3 signal processor 320, a VC-3 signal processor 330, a TUG-2 signal processor 340, and an external device. And a device connection unit 350 and a register processing unit 360.

The present invention 300 receives the 8KHz frame offset clock and 51.84MHz clock supplied from the clock unit 310 as the main clock signal, and the predetermined main controller 400 which is in charge of the overall control of the optical subscriber transmitter. It operates under the control of Main Control Unit.

At this time, the main controller 400 is connected to the main controller 400 through the register processor 360. The register processor 360 has a register (not shown) capable of storing predetermined digital data, so that the main controller 400 Sending and receiving data with is done through the corresponding register.

Among the components of the present invention, the AU-3 signal processor 320 receives a predetermined AU-3 serial signal and outputs the AU-3 parallel data using the main clock signal. In addition, the AU-3 pointer is interpreted to output the received VC-3 payload data and a predetermined alarm signal, and the VC-3 payload data received from the VC-3 signal processor 330 and the AU-3 pointer generated by the AU-3 pointer are generated. Form and output AU-3 signal with information.

The VC-3 signal processor 330 extracts the reception path overhead of the received VC-3 payload data output from the AU-3 signal processor 320, separates the received TUG-2 data, and outputs the received TUG-2 data. Predetermined data on the path overhead and an alarm signal are output. In addition, after forming a predetermined number of transmission TUG-2 data input from the TUG-2 signal processing unit 340 and transmission path overhead received from the register processing unit 360, the AU-3 signal processing unit ( Output to 320).

The TUG-2 signal processor 340 transmits the TU- of received TUG-2 data output from the VC-3 signal processor 330 according to the TU type control signal transmitted from the main controller 400 through the register processor 360. After the 11 pointers or the TU-12 pointers are aligned, the aligned transmit TUG-2 data is output again to the VC-3 signal processor 330.

The external device connection unit 350 selects one of the AU-3 data processed in parallel by the AU-3 signal processor 320 and the transmitted VC-3 data generated by the VC-3 signal processor 330 according to the intended purpose. After selecting, the phase is adjusted to match the predetermined clock and output.

Now, an embodiment of each of the present invention 300 will be described in detail.

4 is a detailed block diagram of the AU-3 signal processor 320, which includes an AU-3 signal connector 321, an AU-3 pointer analyzer 322, an AU-3 pointer buffer 323, and an AU-3. The pointer generator 324 is configured.

The AU-3 signal connection unit 321 receives a 51.84 MHz clock and an 8/2 KHz clock from the clock unit 310, and includes an 8 KHz clock (fr8kro), a 2 KHz clock (f2k), a 6.48 MHz clock (pck), and a 12.96 MHz clock ( mck), and a 25.92 MHz clock (ck25m).

The generated AU-3 parallel signal is converted into AU-3 parallel data by using the generated clock signal, and the AU-3 parallel data is input to the AU-3 pointer analyzer 322 and connected externally. It is also input to the device 350. At this time, when the input AU-3 serial signal is converted to AU-3 parallel data and outputted, at the falling edge when there is not enough phase difference to process at the rising edge of the 51.84 MHz clock. Process.

In addition, the second bit of the C1 byte for the input AU-3 signal is examined, and an error is notified to the register processor 360 when an error occurs.

On the other hand, the 8KHz clock (fr8kro) of the generated clock is used as the frame clock of the AU-3 signal converted into parallel data by the 6.48MHz clock. In addition, the AU-3 pointer generator 324 is used as a reference clock to indicate the start of the AU-3 frame during the AU-3 pointer generation process. In this case, 6.48MHz is used to match the phase with the converted parallel data. The clock is used by delaying a predetermined number of clocks (for example, three clocks).

The 2KHz clock f2k is provided to the TUG-2 signal processing unit 340 to use the reference clock representing the V4 bytes of the multiframe when payload data of the VC-3 signal is formed of the TU-11 signal. In addition, the 6.48 MHz clock (pck) is used to process the AU-3 parallel data input and output, the 12.96 MHz clock (mck) is a clock signal for controlling the 6.48 MHz clock (pck). This 6.48 MHz clock (pck) and 12.96 MHz clock (mck) are also provided to the AU-3 pointer generator 324.

A 25.92 MHz clock (ck25m) is provided to the external connection device 350 to use to phase the output data.

In the transmission process, the VC-3 payload data output from the AU-3 pointer buffer unit 323 and a pointer word determined by the AU-3 pointer generation unit 324 are multiplexed and output as an AU-3 signal. At this time, in order to interface between devices with other devices, the parity of all bits except the C1 byte of the previous frame is calculated and inserted into the second bit position of the C1 byte of the AU-3 signal.

The AU-3 pointer interpreter 322, based on the 8KHz clock (fr8kro) for the start instruction of the AU-3 frame, processes the AU-3 parallel data. 3 generates a clock for extracting data, and also generates a clock for extracting H1 byte and H2 byte with the pointer word inserted.

The VC-3 data is extracted from the AU-3 parallel data output from the AU-3 signal connection unit 321 by using the generated clock signal, and then output.

In addition, by performing pointer analysis on the pointer word read by the H1 byte and H2 byte digit extraction clocks, the AU-3 signal is alarmed, and the VC-3 signal processing clock on the AU-3 payload data is executed. (vckr) and an 8KHz frame clock (rxofsb) are generated and provided to the AU-3 pointer buffer unit 323.

In detail, the alarm processing function is notified of an Alarm Indication Signal (AIS) state when a frame having a logic value of '1' both of H1 byte and H2 byte is detected three times in succession.

If a new data indicator (NDF) is enabled or an inappropriate pointer value is detected for eight consecutive frames, it indicates a pointer loss state (LOP: Loss Of Pointer) and AIS is activated by an NDF enable signal. After clearing the state, the NDF enable value must be input again for 8 consecutive frames to inform the LOP state.

If more than three bits out of four bits of the new data indicator (NDF) match "1001", then it is declared as NDFS (NDF Set) state. If more than three bits match "110", the NDFN state is notified.

In addition, when the pointer value (PV) is 782 or more, it indicates that the pointer value is invalid.

By comparing the pointer value of the previous frame with the pointer value of the current frame, it is determined whether the I bit or the D bit is inverted, and there is no I or D bit inversion in the previous frame and there is no NDF enable value. If the ss bit is " 10 " and the pointer alignment is not prohibited, declare positive justification when inverting the I bit and negative justification when inverting the D bit. At this time, when the alignment occurs, the data extraction clock of the 0 address digit which is the next address of the H3 byte is deleted, and when the misalignment occurs, the clock is generated to read the data of the H3 byte digit.

If the NDF is normal and the ss bit is "10" and has a valid pointer value, the normal pointer state (NPTR: Normal Pointer) is declared, and the ss bit is "10" and has a valid pointer value, and the NDF is set. If it does, it announces the NDF enable. In addition, the pointer value is three consecutive frames without the NPTR state, the NDF enable state, and the pointer alignment (PJE) state and not the AIS state, or not all the NPTR state, NDFE state, and PJE state. In this other case, an invalid pointer state (invalid PTR) is reported.

In addition, when the pointer value is the same while having an NPTR value for three consecutive frames, an EPTR (Exactly correct PTR) is notified.

The AU-3 pointer buffer unit 323 is configured by the AU-3 pointer analyzer 322 and the VC-3 signal processor 330 according to the operation mode selected by the operation mode selection signal sent from the main controller 400. Select one of the output VC-3 data and sort it. That is, when only the alignment of the AU-3 pointer is required, the VC-3 data output from the AU-3 pointer analyzer 322 is selected, and the alignment of the TU pointer (TU-11 pointer or TU-12 pointer) is required. In this case, the VC-3 signal output from the VC-3 signal processor 330 is selected.

At this time, when selecting the VC-3 data extracted by the AU-3 pointer analyzer 322, when pointer alignment occurs, a predetermined memory (e.g., 16) in the AU-3 pointer buffer unit 323 is generated. × Use 9) to handle this.

That is, the VC-3 signal processing clock vckr extracted by the AU-3 pointer analyzer 322 is used as a write clock, but the memory address for writing data is accessed from address 8 and stored in the memory. When reading data, read from address 0, so that data can be processed with 8 address. At this time, the clock used for writing uses the VC-3 signal processing clock vckr, and the clock used for reading uses a predetermined clock vckx for transmitting VC-3 data.

On the other hand, if positive justification occurs in the AU-3 pointer analyzer 322, and the values of the write address and the read address for the memory are close to each other, the address is generated by the sender. This slows down the reading by making the data in memory read as slowly as possible.

In addition, when negative justification occurs and the values of the read address and the write address become close to two addresses, the negative address is generated on the sender side so that the data in the memory can be read as quickly as one address. Keep the distance of 2 or more.

In order to satisfy this function, when a pointer alignment request occurs, first invert the I and D bits of the pointer value of the AU-3 pointer generator 324, and then replace the H3 byte position or the A0 byte position. Control the clock.

The AU-3 pointer generation unit 324 generates an AU-3 pointer, generates and outputs a clock vckx used for reading the memory from the AU-3 buffer unit 323.

Specifically, on the basis of the 8KHz clock (fr8kro) received from the AU-3 signal connection unit 321, a 6.48 MHz clock (pck) and a 12.96 MHz clock (mck) are used to generate the AU-3 signal. Generates a 72 kHz clock for processing section overhead (SOH), a clock for pointer insertion, and a clock (vckx) for transmitting VC-3 signals.

At this time, bits 15 to 11 of the 16 bits of the pointer word to be generated are NDF bits, and the initial NDF value is set to "1001".

In addition, the pointer value indicating the start position of the VC-3 signal is determined, and when the occurrence of the correct and negative alignment is required, the pointer value is immediately reversed by ignoring the previous pointer value and immediately inverting the values of the I and D bits. Create At this time, if the pointer value of the previous frame is 782 and the right alignment occurs, the value of address 0 should be set to the next frame. If the pointer value of the previous frame is 0, the misalignment occurs to the next frame 782. Insert the value of.

Then, a 4-byte NDF ("110" or "1001"), a 2-bit SS ("10"), and a 10-bit pointer value are generated to generate a 2-byte pointer word, and then the AU-3 signal connection unit. Output to 321. At this time, if the alignment does not occur in the process of generating the pointer value and does not equal the pointer value of the previous frame, it is recognized as new data and the NDF value of one frame is inserted as "1001".

Now, the VC-3 signal processor 330 will be described in detail.

5 is a detailed block diagram of the VC-3 signal processor 330, which includes the VC-3 signal analyzer 331, the VC-3 alarm processor 332, the VC-3 overhead connector 333, and the VC-3. And a signal generator 334.

The VC-3 signal analyzer 331 extracts each received TUG-2 data and the corresponding VC-3 path overhead from the received VC-3 data output from the AU-3 signal processor 320 and outputs the extracted overhead.

Specifically, in order to process the path overhead of the received VC-3 data and the fixed byte in the payload, seven 864KHz clocks for extracting each TUG-2 data in the payload are generated. The TUG-2 data is read from the payload using the seven extracted 864KHz clocks, reprocessed to match the 864KHz clock used by the TUG-2 signal processor 340, and then the TUG-2 signal processor. Send to 340.

In this case, the TUG-2 signal processing unit 340 may be configured as seven modules that process one TUG-2 signal, and may process separate TUG-2 signals.

On the other hand, the processing contents for each data of the extracted path overhead are as follows.

The J1 byte can insert the value back into the J1 byte of the path overhead of the transmitted VC-3 data, and output it serially externally.

The C2 byte can be reinserted into the C2 byte of the path overhead of the transmission VC-3 data and outputted serially to the outside. In addition, it is determined whether the value of the C2 byte is "2", and if it is not "2", a C2 reception error is declared, and the value of the C2 byte is notified to the register processing unit 360.

The B3 byte is compared with the calculated value of BIP-8 of the received VC-3 data, and when an error occurs, the B3 byte is accumulated and stored in the register processing unit 360.

For the H4 byte, bit 1 and bit 0 of the extracted data are examined, and if "11", a 2KHz clock is generated to indicate that the TU pointer position of the next VC-3 data is located at V4 byte. Also, if bit 1 and bit 0 do not have the order of "0"-> "1"-> "10"-> "11" by checking the value of every frame, the multiframe loss state (LOMF: Loss Of Multi-) Frame) state to the register processing unit 360.

For the G1 byte, the number of far end block errors (FEBEs) sent from the power station is calculated and notified to the register processing unit 360, and bit 5 is checked to declare a far end receive failure (FERF). At this time, the G1 byte is serially output to the outside.

F2 bytes, Z1 bytes to Z3 bytes are serially output to the outside.

The VC-3 alarm processing unit 332 receives the C2 bytes, G1 bytes, and H4 bytes extracted from the VC-3 signal analysis unit 331, checks them, and sends them to the register processing unit 360 according to a predetermined rule.

That is, when the C2 byte detected by the VC-3 signal analyzer 331 is different from the value of "2", the C2 mismatch state is transmitted to the register processor 360. In addition, by checking the bit 5 of the G1 byte detected by the VC-3 signal analyzing unit 331, and outputting a signal indicating that the FERF state when the logic value '1' has, the VC-3 signal analyzing unit 331 It checks whether LOMF is detected by checking H4 bytes detected by.

The VC-3 overhead connection unit 333 receives the VC-3 path overhead data extracted by the VC-3 signal analysis unit 331 in a predetermined order (J1, B3, C2, G1, F2, Z3, Z4, Z5). Order), and receives the VC-3 path overhead data from the register processor 360 and outputs the signal to the VC-3 signal generator 334 according to the above procedure.

The VC-3 signal generator 334 outputs a predetermined number (7) of transmission TUG-2 data output from the TUG-2 signal processor 340 and the VC-3 path output from the VC-3 overhead connection unit 333. Overhead is multiplexed to generate transmit VC-3 data.

In addition, a 2KHz clock and a 6.48MHz clock are received from the AU-3 signal connection unit 321 to generate a 72KHz clock for path overhead processing and a 216KHz clock for fixed byte processing. In addition, a 864KHz clock (tx864k) for TUG-2 parallel data processing and a multiplexing clock for multiplexing seven TUG-2 data are generated and supplied to the TUG-2 signal processor 340.

At this time, the external data input from the VC-3 overhead connection unit 333 may also be accommodated, and the insertion of H4 bytes may be performed by changing bit 1 and bit 0 of each frame to match the insertion order of the multiframe. 0 "->" 1 "->" 10 "->" 11 "in this order.

6 is a detailed block diagram of the TUG-2 signal processor 340, which includes a TU signal analyzer 341, a TU pointer buffer unit 343, a TU pointer generator 344, a TU signal multiplexer 345, and TU type determination section 342 is made.

First, the TU type determiner 342 determines a type of a TU signal to be processed by the TUG-2 signal processor 340 according to the TUG-2 data output from the VC-3 signal processor 330. .

That is, after finding the pointer position of the first TU-11 signal in the input TUG-2 signal and checking its ss bit, if the value of the ss bit is "10", it is assumed to be a TU-12 signal, and "11". Is assumed to be a TU-11 signal. When the normal pointer state is confirmed for three consecutive frames, the use clock is changed to the changed TU signal. At this time, separate control is possible by the TU type control signal from the register processing unit 360.

The TU signal analyzer 341 uses a 864KHz clock sent from the VC-3 signal processor 330 and a 2KHz clock for designating a V4 byte position of a multi-frame transmitted from the AU-3 signal processor 320, using the TU- This function extracts the clock for V5 digit and the clock for VC-11 processing to operate in 11 mode or TU-12 mode.

After the TU pointer of the received TUG-2 data output from the VC-3 signal processing unit 330 is analyzed, the TU-11 signal or the TU-12 signal is output. At this time, whether the TU-11 signal or the TU-12 signal depends on the TU type signal output from the TU type determiner 342.

The TU pointer buffer unit 343 extracts and outputs the VC-11 data or the VC-12 data from the TU-11 signal or the TU-12 signal output from the TU signal analyzer 341.

Specifically, in order to process the VC-11 data set according to the V5-digit clock and the VC-11 processing clock extracted by the TU signal analyzer 341 into a predetermined transmission clock (eg, 8 × 9 Use memory).

At this time, the write in the initial state is accessed from address 4, and the read starts from address 0. In addition, if the difference between the write address and the read address is narrowed down to 1 by the TU signal analysis unit 341 continuously generating the alignment of the pointer, the TU pointer generation unit 344 requests the occurrence of the alignment. When the sub-alignment occurs in the TU signal analysis unit 341 and the address to which the read address is written is shifted to the address of 1, the sub-alignment generation request is made to the TU pointer generator 344.

The TU pointer generation unit 344 generates predetermined TU pointer information according to the TU type signal, multiplexes the TU-11 signal or the TU-12 signal output from the TU pointer buffer unit 343, and then TU-11 signal or TU. -12 Regenerate and output the signal.

At this time, the pointer value is generated using the V5 clock read from the TU pointer buffer unit 343, and the I and D bits of the pointer value are generated in response to the request for the occurrence of correct or negative alignment from the TU pointer buffer unit 343. The range of pointer values is 0 to 103 for TU-11 and 0 to 139 for TU-12.

The TU signal multiplexer 345 multiplexes a predetermined number of TU-11 signals (4) or TU-12 signals (3) output from the TU pointer generator 344, and outputs the transmitted TUG-2 data. . Since the multiplexed TUG-2 signal can be sent to the VC-3 signal processor 330 for processing, the TU signal can be freely switched afterwards.

The external device connection unit 350 includes AU-3 parallel data processed in parallel by the AU-3 signal connection unit 321 of the AU-3 signal processing unit 320 and transmitted VC-3 data generated by the VC-3 signal processing unit 330. After receiving the input, select one according to the purpose to use, and outputs in phase with the 25.92MHz clock sent from the AU-3 signal processor 320.

On the other hand, the register processing unit 360 is connected to the main control device 400 performs an interface function to exchange a predetermined control signal or data between the device of the present invention and the main control device 400.

The register processor 360 includes a register to store each control signal to be controlled according to a predetermined register bit map, and each bit corresponds to a corresponding functional element.

In addition, the status information and the alarm contents processed and sent from the respective functional elements are arranged in byte units, and sent to the main control device 400 in the order of the register bit map. Then, E-BER and SD are declared according to the accumulated number of BIP-8 errors, and the error is accumulated in 1 byte and reported to the main control device 400.

In addition, the VC-3 signal analyzer 331 receives the G1 byte and accumulates the error number of bits 1 to 4 as 1 byte and reports the result to the main controller 400.

As described above, according to the present invention, the AU pointer and the TU pointer may be aligned by receiving a predetermined AU-3 signal. Therefore, the time slot exchange (TSI) function of the AU-3 signal, the TU-11 signal, and the TU-12 signal unit is enabled in an external device interworking with the device of the present invention, and thus, There is an effect that can provide flexibility.

Claims (3)

Used in a predetermined optical subscriber transmission device using a synchronous transmission method to align the AU-3 pointer, TU-11 pointer, and TU-12 pointer to the AU-3 signal under the control of a predetermined main controller 400 (MCU). An apparatus comprising: a clock unit (310) for supplying a predetermined main clock signal; Receives a predetermined AU-3 serial signal, outputs the AU-3 parallel data using the main clock signal, interprets the AU-3 pointer, and outputs the VC-3 data and the predetermined alarm signal, and also the predetermined VC-3. An AU-3 signal processor 320 for receiving data and predetermined AU-3 pointer information to form and output an AU-3 signal; Analyze the path overhead of the VC-3 data output from the AU-3 signal processor 320, separate the data into TUG-2 data, output the predetermined data and the alarm signal for the path overhead, In addition, the VC-3 signal processing unit 330 for receiving a predetermined TUG-2 data and a predetermined path overhead to form the VC-3 data, and then outputs the VC-3 data to the AU-3 signal processing unit 320; According to a predetermined TU type signal, the TU-11 pointer or the TU-12 pointer of the TUG-2 data output from the VC-3 signal processor 330 is aligned, and the aligned TUG-2 data is aligned with the VC-3 signal processor. A TUG-2 signal processor 340 outputting the signal 330; An external device connection unit 350 that selects one of the AU-3 parallel data and the VC-3 data output from the VC-3 signal processor 330 and adjusts a phase to output a predetermined clock; And An interface function is performed between the AU-3 signal processor 320, the VC-3 signal processor 330, the TUG-2 signal processor 340, and the external device connector 350 and the main controller 400. A management unit pointer and a hierarchy unit pointer processing device for the management unit signal in the optical subscriber transmission device, characterized by including a register processing unit (360). The VC-3 signal processor of claim 1, wherein the AU-3 signal processor 320 receives a predetermined AU-3 serial signal using the main clock signal, converts the AU-3 signal into AU-3 parallel data, and outputs the AU-3 signal. An AU-3 signal connection unit 321 which receives the VC-3 data and the predetermined AU-3 pointer information output from 330 to form and output an AU-3 signal; AU-3 parallel data output from the AU-3 signal connection unit 321 and AU-3 parallel data output from the external device connection unit 350 are selected, and the corresponding AU-3 pointer is selected. An AU-3 pointer analyzer 322 for analyzing and extracting and outputting the VC-3 data and the predetermined alarm signal; After selecting any one of the VC-3 data output from the AU-3 pointer analyzer 322 and the VC-3 data output from the VC-3 signal processor 330, the VC-3 data aligned to a predetermined clock. An AU-3 pointer buffer unit 323 to be outputted as; And Generating predetermined AU-3 pointer information for the aligned VC-3 data output from the AU-3 pointer buffer unit 323 and generating an AU-3 pointer that is sent as an input signal of the AU-3 signal connection unit 321. And a management unit pointer and a hierarchy unit pointer processing device for the management unit signal in the optical subscriber transmission device, characterized by including a unit (324). The VC-3 signal processor 330 extracts and outputs each TUG-2 data and a corresponding VC-3 path overhead from the VC-3 data output from the AU-3 signal processor 320. A VC-3 signal analyzer 331; The VC-3 alarm processing unit 332 which examines C2 bytes, G1 bytes, and H4 bytes among the VC-3 path overheads extracted by the VC-3 signal analysis unit 331 and outputs an alarm signal according to a predetermined rule. ; The VC-3 path that receives the VC-3 path overhead extracted from the VC-3 signal analysis unit 331 or the predetermined VC-3 path overhead data sent from the register processing unit 360 and outputs them in a predetermined order. Head connecting portion 333; And VC-3 data is formed by multiplexing a predetermined number of TUG-2 data output from the TUG-2 signal processor 340 and the VC-3 path overhead output from the VC-3 overhead connection unit 333. And a management unit pointer and a hierarchy unit pointer processing device for the management unit signal in the optical subscriber transmission device, characterized in that it comprises a VC-3 signal generation unit 334 for outputting afterwards.