KR100201330B1 - A circuit for compensating timing error of v5 clocks caused by reseting a tu pointer buffer in a synchronous multiplexer - Google Patents

Abstract

According to the present invention, the corresponding VC payload is stored in the buffer 45 from the TUG data according to the write address formed by dividing the write clock determined according to alignment with the received TUG2 clock, and the read clock is divided according to the read address. In the synchronous multiplexing device configured to read data from the buffer 45, the write address and the read address are compared to output a buffer full signal pbfull when the buffer 45 is full, and a buffer beam signal when the buffer is empty. an address comparison unit 47 for outputting pbempty; When the buffer beam signal or the buffer full signal pbfull is generated or the buffer reset signal pbset is input, the write address generator 44, the read address generator 45, the buffer 45, and the address comparison are performed. The unit 47 and the transmission V5 clock generation unit 47 are reset, and a TU clock generation unit 42 is included when a reset signal (reset) is input, and the write address generation unit 44 or the read address generation unit ( 46, a reset processing unit 43 for resetting the buffer 45, the address comparison unit 47, and the transmission V5 clock generation unit 49; A transmit V5 clock generation unit 49 which receives the V5 position clock from the buffer, receives the transmit clock, and generates a compensated transmit V5 clock in consideration of the address difference according to reset and buffer reset, includes a write address at the time of buffer reset. There is an effect that can compensate for the deviation of the V5 position clock caused by the difference between the and the read address.

Description

A circuit for compensating timing error of V5 clocks caused by reseting a TU pointer buffer in a synchronous multiplexer

The present invention relates to a synchronous multiplexing device. In particular, the VC payload is stored in the buffer according to the write clock from the TUG2 received from the counterpart, and then read in accordance with the read clock and transmitted to the other counter. The present invention relates to a circuit for compensating for the deviation of the V5 position clock due to a difference between an address and a read address.

In general, a synchronous optical transmission device converts an optical signal multiplexed (eg, DS1, DS1E) into a synchronous multiplex, converts it into an optical signal in an optical transmitter, and then transmits the optical signal received from the other station to an optical station. It converts into an electrical signal and then synchronously demultiplexes and outputs a synchronously multiplexed signal. In this synchronous optical transmission device, a process of synchronously multiplexing a synchronously multiplexed signal to form an STM-1 frame of 155.520 Mbps is as follows.

DS1 frame input from the user side is mapped to box (C: Container) and becomes C-11, and when path overhead (POH: Path OverHead) is added, it becomes virtual container VC-11. When the pointer PTR is added, it becomes a tributary unit (TU) TU-11. In addition, the TU-11 is grouped into four groups of TUG-2, and then multiplexed into VC-3 and VC-4, and VC-3 is passed through the management unit (AU) AU-3. The three are multiplexed to form a management unit group (AUG), and a section overhead (SOH) is added thereto to finally become STM-1. At this time, the European DS1E is mapped to C-12, and a path overhead (POH) is added to form the virtual box VC-12. Here, the box (C: Container) is a basic unit constituting the synchronous multiplexing structure (that is, the payload of the VC), and the existing asynchronous digital threshold signals are synchronously multiplexed by being mapped into the corresponding boxes. There are C-1, C-2, C-3, C-4, and C-1 is again divided into C-11 for mapping North American DS1E and C-12 for mapping European DS1EE. In addition, the virtual box (VC) is a signal unit for supporting connection between path layers in synchronous transmission, and a path overhead (POH) is added to the virtual box, and the hierarchy signal unit (TU) is a lower path. It is formed by adding a pointer to the virtual box, and is used to adapt between the layers VC-1 and VC-2 and the upper path layers VC-3 and VC-4. Combine one or more (TU) to align to a fixed position in the upper VC payload space, the management unit (AU) is used as a signal unit to provide the adaptive function between the upper path layer and the multiplexer interval layer, A management unit group (AUG) means that one or more management unit (AU) signals are combined and arranged at a predetermined position in the STM pay space.

On the other hand, the structure of the VC11 formed by mapping the North American DS1 is as shown in Figure 1a, the format of the low path overhead (referred to as V5) is shown in Figure 1b.

In Fig. 1A, the structure of VC11 is formed by 26 bytes in one frame of 125 | Ls, and four frames are gathered to form a multiframe of 500 | Ls. Therefore, the entire VC-11 consists of 104 bytes, and the first byte of the first frame is referred to as V5 as the low path overhead (POH), and has a format as shown in FIG. 1B. V5 is followed by one byte with fixed bits (R, R, R, R, R, R, I, R), followed by 24 bytes of information data with DS1 mapped. The second frame consists of J2 bytes, Y1 bytes having C1, C2, O, O, O, O, I, R formats, and 24 bytes of information data, and the third frame is Z6 bytes and C1, C2, O, O. , Y2 byte having O, O, I, R format, and 24 bytes of information data, and the fourth frame is Z7 byte and Y3 byte having C1, C2, R, R, R, S1, S2, R format. , And 24 bytes of information data.

Where R denotes a fixed stuffing bit, I denotes an information bit, C1, C2 denotes a justification control bit, S1, S2 denotes a alignment enforcement bit, and eight O bits and Z6 indicate a preliminary over. Used as a head

The lower path overhead, V5, consists of BIP-2, FEBE (REI), RFI, signal levels (L1, L2, L3) and remote alarm (RDI), as shown in FIG. 1B. 'Denotes the result of even parity for odd bits for all bytes of the previous VC11 at once, and inserts the result of even parity for even bits in bit 2. 'REI' is 1 when the number of error blocks of BIP-2 is more than 1 for the signal received from the power station, and is sent to the transmitter. 'RFI' after the transfer is completed when the FAIL signal is input to the signal received from the power station. If FAIL signal is not released until then, it is set to 1 and 'RDI' is set to 1 when it is TU-1 / TU-2 AIS or FAIL from the power. Signal level (L1, L2, L3) is 0 is set not set, 1 is set in a non-specific manner, 10 is asynchronous floating (Asynchronous floating), 11 is bit synchronous, 100 is byte synchronous.

FIG. 2 is a diagram showing the structure of the VC12 mapped to the European-style DS1E. The structure of the VC-12 is formed by 35 bytes in one frame of 125 Ls, and four frames are gathered to form a multi frame of 500 Ls. Form. Therefore, the entire VC-12 consists of 140 bytes, and the first byte of the first frame is called V5, which is a low path overhead (POH). V5 is followed by R * bytes with fixed bits, followed by 32 bytes of information data mapped with DS1E. The second frame is composed of J2 bytes, Y1 bytes and 32 bytes of information data having C1, C2, O, O, O, O, R, and R formats, and the third frame is Z6 bytes, C1, C2, O, O, It consists of Y2 bytes and 32 bytes of information data in O, O, R, R format, and the fourth frame is K4 bytes and Y3 bytes and C1, C2, R, R, R, R, S1, S2 format and 32 It consists of bytes of information data.

Where R is a fixed stuffing bit, I is an information bit, C1, C2 is a alignment control bit, S1, S2 is a alignment opportunity bit, and eight O bits and Z6, K4 are Used as preliminary overhead.

3A is a diagram illustrating the formation of a TU1 signal by adding the lower pointers V1, V2, V3, and V4 to the format of VC1. V1, V2, V3, and V4 are added to make TU12. When four TU11s are aligned, the result is TUG2, and when three TU12s are aligned, the result is TUG2.

Here, V1, V2, and V3 are used as lower pointers, the structure is as shown in Fig. 2B, and V4 is reserved for use. At this time, the high-level pointers H1, H2, and H3 used in the AU-4, AU3, and TU-3, etc., also have a structure similar to the pointers V1, V2, and V3 of the low path.

In FIG. 3B, the first four bits NNNN of V1 (H1) are new data flag bits and are reversed to 1001 when the pointer is 110 in a normal operating state and the pointer value is changed to a new value. Ss is a signal magnitude bit, and is set to 10 for the high pointers H1, H2, and H3, 0 for TU2, 11 for TU11, and 10 for TU12 in the low pointers V1, V2, and V3. In addition, 2 bits of V1 and V2 are added and 10 bits represent a pointer value. The address of the pointer means a deviation from the pointer H3 to the start point of VC in the case of the high pointer, and from the pointer V2 in the case of the low pointer. The degree of deviation from the VC start point. Also, a 10-bit pointer consists of 5 bits of increment (I) bit and 5 bits of decrease (D) bit. When positive justification proceeds, I bit is inverted and negative justification proceeds. The D bit is inverted. Table 1 shows the address range of these pointers.

Address range by pointer Pointer Size (ss) Address range Pointer Size (ss) Address range AU-4 10 0 to 782 TU-2 00 0-427 AU-3 10 0 to 782 TU-12 10 0 to 139 TU-3 10 0 to 764 TU-11 11 0 to 103

As shown in Table 1, in the case of TU11, the size ss is 11 and the address range is 0 to 103. V3 is used as a byte (sub-Justicement Opportunity Byte) for delivering valid data at the positional alignment, and the first byte after V3 is a byte for transmitting invalid data at the right position (justjust). Opportunity bytes).

As described above, after the lower level signals are mapped to VC using the synchronous transmission method, the sub-signal signals are freely floated in the payload space of the corresponding TU. In this case, the positional relationship is stored in the pointers V1, V2, and V3 as described above. Is indicated by. In this way, when the VC is aligned with the TU, its position is not fixed but is changed by the pointer. This is called floating mode. In contrast, when the TU is synchronized with the VC, the fixed position of the starting point is used. It is called a locked mode.

On the other hand, when operating a synchronous transmission system in an ADD / DROP type, it is necessary to switch the lower level signal received from the counterpart in VC units and transmit it to another counterpart, taking into account alignment from the reception clock. After the payload extraction clock is formed, the effective load is stored in the buffer, read according to the read clock, and transferred to the other counterpart. At this time, the received valid data is stored in the buffer according to the write address generated by dividing the write clock and read according to the read address formed by dividing the read clock. The write address and the read address are generally separated from each other. . For example, in the case of a buffer having eight addresses, the write address and the read address have a difference of about 4 so as to always access the data. However, since the write address and the read address are separated from each other, useless data is initially stored in the read address area at the time of buffer reset. Therefore, it is necessary to start reading after writing valid data. That is, if the write address starts from 0 at the time of reset in the buffer having 8 addresses, the read address starts from 4, so if the write and read start immediately, the data is read early. Therefore, at the time of buffer reset, read should be started after one buffer write operation is performed.

Accordingly, in order to satisfy the above necessity, the present invention provides a TU pointer buffer reset to compensate for misalignment of the V5 clock according to the difference between the write address and the read address when the buffer is reset when switching and transmitting the received hierarchical signal in units of VC1. To provide a V5 clock position compensation circuit.

In order to achieve the above object, the present invention stores the corresponding VC1 payload in the buffer from the TUG data and divides the read clock according to the write address formed by dividing the write clock determined according to the alignment with the received TUG2 clock. A synchronous multiplexing device configured to read data from a buffer according to a read address formed by the method, wherein the write address is compared with the read address to output a buffer full signal when the buffer is full, and output a buffer beam signal when the buffer is empty. A comparator; When the buffer beam signal or the buffer full signal is generated or the buffer reset signal is input, the write address generation unit, the read address generation unit, the buffer, the address comparison unit, and the transmission V5 clock generation unit are reset, and when the reset signal is input, the TU clock is generated. A reset unit for resetting the write address generation unit, the read address generation unit, the buffer, the address comparison unit, and the transmission V5 clock generation unit; And a transmission V5 clock generation unit configured to receive a V5 position clock from the buffer, receive a transmission clock, and generate a compensated transmission V5 clock in consideration of address differences according to reset and buffer reset.

1A is a schematic diagram of mapping NAS DS1 to VC-11;

1B is a format diagram of V5, which is a low path overhead

2 is a structural diagram mapping a DS1E to VC12;

3A is a diagram illustrating the concept of forming TU1 from VC-1,

3B is a format diagram showing the structure of a general pointer;

4 is a block diagram showing a circuit for extracting and transmitting a VC payload from a received TUG in accordance with the present invention;

FIG. 5 is a detailed block diagram of the transmission V5 clock generator shown in FIG. 4.

* Explanation of symbols for main parts of the drawings

41: TUG receiving processing unit 42: TU clock generating unit

43: reset processing unit 44: write address generation unit

45: FIFO buffer 46: lead address generation unit

47: address comparison 48: OA gate

49: transmit V5 clock generator

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a diagram illustrating a part of generating a VC1 payload extraction clock from a TUG2 received from a counterpart according to the present invention, extracting VC1 data, and then transmitting the data to another counterpart. In FIG. 4, a circuit for extracting and transmitting a payload from the received TUG2 includes a TUG receiving processor 41, a TU clock generator 42, a reset processor 43, a write address generator 44, and a FIFO buffer. 45, a read address generator 46, an address comparator 47, an OR gate 48, and a transmit V5 clock generator 49.

The TUG receiving processor 41 receives the TUG2 data and the clock received from the other side, and outputs a received V5 position clock (rV5ck), a received TU clock (rtuck), a TUG data (rtugdata), and a TUG clock (rtugclk), and outputs a TU clock. The generation unit 42 receives the output of the TUG receiving processor 41 and buffers the 8-bit TUG data tugdata [0: 7] and the 1-bit V5 position clock V5ck [8] via the bus. 45), and outputs the TU clock to the write address generator 44. FIG. Here, the TUG2 clock (tugck) is a clock for transmitting TUG2 data of about 6048 Kbps, the receiving TU clock (rtuck) is a clock including the TU pointer and the VC1 payload, VC1 clock is 26 in the receiving TU clock if VC11 One bit per bit The pointers V1, V2, V3, and V4 clocks are gapped VC payload clocks.

The write address generator 44 is implemented as a binary counter to divide the TU clock output from the TU clock generator 42 to generate a write address, and the read address generator 46 is implemented as a binary counter. The read clock is divided to generate a read address. The FIFO buffer 45 receives and stores the 8-bit payload and the V5 position clock from the TUG2 data at the address designated by the write address, reads the data specified by the read address, and outputs the 8-bit payload as the payload of the transmission. The V5 position clock is outputted to the transmission V5 clock generator 49.

The reset processing unit 43 receives an ORA gate for performing an OR operation by receiving the ORB of the buffer reset signal pbset input from the outside, the buffer beam pbempty and the buffer full signal pbfull output from the address comparator. 43-1), an ORA 43-2 for performing an OR operation on the reset signal reset and the output of the ORA 43-1, and an inverting buffer 43-4 and an ORAQ inverting the reset signal. And an inverting buffer 43-3 for inverting the output of 43-2). At this time, when the reset signal is activated, the TU clock generator 42 includes the write address generator 44, the read address generator 46, the FIFO buffer 45, the address comparator 47, and the transmit V5 clock. When the generator 49 is reset and the buffer reset signal pbset or the address error signal add_fail is generated, the address of the write address generator 44 or the read address generator 46 is initialized, and the FIFO buffer ( 45), the address comparison section 47, and the transmission V5 clock generation section 49 are reset.

The address comparison unit 47 is a buffer full detection unit for generating a buffer full signal (pbfull) when the read address matches the write address, and a buffer beam detection unit for generating a buffer beam signal (pbempty) when the write address matches the read address. And a buffer full detection unit and a buffer beam detection unit each include an exclusive or gate for comparing the write address and read address bit by bit. The buffer full signal pbfull and the buffer beam signal pbempty of the address comparison unit 47 are ORed at the OR gate 48 and are output to the reset processing unit 43 as the address error signal add_fail.

As shown in FIG. 5, the transmission V5 clock generator 49 includes a binary counter 51, an end gate 52, first and second latches 53.54, and a multiplexer 55. The V5 position clock is input from the 45 and the transmission clock is input to generate the compensated transmission V5 clock tv5ck in consideration of the address difference according to the reset and the buffer reset. Referring to FIG. 5, when the buffer reset signal pbset is input, the binary counter 51 receives an initial count value from the abcd input terminal, counts according to the TU clock, and the AND gate 52 counts the counter. The qa, qc, and qbn signals at (51) are ANDed and output to the d input terminal of the first latch 53. The first latch 53 outputs the inputted output of the AND gate 52 according to a clock, and the second latch 54 receives logic 1 as the d input terminal and according to q output of the first latch 53. The latch is output to the selection terminal s of the multiplexer 55. The multiplexer 55 is a 2x1 multiplexer which receives logic 1 at terminal a, receives V5 position clock pbv5 input from buffer 45 at terminal b, and outputs the second latch 54 according to the output of the second latch 54. Select to print. At this time, the s input of the multiplexer becomes 0 for a predetermined clock after the buffer reset (pbset) starts, selects logic 1 and outputs it, and when the s input is 1, the v5 position clock (pbv5) input from the buffer 45 is selected. To print.

As described above, when the VC payload is stored in the buffer from the TUG2 received from the counterpart according to the write clock, and then read according to the read clock and transmitted to the other counterpart, the write address and the read address difference when the buffer is reset. There is an effect that can compensate for the deviation of the V5 position clock generated by.

Claims (2)

The VC payload is stored in the buffer 45 from the TUG data according to the write address formed by dividing the write clock determined according to the alignment with the received TUG2 clock and the read clock is divided into the buffer 45 according to the read address formed by dividing the read clock. In a synchronous multiplexer that reads data from An address comparator 47 for comparing the write address with the read address and outputting a buffer full signal when the buffer 45 is full and outputting a buffer beam signal when the buffer is empty; When the buffer beam signal or the buffer full signal pbfull is generated or the buffer reset signal pbset is input, the write address generator 44, the read address generator 45, the buffer 45, and the address comparison are performed. The unit 47 and the transmission V5 clock generation unit 47 are reset, and a TU clock generation unit 42 is included when a reset signal (reset) is input, and the write address generation unit 44 or the read address generation unit ( 46, a reset processing unit 43 for resetting the buffer 45, the address comparison unit 47, and the transmission V5 clock generation unit 49; A TU pointer in a synchronous multiplexing device having a transmission V5 clock generator 49 which receives a V5 position clock from the buffer and receives a transmission clock and generates a compensated transmission V5 clock in consideration of address differences according to reset and buffer reset. V5 position clock compensation circuit according to buffer reset. The clock generator of claim 1, wherein the transmission V5 clock generating unit (49) comprises: a binary counter (51) for demounting a predetermined initialization value when the buffer reset signal is input, and counting according to a TU clock; An AND gate 52 that multiplies the output of the binary counter; And a multiplexer (55) for receiving a V5 clock from logic 1 and a buffer and selecting the V5 clock according to the output of the AND gate. The V5 position clock compensation circuit according to a TU pointer buffer reset in a synchronous multiplexer.