JP2946863B2 - Parity counting circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parity counting circuit for a digital transmission signal, and more particularly to a parity counting circuit applied to monitor parity of a digital transmission signal multiplexed in a multiframe.

[0002]

2. Description of the Related Art Conventionally, m bits (m is 2) in one frame.
FIG. 3 shows a case where, in a multi-frame digital transmission signal composed of n (n is an integer of 2 or more) frames accommodated in n frames, the parity of n frames for any one bit in the frame is counted. Such a circuit was used.

[0003] The input signal Si transmitted serially is input to a data extracting circuit 4, and a bit for performing a parity count out of m bits in one frame is extracted according to an extracting timing signal. The extracted data is stored in the storage circuit 5 until n frames are prepared. In this case, data is stored bit by bit according to the address indicated by the address counter 6 reset by the reset signal input at the beginning of the frame. When the parity data for n frames is completed, the data is read from the storage circuit 5 and input to the alignment circuit 7. The alignment circuit 7 rearranges the input parity data one bit at a time into an n-bit parallel signal and sends it to the parity counter 8. In the parity counter 8, “1” in n bits in units of n bits
For example, in the case of odd parity, if the bit number of “1” is odd, “1” is output as the parity count signal Po, and if it is even, “0” is output as the parity count signal Po. .

A bit error in a transmission path is detected by comparing the parity count signal value with a parity count signal value multiplexed into a digital transmission signal sequence and transmitted from a transmission destination.

[0005]

In the above-described conventional parity counting circuit, in order to count the parity of bits developed into a multi-frame, parity data in units of one frame is temporarily stored in a storage circuit, and then the multi-frame is counted. Since the parity is counted by reading the data at the time when the data has been collected, an alignment circuit for converting data for multiple frames into parallel signals is required. Further, when the number of bits for performing the parity count becomes longer, the scale of the storage circuit and the address counter becomes larger, and the configuration of the alignment circuit becomes more complicated.

An object of the present invention is to provide a parity counting circuit having a simple circuit configuration even if the number of bits for performing parity counting becomes long.

[0007]

According to the present invention, a parity counting circuit according to the present invention converts an input digital data signal composed of n (n is an integer of 2 or more) frames having a plurality of bits in one frame into each frame. In a parity counting circuit that extracts a specific one bit and performs n-bit parity counting,
Storage means operating in response to a clock signal synchronized with each bit of the input digital data signal and a frame timing signal synchronized with the frame, and outputting the input digital data signal as n digital data signals sequentially delayed by one frame at a time. And latch means for receiving the n digital data signals and extracting and holding a specific bit of each frame in response to a latch timing signal. Further, the storage means has at least n
A first port that operates in response to the clock signal and the frame timing signal to delay one frame between input and output, inputs the input digital data signal to a first port on the input side, Side k (k is 1
≦ k ≦ n−1) port and the (k + 1) th input side
May be configured by a storage circuit having a FIFO structure which is connected to each of the ports.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The digital transmission signal Si input here is 1
A serial data signal containing m bits (m is an integer of 2 or more) in a frame, and is composed of n (n is an integer of 2 or more) frames. N arranged over multiple multiframes
Consider a case where parity counting is performed on bit parity data.

Now, the input digital transmission signal Si
Is input to the storage circuit 1. The storage circuit 1 generally includes a FIFO (First In First Out)
It has a plurality of independent input / output ports, and can independently perform writing and reading operations to and from a storage circuit.

Now, a clock Pc synchronized with the data stream of the input signal Si and a frame timing signal Pf synchronized with the head of the frame are input to the recording circuit 1, and the input / output ports are connected as shown in FIG. The recording circuit 1
Output data S11 to Sn1 from the n output ports
Are output as data strings delayed by one frame, respectively, as shown in FIG.

The n data strings S11 to Sn1 are represented by S
When the eleventh data string outputs the N-th frame, it can be seen that the first to N-th frames are developed in the order of Sn1 to S11. That is, if data is extracted from the n data strings at the same timing, data for n frames can be extracted at a time. Therefore, as shown in FIG. 1, by supplying n data strings to the latch circuit 2 and taking in the latch circuit 2 in accordance with the latch timing signal P1 synchronized with a specific bit for performing parity counting in the frame, 1 A specific bit of m bits in the frame is extracted, and n-bit data S12
To Sn2 are obtained.

The n-bit data S12 to Sn2 captured by the latch circuit 2 are sent to the parity counter 3, and the number of "1" bits in the n bits is counted. For example,
In the case of odd parity, if the number of bits of “1” is odd, “1” is output as the parity count signal Po, and if it is even, “0” is output. By comparing the parity count signal value with the parity count signal value multiplexed into the digital signal sequence and transmitted from the transmission destination, a bit error in the transmission path can be detected.

[0014]

As described above, according to the present invention, by using a combination of a storage circuit having a FIFO structure having a plurality of input / output ports and a latch circuit, a specific bit for performing parity counting over a multi-frame is obtained. Since the data can be latched at a time and extracted as parity data, a simple circuit configuration is obtained. Further, by changing the latch timing to the latch circuit, there is an effect that the parity count can be easily performed for an arbitrary bit in the frame.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a timing chart of each signal shown in FIG.

FIG. 3 is a block diagram illustrating an example of a conventional parity counting circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Storage circuit 2 Latch circuit 3 Parity counter Si Input digital data signal S11-Sn1 Digital data signal output from storage circuit 1 S12-Sn2 Data fetched by latch circuit 2

Claims (2)

(57) [Claims] 1. A frame having a plurality of bits in one frame
(N is an integer of 2 or more) In a parity counting circuit that extracts a specific bit of each frame from an input digital data signal composed of frames and performs n-bit parity counting, each bit of the input digital data signal Storage means operating in response to a clock signal synchronized with the frame and a frame timing signal synchronized with the frame and outputting the input digital data signal as n digital data signals sequentially delayed by one frame at a time; And a latch means for receiving a signal and extracting and holding a specific bit of each frame in accordance with a latch timing signal. 2. The storage means has at least n ports on an input side and an output side, respectively, and operates according to the clock signal and the frame timing signal to delay one frame between input and output. The input digital data signal is input to a first port on the input side, and the k-th port (k is an integer of 1 ≦ k ≦ n−1) on the output side and the (k + 1) -th port on the input side are respectively connected. 2. The parity counting circuit according to claim 1, wherein the parity counting circuit is a storage circuit having a FIFO structure connected thereto.