JPH03198544A - Parity count circuit - Google Patents

Abstract

PURPOSE:To extract a data from a memory in a required timing even when the result of entire parity count is produced over plural frames by integrating the parity count of a same frame number and a same channel number into a memory sequentially. CONSTITUTION:An outputted parity count data is inputted to a 2nd serial parallel converter 3, where parallel data in the unit of one frame are arranged and collected in the unit of frames and outputted. Then a succeeding parity count data by one frame is ORed with a one-preceding parity count data of a same frame number and a same channel number read from a memory 7 at an OR circuit 5. The ORed and integrated data is stored in a same address as read from the memory 7 and written in the memory 7. Thus, the parity count data of a same frame number and of a same channel is written in the same address in the memory 7 as a data integrated in the unit of frames.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to line termination technology in a digital transmission network, and particularly to a circuit that is effective in monitoring the parity of multiplexed transmission signals.

[Conventional technology]

Conventionally, in digital transmission signals, N
When performing parity counting on a channel-by-channel basis for a signal multiplexed in bits on a channel-by-channel basis, the circuit shown in FIG. 4 is used. That is, in the figure, it is composed of a serial-parallel converter 11 that converts a serially transferred signal into an N-bit parallel signal, and a parity counter 12 that counts the odd or even parity of the N-bit parallel signal. has been done.

According to this configuration, a serially transferred digital data signal string is input to the serial/parallel converter 11 and converted into an N-bit parallel signal. Next, this converted signal is input to the parity counter 12, which counts the number of "1" bits among the N bits in units of N bits.In the case of odd parity, the number of "1" bits is an odd number. If the number is even, output “1”, and if the number is even, output “°0′′
Output. Also, in the case of even parity, °“1”
If the number of bits is an even number, it outputs "1"°, and if it is an odd number, it outputs rr OI+. By comparing this parity count value with the N-bit parity count value multiplexed with the previous data signal and sent from the destination, it is possible to detect a focus error on the transmission path.

(Problems to be Solved by the Invention) The conventional parity counting circuit described above has a problem in that it can only perform a parity check in units of I frames because it immediately outputs the parity count value. Therefore, in the signal sequence multiplexed in frame units, N
When performing parity counting for each channel of bits,
It is necessary to accumulate the parity count value for each frame.
Conventional circuits cannot handle this.

An object of the present invention is to provide a parity counting circuit that makes it possible to obtain parity counting results over multiple frames.

[Means to solve the problem]

The parity counting circuit of the present invention includes a first serial-to-parallel converter that converts a signal string obtained by multiplexing frames consisting of N-bit channels into parallel data for each channel, and a parity counting circuit for each channel. a second serial-to-parallel converter that arranges the parity count values of each channel in frame units; a memory that stores the parity count values of each frame at a required address for each channel; The apparatus includes an OR circuit that performs a logical sum of the parity count counted in the next frame corresponding to the stored parity count and the stored parity count and stores the result in the memory.

[Operation] In this configuration, parity is counted in units of N-bit channels within one frame, and the counted values are arranged in units of frames, sequentially ORed, and stored in memory.
It becomes possible to accumulate parity values for each channel in units of multiple frames.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

In the figure, 1 is a first serial-to-parallel converter that converts serially transferred signals into N-bit parallel signals for each channel, and 2 is a parity counter that performs odd or even parity counting of N-bit parallel signals. This is vessel 2. A second serial-to-parallel converter 3 is connected to the parity counter 2 for bundling the parity count data for each channel into parallel data in units of one frame. A latch circuit 4 for temporarily holding data is connected. Furthermore, there is an OR circuit 5 for integrating the parity count value of one frame before read from the memory 7 and the value counted this time, which will be described later, and a one-clock circuit for writing the accumulated parity count value to the same address in the memory. A storage circuit (memory) 7 for storing the N-bit channel parity count value for each frame is connected through the flip-flop circuit 6. This memory 7 has an address counter 8 for setting memory addresses corresponding to multi-frames.

On the other hand, the flip-flop circuit 6 is operated by inputting a clock, and this clock is input to the divider-by-2 divider 9.
It is configured to operate by inputting the data to the memory 7 and address counter 8 via the memory 7 and the address counter 8.

Next, the circuit operation will be explained using the data signal frame format shown in FIG. 2 and the operation timing diagram shown in FIG. 3.

As shown in FIG. 2, it is assumed that data signals are input in a frame-by-frame multiplexed form according to frame numbers. Here, one frame has 15 bits and is configured as a multiframe consisting of five or more frames. For this data signal, the sum of parity counts for the same channel with the same frame number is calculated.

First, the data stored in the memory 7 is cleared at the timing of starting parity counting.

The serially transferred digital data signal string is input to the first serial/parallel converter 1 and converted into an N-bit parallel signal for each channel. Next, this signal is input to a parity counter 2, which counts the number of l' bits out of N bits for each channel. In the case of odd parity, if the number of bits in °゛1°° is an odd number, "l゛".

If the number is even, output “0”°. Further, in the case of even parity, if the number of bits of "1°" is an even number, "1°" is output, and when the number of bits of "1°" is an odd number, "0" is outputted.

The output parity count data is input to the second serial-to-parallel converter 3, where it is arranged into parallel data in units of one frame (in units of 15 bits in this embodiment) and converted in units of frames. It is bundled and output. This data is temporarily held in the latch circuit 4.

And logical sum circuit 5. Parity count data for one frame is stored in the memory 7 for each channel through the flip-flop circuit 6.

Parity counting is similarly performed for the next frame. Then, the parity count data for the next one frame is once held in the latch circuit 4, and then read out from the memory 7 for the previous (previous) same frame number and same channel number. A logical OR is performed on the parity count data and the OR circuit 5.

As shown in the timing chart shown in FIG. 3, the logical ORed and accumulated data is delayed by one clock by the flip-flop circuit 6 which uses the clock frequency divided by the frequency divider 9. The data is stored in the same address that was previously read from the memory 7 and written to the memory 7.

As a result, as shown in FIG. 3, the parity count data of the same frame number and the same channel is written to the same address in the memory 7 as data accumulated on a frame-by-frame basis.

By repeating this operation of reading and writing to the memory 7, the parity count value for each channel of the signal string input after clearing the memory is stored in the memory 7.
can be accumulated.

The output terminal of the memory 7 is connected to an external output, and data is sent to the outside at a timing before the memory 7 is cleared.

〔Effect of the invention〕

As explained above, the present invention sequentially accumulates the parity count values of the same frame number and the same channel number in the memory, so even when generating the overall parity count result over multiple frames, it is possible to retrieve the parity count value from the memory at the necessary timing. I can do it. Furthermore, bit errors in the transmission path can be detected by comparing the overall parity counting result with the destination parity counting information multiplexed on the transmitted signal string.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the parity counting circuit of the present invention, and FIG.
The figure shows a frame format of a data signal input to the parity counting circuit of the present invention, FIG. 3 is an operation timing diagram of the parity counting circuit of the present invention, and FIG. 4 is a block diagram of a conventional parity counting circuit. ■...First serial/parallel converter, 2...Parity counter, 3...Second serial/parallel converter, 4...Latch circuit, 5...OR circuit, 6・・・
・Flip-flop circuit, 7...Storage circuit (memory)
, 8...Address counter, 9...2 frequency divider, 11
...Serial-to-parallel converter, 12...Parity counter.

Claims (1)

[Claims] 1. A first serial-to-parallel converter that converts a signal sequence obtained by multiplexing a frame consisting of channels of N bits (N is any positive integer) into parallel data for each channel, and a first serial-to-parallel converter for each channel. a parity counter that performs parity counting, a second serial-to-parallel converter that arranges the parity count values of each channel in frame units, and a memory that stores the parity count values of each frame at a required address for each channel. and an OR circuit that calculates the logical sum of the parity count counted in the next frame corresponding to the stored parity count and the stored parity count and stores the result in the memory. Parity counting circuit.