JP2655611B2 - Demultiplexer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is used for demultiplexing means for input signals of a digital transmission apparatus. In particular, the present invention relates to means for matching the phases of a plurality of output signals obtained by demultiplexing an input signal.

〔Overview〕

The present invention provides a means for demultiplexing an input signal of bits with irregular timings, by simultaneously cutting out bits of a predetermined width from a time zone in which all of a plurality of input bits are stable, thereby achieving demultiplexing. The required circuit configuration can be simplified.

[Conventional technology]

Conventionally, input signal demultiplexing means of a digital transmission device of this kind, when there is a phase difference in a frame between a plurality of input signals, corrects these differences to match the phase of the frame before each input signal. Was demultiplexed.

[Problems to be solved by the invention]

Such a conventional example is composed of a memory, a write counter and a read counter. An elastic memory, a demultiplexing circuit, which corrects the phase difference of frames between input signals to match the phases of those frames, and includes them. Since a control counter is required, there is a disadvantage that the circuit scale becomes large.

An object of the present invention is to eliminate such a drawback and to provide a demultiplexing apparatus having a simple circuit configuration.

[Means for solving the problem]

The present invention provides a first counter that is counted at a timing corresponding to a frame synchronization signal extracted from an input signal, and temporarily stores each bit of the input signal in a predetermined area in the order of arrival according to an output of the first counter, N memories for reading the temporarily stored bits in the order of arrival, and M (M = N / M) which time-division multiplexes every L data of bits related to the bits read from the N memories. (L) multiplexing circuit (103-106) for separating the input signal into M parallel data strings. A second counter for counting the timing of simultaneously extracting the values of the M bits from one time zone not including the time at which the value changes, and providing the output of the own counter as a read clock for the multiplexing circuit; And wherein the door.

[Action]

The incoming time-division multiplexed input signal is written into N memories by controlling write timing with a frame period signal detected from the input signal. The output signal of this memory is input to every M multiplexing circuits, and every L multiplexing circuits are time-division multiplexed by controlling the timing of the multiplexing circuits so as to have a phase relationship for selecting a stable band of data output from the memory. . As a result, the phases of the frames between the output signals are matched, and the output signals are demultiplexed into M output signal trains.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of this embodiment.
A case where input signals are demultiplexed into four signals by 16 memories will be described.

In this embodiment, as shown in FIG. 1, a data writing counter 102 as a first counter which counts at a timing corresponding to a frame synchronization signal extracted from an input signal.
In response to the output of the first counter, N memories 101 for temporarily storing each bit of the input signal in a predetermined area in the order of arrival, and reading out the temporarily stored bits in the order of arrival.
And M (M = N / L) multiplexing circuits 103, 104, 105 and 106 for time-division multiplexing every Lth data of bits read from the N memories 101, From one time slot not including the time at which the value of the M bits input to each of the
Count the timing to extract the values of all bits at once,
A multiplexing counter 107 serving as a second counter for providing the output of its own counter as a read clock for the multiplexing circuit.

Next, the operation of this embodiment will be described. The input signal 001 is sequentially stored and output for each bit to the 16 memories 101 according to the write control signal 002 from the data write counter 102. The data write counter 102 is controlled by a frame synchronization signal 003 detected from the input signal 001. As shown in FIG. 2, the multiplexing counter 107 controls the phase relationship in which the multiplexing circuits 103 to 106 controlled by the multiplexing counter 107 always select the data stable band of the memory output signal 005 with respect to the frame synchronization signal 003. The data written in the 16 memories 101 are grouped every fourth data while being controlled by the frame period signal 004 supplied from the device so that
In accordance with the multiplex control signal 010 from 107, each of the multiplex circuits 103-1
The output signals 006 to 009 are obtained by multiplexing the input signal 001 at 06 and demultiplexing the input signal 001 into four lines.

 The operation of this embodiment will be further described with reference to the drawings.

FIG. 3 shows an input signal 001 and output signals 006 to 009 output from the multiplexing circuits 103 to 106.
The multiplexed signals that are input in a time-division multiplexed manner as C, D, E, F... Are respectively referred to as “A, E, I, M”, “B, F,
FIG. 7 shows a state in which four time-division multiplexed parallel signals of “J, N”, “C, G, K, O”, and “D, H, L, P” are demultiplexed and output. In this embodiment, even if the input data is not in the state but in a state where the phase is shifted, in this embodiment, the multiplexing circuits 103 to 106 multiplex and output according to the control signal of the multiplexing counter 107. A uniform output signal can be obtained.

FIG. 4 shows data (input signal 0) input to the memory 101.
01) and 16 data (memory output signal 005) output from the memory 101. As described above, the memory 101 writes an incoming input signal and outputs data at a long time interval until the next write timing. FIG. 5 is a diagram showing a time relationship between input data and output data in the multiplexing circuit 103. Multiplex circuit 10
3 outputs the signals of A, E, I, and M at the timing shown by the broken line. The timing indicated by the broken line has a phase relationship for selecting the stable band of the output data of the memory 101 shown in FIG. 2, and is controlled by the multiplex control signal 010 supplied from the multiplex counter 107.

Thus, in the present embodiment, even if a phase shift occurs in the input signal, it is possible to correct the phase shift and generate a demultiplexed signal having the same phase.

〔The invention's effect〕

As described above, the present invention multiplexes the data output stored for each bit in the memory with a plurality of multiplexing circuits, and thus corrects the phase difference of frames between a plurality of output signals to a digital transmission device, Can be simplified further.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a waveform chart showing the operation of the embodiment of the present invention. FIG. 3 is a diagram showing examples of input signals and output signals of the embodiment of the present invention. FIG. 4 is a diagram showing a relationship between an input signal and an output signal of a memory according to the embodiment of the present invention. FIG. 5 is a diagram showing a relationship between an input signal and an output signal of the multiplexing circuit according to the embodiment of the present invention. 001: input signal, 002: write control signal, 003: frame synchronization signal, 004: frame cycle signal, 005: memory output signal, 006 to 009: output signal, 010: multiplex control signal, 101 ..., A memory, 102, a data write counter, 103 to 106, a multiplex circuit, 107, a multiplex counter.

Claims (1)

(57) [Claims] 1. A first counter (102) counting at a timing corresponding to a frame synchronization signal extracted from an input signal.
N memories (101) for temporarily storing each bit of the input signal in a predetermined area in the order of arrival in accordance with the output of the first counter, and reading out the temporarily stored bits in the order of arrival.
And M data (M = N / M) that time-division multiplexes every L data of bits read from the N memories.
L) multiplexing circuit (103-106) for separating an input signal into M parallel data streams, wherein M bits of M bits input in the same order as each of the multiplexing circuits are provided. A second counter that counts the timing of simultaneously extracting the values of the M bits from one time zone that does not include the time at which the value changes, and provides the output of its own counter in common as a read clock for the multiplexing circuit ( 107) A demultiplexer characterized by comprising: