JPH0220136A - Delaying equalizing circuit - Google Patents

Abstract

PURPOSE:To restore to an original data column even when the connecting condition of the output line of a data column distributed at a transmitting side and the input line at a receiving side is changed by decoding the difference in the frame arrangement from the high speed encoding data obtained by equalizing the delaying difference in the transmission line and executing the circuit constitution to replace the arrangement of the data again. CONSTITUTION:The transmitting multi-frame of respective channels has the information inherent to respective channels to designate the bit rate allocation of the encoding transmitting channel sent for respective channels. A control information decoding circuit 9 outputs the signal to replace the sequence by the decoding of the service bit included in the high speed encoding data of the output of a front step data selecting circuit 7. A rear step data selecting circuit 10, in accordance with the sequence replacing control signal, reads the data from delaying memories 5-1 to 5-4 again and outputs the high speed encoding data combined to the sequence of the original high speed encoding data to an output terminal 11. At the front step data selecting circuit 7 and the rear step data selecting circuit 10, the smaller signal than the delaying memory respectively at the relation of the reading, arrangement and high speed processing from the same delaying memories 5-1 to 5-4 is provided according to the necessity.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a delay equalization circuit, and in particular, a circuit that equalizes the mutual delay between data transmitted in parallel via a plurality of transmission paths, which is a frost in delay time, and The present invention relates to a delay equalization circuit that restores the order of data transmitted in parallel.

[Conventional technology]

Recently, in image transmission and the like, a method has been used in which high-speed encoded data is speed-converted, distributed over multiple transmission paths, and transmitted in parallel. As a basic frame structure of such high-speed encoded data, there is a frame structure based on CCITT Recommendation Y, 22.1 as shown in the format diagram of FIG. This figure shows the basic data frame structure for a 64 K b/S channel, and one multiframe data consists of 16 frames (FN=O to 15).
Each frame consists of 80 octets, with service bits containing frame-specific information in a specified number of octets.

Note that an octet is an information unit composed of 8 bits. Now, the number of channels for transmitting this multi-frame data is Q
= 4, when transmitting low-speed data, the high-speed encoded data frame FN = O as shown in the format diagram in Figure 3.
Each frame of ~15 is decomposed into 4 transmission subframes. Each transmission subframe consists of one frame 8 in FIG.
A frame consisting of 0 octets is extracted every 4 octets, and 20 octets constitute one transmission subframe. Here, if one transmission subframe is 2 bits, this high-speed encoded data is converted to 1/4 low-speed encoded data and distributed to each transmission channel chi to ch4. A multiframe consisting of 16 transmission subframes of each distributed transmission channel is called a transmission multiframe. Here, the first number in parentheses of the high-speed encoded data and low-speed encoded data frames represents the frame number, and the next number is the transmission channel number (hereinafter referred to as chNo).
represents. In addition, the start bits of the first and next multiframes of chi to ch4, which have a transmission multiframe length of M bits, are F1-IFl-2, ~F4, respectively.
-1, F4-2. Now, the delay experienced by the data of each transmission channel on the transmission path is as shown in the time chart of FIG. 4(a), for example.

Now, let us define the maximum delay and length between the four transmission channels as N
Then, the relationship between M and N is the start bit F of ch3.
3-1 is set in the range M>2N in order to prevent erroneous synchronization adjustment with the start bit F2-2 of ch2.

The operation of the conventional delay equalization circuit when receiving the transmission data of each transmission channel described above will be explained with reference to the block diagram of FIG. Note that the figure illustrates a case where the number of transmission channels Q=4. Conventional delay equalization circuits
Transmission line clock input terminal 1 common to low-speed encoded data of h4, each transmission data input terminal 2-1 of chi to ch4
2-4 and a high-speed clock input terminal 3 for high-speed encoded data. In addition, synchronization circuits 4-1 to 4-4 detect frame synchronization and multi-frame synchronization signals of each transmission data of chi to ch4, and data of each input channel is controlled by a delay control circuit 6 to be described later. Delay memory 5-1 to 5 for writing to and reading addresses
-4. The delay control circuit 6 includes synchronous circuits 4-1 to 4-4.
Write pulses are output in the order of the transmission subframe data arrangement of each transmission channel based on the high speed clock and transmission line clock common to each synchronization signal detected at -4. Further, the delay control circuit 6 determines the maximum delay difference bit N between transmission multi-frames of each transmission channel as shown in the time chart of FIG. 4(b), and delays the read pulse by bits from this N bit. Align each channel to the same phase.

The pre-stage data selection circuit 7 sequentially reads the data of the transmission subframes from the delay memories 5-1 to 5-4 based on this read pulse. Specifically, as shown in the time chart of FIG. The same data consisting of bits (0.1) of the delay memory 5-1 is repeatedly read out four times at high speed. Other delay memory 5-2.5-3.5-4
Similarly, the same data (0, 2), (0, 3), and (0, 4) are repeatedly read out four times at high speed. Furthermore, in the pre-stage data selection circuit 7, the same data that is repeated four times from the delay memories 5-1 to 5-4 is shifted and extracted bit by bit, and is extracted by bits (0, 1), (0, 2>, (0 ,3),
It takes the form of outputting an array of (0,4) high-speed encoded data. Note that the readout order using the readout pulse of the delay control circuit 6 described above is as follows:
, ch2. cl-+3. In order of ch4, FN=1
．． FN=2...FN=15 are output in the same procedure. Therefore, the output data of the pre-stage data selection circuit 7 is outputted in time series in real time in this reading order, and the high-speed encoded data as shown in FIG. 6 is restored.

[Problem to be solved by the invention]

However, in conventional delay equalization circuits, which output line of a data string distributed to a plurality of transmission lines on the transmitting side is connected to which input line on the receiving side is uniquely fixed.

An object of the present invention is to provide a delay circuit that can restore the data array of the original high-speed encoded data even if the data string distributed on the transmitting side is transmitted by arbitrarily changing the transmission path.

[Means to solve the problem]

The delay equalization circuit of the present invention converts the speed of high-speed encoded data on the transmitting side, which has a multi-frame configuration of a plurality of frame data each having frame-specific service bits, and then distributes the data to 0 transmission paths for transmission. Q delay memories each input and store each of the low-speed encoded data, and the start bit of each multi-frame is determined based on the multi-frame synchronization signal detected from each of the Q low-speed encoded data. The delay difference is detected from the phase of the start bit of each transmission line and Q synchronous circuits that output
a delay control circuit that outputs read signals with no frame data read time difference between the Q transmission lines in a predetermined order; and a plurality of frame data inputted with the high-speed read signal and read out sequentially from the Q delay memories. and a pre-stage data selection circuit that restores the first high-speed encoded data to the first high-speed encoded data, the delay equalization circuit divides the first high-speed encoded data into a plurality of frame data having a predetermined delay and outputs the 2Q- Two delay circuits and a control signal of a control information decoding circuit that decodes a plurality of service bits included in the first high-speed encoded data and outputs a control signal instructing frame arrangement replacement, The second data selection circuit outputs second high-speed encoded data in which the data read from the delay memory is rearranged into the same frame arrangement as the high-speed encoded data on the transmitting side.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

Note that this embodiment is also illustrated with the number of transmission channels Q=4. In the figure, transmission line clock input terminal 1, transmission data input terminals 2-1 to 2-4, high-speed clock input terminal 3, synchronous circuits 4-1 to 4-4, delay memories 5-1 to 5-4, and delay control Circuit 6, the pre-stage data selection circuit, has the same configuration and function as the conventional example. Furthermore, in this embodiment, the control information decoding circuit 9 and the delay circuit 8-1. ~8- (2Q-2) and a subsequent data selection circuit 10 are added.

As described above, the transmission multiframe of each channel has a plurality of service bits, and has information unique to each channel that specifies the bit rate allocation of the encoded transmission media sent for each channel. Therefore, as long as the arrangement of the basic data frame itself on the transmitting side does not change, even if the transmission path of distributed low-speed encoded data is replaced, the state of replacement can be detected by decoding this unique information. The control information decoding circuit 9 decodes the service bits included in the high-speed encoded data output from the pre-stage data selection circuit 7 and outputs a signal for rearranging the order. As a further supplement, suppose that chi and ch2 are exchanged, and the arrangement of high-speed encoded data output from the front-stage data selection circuit 7 is (0, 2) (0, l) < 0.3) (0, 4). The control information decoding circuit 2 detects the service bits of the basic data frame structure predetermined on the transmitting side from each transmission subframe, regardless of each transmission subclaim that is sequentially input, and determines whether the data sent by chl is ( 0,2), it is decoded that the data sent on channel 2 is (0,1). This decoding result shows that it is a normal array (0.1
>(0,2)(0,3>(0,4>) A read signal of the address of the delay memories 51 to 5-4 is output.

The subsequent data selection circuit 10 includes the control information decoding circuit 9 described above.
According to the order reversal control signal decoded by
Read data again from delay memories 5-1 to 5-4,
The high-speed encoded data rearranged in the order of the original high-speed encoded data is output to the output terminal 11. It should be noted that the preceding data selection circuit 7 and the subsequent data selection circuit 10 may each be provided with a smaller memory than the delay memory, if necessary, in order to read from the same delay memories 5-1 to 5-4, arrange them, and perform high-speed processing. There is.

〔Effect of the invention〕

As explained above, according to the present invention, when converting high-speed encoded data to low-speed encoded data and distributing it to multiple transmission paths for parallel transmission, first, the delay differences of the transmission paths are equalized and the resulting data is obtained. The difference in frame arrangement is deciphered from the high-speed encoded data. By using a circuit configuration that rearranges the data array again based on the decoding result, even if the connection state between the output line of the data string distributed on the transmitting side and the input line on the receiving side is arbitrarily changed, the original data will be preserved. This has the effect of restoring columns.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG.
Figure 3 is a format diagram for explaining high-speed encoded data, Figures 4 (a) and (b) are time charts showing the delay experienced by transmission data and its equalization, and Figure 5 is a conventional delay etc. FIG. 6 is a block diagram of the conversion circuit and is a time chart of the conventional example shown in FIG. l...Transmission line clock input terminal, 2-1.2-2゜~
2-4...Transmission data input terminal, 3...High speed clock input terminal, 4-1.4. , -2. ~4-4... Synchronous circuit, 5-1.5-2. ~5-4...delay memory, 6
. . . Delay control circuit, 7 . . . Pre-stage data selection circuit, 9
. . . Control information decoding circuit, 1o . . . Post-stage data selection circuit, 11 . . . Output terminal.

Claims (1)

[Claims] The high-speed encoded data on the transmitting side, which has a multi-frame configuration of multiple frame data each having frame-specific service bits, is distributed to Q transmission paths after speed conversion, and each transmitted low-speed encoded data is input. and Q delay memories for storing each, and Q synchronization circuits that output a start bit of each of the multiframes based on a multiframe synchronization signal detected from each of the Q low-speed encoded data. , a delay control circuit that detects a delay difference from the phase of the start bit of each transmission line and outputs read signals with no frame data read time difference among the Q transmission lines in a predetermined order; and the high-speed read signal. and a pre-stage data selection circuit for restoring a plurality of frame data sequentially read from the Q delay memories into first high-speed encoded data. 2Q output divided into multiple frame data with a specified delay
- two delay circuits and a control signal of a control information decoding circuit that decodes a plurality of service bits included in the first high-speed encoded data and outputs a control signal instructing frame arrangement replacement; and a post-stage data selection circuit that outputs second high-speed encoded data in which the data read from the delay memory of the transmitter is rearranged into the same frame arrangement as the high-speed encoded data on the transmitting side. Delay equalization circuit.