JPH01228228A - Multiplex frame aligner circuit - Google Patents

Abstract

PURPOSE:To perform the phase alignment of multiplex data by a circuit with a small scale by constituting every part so as to perform output control by generating a delay quantity at every channel based on the phase difference of channel data for a reference phase. CONSTITUTION:The synchronization of a frame is taken from input data multiplexed at a multiplex synchronism detecting part 1, and also, a frame pulse is outputted at every channel corresponding to a specific data position in the frame according to each channel address from a channel address generating part 5. For the frame pulse, the phase difference with the reference phase of a reference phase signal is detected at every channel at a multiplex phase difference detecting part 2. A detected phase difference at every channel is sent to a multiplex delay quantity generating part 3, and the delay quantity corresponding to the phase difference is generated at the part 3. And the generated delay quantity of each channel is sent to a multiplex output control part 4, then, the data of each channel is delayed corresponding to the delay quantity. In such a way, it is possible to always output the data corresponding to the reference phase.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a multiple frame aligner circuit that aligns the frame phase of multiplexed multiple channel data with different phases to a specific reference phase, with the aim of reducing the circuit scale. A multiplex synchronization detector that synchronizes frames and outputs a frame pulse for each channel in response to a specific common data position, and a multiplex synchronization detector that detects the phase difference between the reference phase and each frame pulse for each channel. A phase difference detection section, a multiplex delay amount generation section that generates a delay amount according to the phase difference in each channel, a multiplex output control section that delays each channel data according to the delay amount, and corresponds to the plurality of channels. and a channel address generation section that supplies each address to each section.

[Industrial application field]

The present invention relates to a frame aligner circuit, and more particularly to a multiple frame aligner circuit that aligns frame phases of multiplexed multiple channel data having different phases to a specific reference phase.

In data communication, when receiving data from multiple channels with different frame phases for each channel, it is necessary to align the frames of each channel before processing the received data on each channel. It is often convenient, and from this point of view, frame phasing c
frame alignment) is desired.

[Conventional technology]

FIG. 5 shows a conventionally well-known frame aligner circuit for adjusting the phase of frames for each channel, in which 50 is a separation unit (DMUX), 51, -51 . 52. is a phase difference detection circuit; 527 is a phase matching circuit, in which the multiplexed data is separated into channels CHI to CHn by the separation unit 50, and a specific position of the frame (for example, the frame pulse at the beginning of the frame) is determined for each channel.
The phase difference detection circuit 51. 517, and further detects the phase difference between the position and the reference signal, and each phase matching circuit 521 to 527 delays and outputs each channel data based on the detected phase difference. The phase of each chaffle's data was matched.

[Problem to be solved by the invention]

In the case of a frame aligner circuit for aligning the phases of a plurality of channels as described above, it is necessary to separately provide a phase difference detection circuit and a phase alignment circuit for each channel, which has the problem of increasing the circuit scale.

Therefore, the present invention provides a multiplex frame aligner circuit that adjusts the frame phase of multiplexed multiple channel data having different phases to a specific 71 phases, and the circuit size can be reduced (
The purpose is to

[Means to solve the problem]

In order to achieve the above object, in the multiple frame aligner circuit according to the present invention, as conceptually shown in FIG. a multiplex synchronization detector 1 that outputs pulses for each channel; a multiplex phase difference detector 2 that detects a phase difference between the reference phase and each frame pulse for each channel; A multiplex delay amount generation section 3 that generates a delay amount, a multiplex output control section 4 that delays each channel data according to the delay amount, and a channel address generation section 5 that provides each section with addresses corresponding to the plurality of channels. It is equipped with.

[For production]

In the present invention, first, the multiplex synchronization detector 1 synchronizes frames from multiplexed input data, and generates a frame pulse corresponding to a specific common data position within the frame according to each channel address from the channel address generator 5. is output for each channel. The phase difference between this frame pulse and the reference phase of the reference phase signal is detected for each channel in the multiple phase difference detection section 2. The detected phase difference for each channel is sent to the multiplex delay generation section 3, where a delay amount corresponding to the phase difference is generated.

Then, the generated delay amount for each channel is sent to the multiplex output control section 4, and the data of each channel is delayed according to the delay amount.

This makes it possible to always output data matching the reference phase.

〔Example〕

FIG. 2 shows an embodiment of the multiplex frame aligner circuit according to the present invention. In this embodiment, the multiplex synchronization detector 1 collects 16 channels of multiplexed data (serial data) and channel addresses. It is composed of a synchronization detection circuit 1a that receives each channel address from the generation section 5 and generates a frame pulse FP. An AND gate 2b inputs the inverted signal of the Linopple carry output RC and the reference phase signal ■ and supplies it to the load terminal L0 of the counter 2a, and the output of the counter 2a, the channel address of the channel address generator 5, and the frame pulse FP. RAM 2 receives the signal and generates a phase difference.
It is composed of c. Further, the multiplex delay amount generation unit 3
A selector 3a that selects the above phase difference signal, a RAM 3b that receives the output of this selector 3a and each channel address to generate a counter initial value, and a ripple carry that receives the counter initial value and counter clock CK■. It is composed of a counter 3C that sends a signal RC to a selector 3a and sends a count value to the selector 3a and a RAM 4a that constitutes the multiplex output control section 4. When the selector 3a receives the ripple carry signal RC, it selects the output of the RAM 2c. , otherwise select the output of counter 3C and press R
It is designed to be given to AM3b. Multiple output control section 4
The RAM 4a successively outputs/writes data multiplexed at addresses determined by each channel address and the output from the counter 3c. The channel address generator 5 generates a clock C according to the 16 channel data in this embodiment.
Hexadecimal counter that counts K■5. a (initial value “
0”).

Figure 3 shows the frame phase of data before/after phase adjustment, and Figure 4 shows a time chart of phase adjustment for channel CH8 in particular. explain.

First, the hexadecimal counter 5a of the channel address generation section 5
load terminal. Using the load signal that is input when the data of the first channel arrives at , the addresses for 16 channels from "0" to "15" are generated in decimal notation shown at the top of Fig. 3 (a) and (b). and supplies it to each section 1 to 4. still,
The clock CK■ is a clock having the same speed as each channel data.

Next, the multiplex synchronization detector 1 synchronizes the data of 16 channels, detects the above frame pulse FP (in this case, one before the leading data D1), and writes the data in the RAM 2c of the multiplex phase difference detector 2. Output to enable terminal WE.

The multiple phase difference detection unit 2 uses the reference phase signal ■ shown in the time chart of FIG. Start counting by ■, and RA
Frame pulse F is applied to write enable terminal WE of M2c.
When P is input, the count value "X+2" (in the case of CH8) of the counter 2a at this time is written as a value indicating the phase difference to the address "7" of the RAM 2c indicating the channel CH8 generated by the counter 5a.

In this way, the phase difference between the reference phase signal ■ and the frame pulse FP of each channel is sequentially held in each channel address of the RAM 2c, and then when the corresponding channel address is reached, it is read out from the RAM 2c and sequentially The signal is output to the multiplex delay amount generation section 3.

For example, channel CH8 input to the multiplex delay generation unit 3
The phase difference 'X+-2' for
through a to the channel address “7” of RAM3 b.
This is done for each channel, and further,
Next, when the channel address reaches "7", it is read out and given as the initial value of the counter 3c.
Then, by the clock CK■ in FIG. 4, the initial value "X+2" read from the RAM 3b is loaded and starts counting up.
It is given as the write address of the RAM 4a, and is temporarily held again at the channel address "7" of the RAM 3b through the selector 3a. Therefore, the value of address "7" is incremented by "1" each time it is accessed.

Thereafter, in the same manner, the phase difference of each channel (the value read from RAM2c and written to RAM3b) is read out according to the channel address and given to the counter 3C as each initial value, and in the case of channel CH8, the count value "X+
Sequentially load up to 19”, count up, and load RAM4a
is given as the data write address.

In the RAM 4a, as shown in FIG. 4, the address "X" received from the counter 3C when the channel address is "7" is
After reading the previous data held at +3'', write data D of channel CH8, and then write the data DIM corresponding to the count value - address "X+19°" in sequence.
When the ripple carry signal RC is output from the counter 3c, the phase difference “X+2” held in the RAM 2c is transferred from the selector 3a to the RAM 3 again.
When the channel address is “7”, it is read out and given as the initial value of the counter 3C, and the count “X” is written to
+3” to the RAM 4a as a successive address, the data D written at address “X+3”
, and then write data DI4. Furthermore, RA
The write/read address of M4a is a combination of the address from the channel address generator 5 and the address from the counter 3C.

Thereafter, the same read operation is repeated for each channel, and in the case of the data of channel CH8, the phase of the leading data can be matched with the reference phase signal (2) by delaying "17" data.

〔Effect of the invention〕

As described above, according to the multiple frame aligner circuit according to the present invention, each part is configured to be multiplexed so that a delay amount is generated for each channel and output control is performed based on the phase difference of each channel data with respect to a reference phase. Therefore, phase alignment of multiplexed data can be achieved with a small-scale circuit.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram of a multiple frame aligner circuit according to the present invention. FIG. 2 is a block diagram showing an embodiment of a multiple frame aligner circuit according to the present invention. FIG. 3 is a data frame configuration before and after phase alignment. 4 is a time chart illustrating phase alignment of channel CH8 as an example. FIG. 5 is a block diagram illustrating a conventional frame aligner circuit. In FIG. 1, 1...Multiple synchronization detection unit, 2...Multiple phase difference detection unit, 3...Multiple delay amount generation unit, 4...Multiple output control unit, 5...Channel address generation Department. In the figures, the same reference numerals indicate the same or corresponding parts. Principle diagram of the present invention Figure 1 A real light array of the present invention Figure 2 Conventional example Figure 5

Claims (1)

[Claims] A multiple frame aligner circuit that aligns the frame phase of multiplexed multiple channel data having different phases to a specific reference phase, the circuit synchronizing the frames from the data and aligning the frames to a specific common data position. A multiplex synchronization detector (1) correspondingly outputs a frame pulse for each channel; a multiplex phase difference detector (2) that detects a phase difference between the reference phase and each frame pulse for each channel; a multiplex delay amount generation unit (3) that generates a delay amount according to the phase difference in the channels; a multiplex output control unit (4) that delays each channel data according to the delay amount; A multi-frame aligner circuit comprising: a channel address generating section (5) for supplying each address to each section.