JPS61171246A - Detection circuit for out of synchronism - Google Patents

Abstract

PURPOSE:To detect out of synchronism without using a frame pulse and to simplify circuit constitution by providing a comparison circuit comparing data stored in a data storage circuit and sending an error pulse when they are dissident. CONSTITUTION:When a data is synchronized with a clock, the data has a phase relation to the clock, a length L1 of a data converting point is unchanged and the data is coincident with an interval L2 of clock timing. The data like this is split, a part is fed to an FF circuit 6 directly and the rest is fed to an FF circuit 7 via a delay circuit 5 having a delay time (d) within one clock. On the other hand, since a clock is supplied at the overlapped part of the same data to the two FF circuits 6, 7, the same data are outputted independently of the circuit 5. When the data is not synchronized with the clock, even when the two pulses extracted from the circuits 6, 7 are coincident at a moment, they are dissident at the next moment. Then an error pulse is sent from a comparison circuit 8.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement in an out-of-synchronization detection circuit used in a digital signal processing circuit in a digital radio device.

Of the input data and clock, for example, clock P
In some cases, a LL circuit is used for reproduction, and the reproduced clock and data are added to a signal processing circuit to perform processing such as speed conversion of the data.

At this time, if a fault occurs in the PLL circuit, the voltage controlled oscillator in the PLL circuit will free run, and the clock and data will be out of synchronization.

Therefore, there is a need for a circuit that can easily detect out-of-synchronization.

[Conventional technology]

FIG. 3 shows a block diagram of a conventional example of an out-of-synchronization detection circuit.

In the figure, data including a frame pulse is applied from terminal lN-1 to matching circuit l.

On the other hand, the frame counter 2 applies a pulse to the frame pulse generator 3 and the coincidence circuit 1 every time it measures a predetermined number of clocks. Therefore, the former generates a frame pulse and applies it to the coincidence circuit 1 every time a pulse is applied.

Here, if the frame pulse in the data matches the frame pulse added from the frame pulse generator 3, the matching circuit 1 determines that the position of the pulse from the frame pulse generator 3 is correct, and an error occurs. Pulse counting circuit 4
and not sent to frame counter 2.

However, if they do not match, an error pulse is sent to the two circuits. Therefore, the counting circuit 4 issues an alarm when more error pulses are added, and the frame counter 2 generates a pulse that is shifted by one bit from the previous one.

Now, if an error pulse disappears, the position of this pulse is fixed, but if an error pulse is sent out, the position of the pulse from the frame counter 2 is shifted so that it no longer appears.

Therefore, when the data and the clock are out of synchronization, the two frame pulses do not match, so error pulses continue to be sent out, and the counting circuit 4 determines that the synchronization is out of synchronization and sends out an alarm.

[Problem that the invention seeks to solve]

As explained above, since a frame counter, a frame pulse generator, etc. are required to generate frame pulses synchronized with the clock, there are problems in that the circuit configuration becomes complicated and expensive.

Means for Solving Problem C] The above problem is that the input data is divided into first and second data, the first data is directly transmitted, and the second data is
Through a delay circuit within the clock.

In addition to the first and second flip-flop circuits, respectively,
Comparing a data holding circuit that holds the first and second data at the rising or falling time of a clock applied to the first and second flip-flop circuits with the data held by the data holding circuit; When the out-of-synchronization detection circuit of the present invention is composed of a comparison circuit that sends out an error pulse when there is a mismatch, the out-of-synchronization detection circuit utilizes the fact that there is no correlation between them. 7- That is, when the data and clock are in sync.

The data conversion point and clock timing always match.

Therefore, if you sample the overlapping portion of the same data with a clock for two data obtained through a delay circuit of 1 clock or less, synchronous data and data obtained through a delay circuit of 1 clock or less, it is possible to obtain the same data even if there is a delay time. Data is obtained.

However, when in an asynchronous state, the data conversion point and clock timing do not always match.

For this reason, when two pieces of data are compared using the same method as above, they will sometimes match and other times they will not match. As the delay time increases within one clock, the overlapping portion becomes narrower and the probability of mismatch increases.

In other words, it is possible to detect out-of-sync without using frame pulses, which simplifies the circuit configuration.

It will reduce costs.

〔Example〕

The contents of the present invention will be specifically explained below with reference to illustrated embodiments. Note that the same reference numerals indicate the same objects throughout the figures.

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a time chart of FIG. 1, and FIG.
Figure (bl indicates asynchronous time.

Therefore, the operation shown in FIG. 1 will be explained with reference to FIG.

(1) When data is synchronized with a clock, the data has a phase relationship with the clock.

The length Ll of the data conversion point does not change and matches the clock timing interval L2.

Such data is divided, and a part is directly applied to the flip-flop circuit 6, and the rest is applied to another flip-flop circuit 7 via the delay circuit 5 having a delay time d within l clocks (see FIG. 2 (al- (See ■, ■).

On the other hand, since a clock is applied to the two flip-flop circuits 6 and 7 when the same data overlaps (shaded area), the same data is outputted regardless of the delay circuit 5 (see Fig. 2(a)). −〇～■).

Therefore, no error pulse is sent out from the comparator circuit 8.

(2) When data is not synchronized with the clock Since the data flows relative to the clock, the data conversion point L1 and the clock timing interval L2 may or may not match.

Figure 2(b) - ■ and ■ are the positions of the conversion points over a long period of time, but at a certain moment, the flip-flop circuit 6,
Even if the two data extracted from 7 match, they do not match at the next moment. Therefore, an error pulse is sent out from the comparator circuit 8 (see (2) and (2) in FIG. 2).

Note that as the delay time increases, the shaded area in FIG. 2(a) becomes narrower. Therefore, the rate of clock deviation is higher than in the shaded area, and the probability of mismatch is higher.

This makes it possible to detect whether the data and clock are synchronized.

(Effects of the invention) As explained in detail above, since frame pulses are not used to detect synchronization or asynchronousness, the circuit configuration is simplified,
The effect of cost reduction can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
Figure 3 shows a block diagram of a conventional example. In the figure, 5 is a delay circuit, 6.7 is a flip-flop circuit, and 8 is a comparison circuit. No.j TiIJ Country 3 z Kaya 2 Country (α) (b)

Claims (1)

[Claims] Divide the input data into first and second data, add the first data directly and the second data to the first and second flip-flop circuits respectively via a delay circuit within one clock, The first flip-flop circuit at the rising or falling edge of the clock applied to the first and second flip-flop circuits.
and a data holding circuit that holds the second data, and a comparison circuit that compares the data held in the data holding circuit and sends out an error pulse when they do not match. circuit.